389 	const u8 *lane_map;  member
658 		value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
659 			   SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));  in tegra_sor_power_up_lanes()
661 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |  in tegra_sor_power_up_lanes()
662 			 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);  in tegra_sor_power_up_lanes()
665 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
667 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);  in tegra_sor_power_up_lanes()
670 		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
672 		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);  in tegra_sor_power_up_lanes()
737 		value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
738 			   SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));  in tegra_sor_dp_precharge()
740 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |  in tegra_sor_dp_precharge()
741 			 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);  in tegra_sor_dp_precharge()
744 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
746 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);  in tegra_sor_dp_precharge()
749 		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
751 		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);  in tegra_sor_dp_precharge()
816 		u8 shift = sor->soc->lane_map[i] << 3;  in tegra_sor_dp_link_apply_training()
3402 	.lane_map = tegra124_sor_lane_map,
3442 	.lane_map = tegra124_sor_lane_map,
3483 	.lane_map = tegra210_sor_lane_map,
3503 	.lane_map = tegra210_sor_lane_map,
3586 	.lane_map = tegra124_sor_lane_map,
3622 	.lane_map = tegra124_sor_lane_map,