Lines Matching full:sor
33 #include "sor.h"
401 int (*probe)(struct tegra_sor *sor);
402 void (*audio_enable)(struct tegra_sor *sor);
403 void (*audio_disable)(struct tegra_sor *sor);
486 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
495 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
502 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
506 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
508 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
512 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
521 struct tegra_sor *sor; member
545 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent() local
548 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
561 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
569 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent() local
573 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
596 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, in tegra_clk_sor_pad_register() argument
603 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
607 pad->sor = sor; in tegra_clk_sor_pad_register()
611 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
612 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
617 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
622 static void tegra_sor_filter_rates(struct tegra_sor *sor) in tegra_sor_filter_rates() argument
624 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
646 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_power_up_lanes() argument
655 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
658 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
661 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
662 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
665 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
670 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
679 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
684 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
697 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) in tegra_sor_power_down_lanes() argument
703 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
711 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
716 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
729 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) in tegra_sor_dp_precharge() argument
734 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
737 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
740 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
741 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
744 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
749 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
763 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) in tegra_sor_dp_term_calibrate() argument
768 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
786 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
799 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
806 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_apply_training() local
808 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
816 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
822 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
823 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
856 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_link_apply_training()
857 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_link_apply_training()
860 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_link_apply_training()
862 tegra_sor_writel(sor, pattern, SOR_DP_TPG); in tegra_sor_dp_link_apply_training()
864 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
877 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); in tegra_sor_dp_link_configure() local
886 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
889 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
891 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
898 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
923 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
930 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
932 err = tegra_sor_power_down_lanes(sor); in tegra_sor_dp_link_configure()
934 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
939 err = tegra_sor_power_up_lanes(sor, lanes); in tegra_sor_dp_link_configure()
941 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
946 tegra_sor_dp_precharge(sor, lanes); in tegra_sor_dp_link_configure()
956 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
958 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
959 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
960 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
963 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
965 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
966 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
967 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
970 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
974 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
977 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
979 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
984 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
989 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
999 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
1004 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1007 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1008 tegra_sor_super_update(sor); in tegra_sor_attach()
1011 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1013 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1014 tegra_sor_super_update(sor); in tegra_sor_attach()
1019 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1029 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
1037 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1049 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
1053 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1055 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1060 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1085 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
1153 static int tegra_sor_compute_config(struct tegra_sor *sor, in tegra_sor_compute_config() argument
1182 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_compute_config()
1201 dev_dbg(sor->dev, in tegra_sor_compute_config()
1216 dev_err(sor->dev, in tegra_sor_compute_config()
1221 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1239 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1245 static void tegra_sor_apply_config(struct tegra_sor *sor, in tegra_sor_apply_config() argument
1250 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1253 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1255 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1272 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1274 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1277 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1279 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1282 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1285 static void tegra_sor_mode_set(struct tegra_sor *sor, in tegra_sor_mode_set() argument
1289 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1293 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1339 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1374 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
1379 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1381 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1382 tegra_sor_super_update(sor); in tegra_sor_detach()
1387 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1396 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1398 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1399 tegra_sor_super_update(sor); in tegra_sor_detach()
1402 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1404 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1405 tegra_sor_super_update(sor); in tegra_sor_detach()
1410 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1423 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
1428 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1431 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1436 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1447 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1449 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1473 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
1480 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1493 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
1494 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1506 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1508 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1510 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1512 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1514 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1516 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1518 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
1522 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1523 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1655 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
1656 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1672 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1691 struct tegra_sor *sor = to_sor(output); in tegra_sor_late_register() local
1693 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1695 if (!sor->debugfs_files) in tegra_sor_late_register()
1699 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1701 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1710 struct tegra_sor *sor = to_sor(output); in tegra_sor_early_unregister() local
1712 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1715 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1716 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1739 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1741 if (sor->aux) in tegra_sor_connector_detect()
1742 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1776 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1779 if (sor->aux) in tegra_sor_connector_get_modes()
1780 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1784 if (sor->aux) in tegra_sor_connector_get_modes()
1785 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1811 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
1818 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so in tegra_sor_encoder_atomic_check()
1829 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1862 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
1884 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1892 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1904 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1909 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1914 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
1923 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1927 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1930 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1932 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1938 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1942 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
1945 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1948 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1953 static void tegra_sor_write_eld(struct tegra_sor *sor) in tegra_sor_write_eld() argument
1955 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
1968 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); in tegra_sor_write_eld()
1971 static void tegra_sor_audio_prepare(struct tegra_sor *sor) in tegra_sor_audio_prepare() argument
1981 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1982 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1984 tegra_sor_write_eld(sor); in tegra_sor_audio_prepare()
1987 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1990 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) in tegra_sor_audio_unprepare() argument
1992 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_unprepare()
1993 tegra_sor_writel(sor, 0, SOR_INT_MASK); in tegra_sor_audio_unprepare()
1994 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); in tegra_sor_audio_unprepare()
1997 static void tegra_sor_audio_enable(struct tegra_sor *sor) in tegra_sor_audio_enable() argument
2001 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2008 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2015 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2018 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); in tegra_sor_audio_enable()
2021 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_enable_audio_infoframe() argument
2030 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2034 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2038 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2042 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_enable_audio_infoframe()
2044 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2047 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2052 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_enable() argument
2056 tegra_sor_audio_enable(sor); in tegra_sor_hdmi_audio_enable()
2058 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); in tegra_sor_hdmi_audio_enable()
2063 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2067 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2075 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2077 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2078 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2079 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); in tegra_sor_hdmi_audio_enable()
2081 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); in tegra_sor_hdmi_audio_enable()
2082 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); in tegra_sor_hdmi_audio_enable()
2084 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); in tegra_sor_hdmi_audio_enable()
2085 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); in tegra_sor_hdmi_audio_enable()
2087 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); in tegra_sor_hdmi_audio_enable()
2088 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2091 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2092 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2096 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); in tegra_sor_hdmi_audio_enable()
2098 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2100 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); in tegra_sor_hdmi_audio_enable()
2102 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2104 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2106 tegra_sor_hdmi_enable_audio_infoframe(sor); in tegra_sor_hdmi_audio_enable()
2109 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
2113 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2115 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2118 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) in tegra_sor_hdmi_audio_disable() argument
2120 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_audio_disable()
2124 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
2128 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2129 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2130 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2135 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_disable_scrambling() argument
2139 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2142 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2145 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_disable() argument
2147 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2148 drm_scdc_set_scrambling(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2150 tegra_sor_hdmi_disable_scrambling(sor); in tegra_sor_hdmi_scdc_disable()
2153 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_stop() argument
2155 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2156 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2157 tegra_sor_hdmi_scdc_disable(sor); in tegra_sor_hdmi_scdc_stop()
2161 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_enable_scrambling() argument
2165 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2168 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2171 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_enable() argument
2173 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2174 drm_scdc_set_scrambling(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2176 tegra_sor_hdmi_enable_scrambling(sor); in tegra_sor_hdmi_scdc_enable()
2181 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); in tegra_sor_hdmi_scdc_work() local
2183 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { in tegra_sor_hdmi_scdc_work()
2185 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_work()
2188 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2191 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_start() argument
2193 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2196 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2199 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2200 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_start()
2201 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2209 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
2213 tegra_sor_audio_unprepare(sor); in tegra_sor_hdmi_disable()
2214 tegra_sor_hdmi_scdc_stop(sor); in tegra_sor_hdmi_disable()
2216 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
2218 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2220 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2221 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
2223 /* disable display to SOR clock */ in tegra_sor_hdmi_disable()
2226 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2229 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2235 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
2237 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2239 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2241 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2243 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2252 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
2264 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2266 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2271 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2273 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2277 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2279 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2281 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2313 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2319 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2328 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2331 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2338 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2351 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2353 /* SOR pad PLL stabilization time */ in tegra_sor_hdmi_enable()
2356 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2359 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2361 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2366 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2375 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2377 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2380 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2385 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2388 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2389 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2398 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2400 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2406 /* switch the SOR clock to the pad clock */ in tegra_sor_hdmi_enable()
2407 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2409 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2415 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2417 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2423 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2430 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2432 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2439 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2446 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2467 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
2469 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2472 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
2475 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2478 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2486 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2488 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2503 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2526 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2532 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2534 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2540 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2546 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2586 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2589 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2591 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2593 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2596 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2607 tegra_sor_mode_set(sor, mode, state); in tegra_sor_hdmi_enable()
2609 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2611 /* program preamble timing in SOR (XXX) */ in tegra_sor_hdmi_enable()
2612 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2614 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2616 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2618 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2620 /* enable display to SOR clock and generate HDMI preamble */ in tegra_sor_hdmi_enable()
2623 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2626 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2631 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2639 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2641 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2643 tegra_sor_hdmi_scdc_start(sor); in tegra_sor_hdmi_enable()
2644 tegra_sor_audio_prepare(sor); in tegra_sor_hdmi_enable()
2657 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_disable() local
2669 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2671 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2675 err = tegra_sor_detach(sor); in tegra_sor_dp_disable()
2677 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2679 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_dp_disable()
2680 tegra_sor_update(sor); in tegra_sor_dp_disable()
2683 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2687 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2691 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2692 tegra_sor_update(sor); in tegra_sor_dp_disable()
2695 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2697 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2699 err = tegra_sor_power_down(sor); in tegra_sor_dp_disable()
2701 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2703 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2705 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2707 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2709 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2714 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2721 struct tegra_sor *sor = to_sor(output); in tegra_sor_dp_enable() local
2734 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2736 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2741 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2745 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2747 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2751 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2753 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2755 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2757 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2759 tegra_sor_filter_rates(sor); in tegra_sor_dp_enable()
2761 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2763 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2768 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2782 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2794 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2802 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2806 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2814 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2817 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_enable()
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2829 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2832 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_dp_enable()
2833 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2842 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2844 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2850 /* switch the SOR clock to the pad clock */ in tegra_sor_dp_enable()
2851 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2853 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2859 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2861 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2867 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2870 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2873 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2875 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2877 tegra_sor_dp_term_calibrate(sor); in tegra_sor_dp_enable()
2879 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2881 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2883 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2885 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2887 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2893 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2895 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2897 tegra_sor_apply_config(sor, &config); in tegra_sor_dp_enable()
2898 tegra_sor_mode_set(sor, mode, state); in tegra_sor_dp_enable()
2904 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2907 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_dp_enable()
2909 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2912 tegra_sor_update(sor); in tegra_sor_dp_enable()
2914 err = tegra_sor_power_up(sor, 250); in tegra_sor_dp_enable()
2916 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2919 err = tegra_sor_attach(sor); in tegra_sor_dp_enable()
2921 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2924 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2929 err = tegra_sor_wakeup(sor); in tegra_sor_dp_enable()
2931 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2950 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) in tegra_sor_enable_regulator() argument
2958 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2961 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2965 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2966 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_hdmi_probe()
2967 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), in tegra_sor_hdmi_probe()
2970 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2972 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2977 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2978 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_hdmi_probe()
2979 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), in tegra_sor_hdmi_probe()
2982 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2984 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2989 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2990 if (IS_ERR(sor->hdmi_supply)) in tegra_sor_hdmi_probe()
2991 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), in tegra_sor_hdmi_probe()
2994 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
2996 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
3000 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3012 static int tegra_sor_dp_probe(struct tegra_sor *sor) in tegra_sor_dp_probe() argument
3016 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3017 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3018 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3020 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3024 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3025 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3026 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3028 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3044 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
3049 if (!sor->aux) { in tegra_sor_init()
3050 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3054 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3059 if (sor->output.panel) { in tegra_sor_init()
3069 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3070 sor->link.aux = sor->aux; in tegra_sor_init()
3073 sor->output.dev = sor->dev; in tegra_sor_init()
3075 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3078 sor->output.ddc); in tegra_sor_init()
3079 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3081 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3083 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3084 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3086 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3087 &sor->output.encoder); in tegra_sor_init()
3088 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3090 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3096 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3098 if (sor->aux) { in tegra_sor_init()
3099 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3101 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3110 if (sor->rst) { in tegra_sor_init()
3111 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3113 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3117 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3119 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3124 err = reset_control_assert(sor->rst); in tegra_sor_init()
3126 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3132 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3134 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3140 if (sor->rst) { in tegra_sor_init()
3141 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3143 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3145 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3149 reset_control_release(sor->rst); in tegra_sor_init()
3150 pm_runtime_put(sor->dev); in tegra_sor_init()
3153 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3155 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3159 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3161 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3162 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3169 if (sor->rst) in tegra_sor_init()
3170 pm_runtime_put(sor->dev); in tegra_sor_init()
3177 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
3180 tegra_output_exit(&sor->output); in tegra_sor_exit()
3182 if (sor->aux) { in tegra_sor_exit()
3183 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3185 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3190 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3191 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3192 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3199 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_suspend() local
3203 if (sor->rst) { in tegra_sor_runtime_suspend()
3204 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3210 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3215 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3223 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_runtime_resume() local
3233 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3241 if (sor->rst) { in tegra_sor_runtime_resume()
3242 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3248 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3258 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3260 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3630 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3631 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3633 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3634 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3635 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3640 static int tegra_sor_parse_dt(struct tegra_sor *sor) in tegra_sor_parse_dt() argument
3642 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3648 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3653 sor->index = value; in tegra_sor_parse_dt()
3659 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3661 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3662 sor->index = 0; in tegra_sor_parse_dt()
3664 sor->index = 1; in tegra_sor_parse_dt()
3671 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3673 /* copy cells to SOR XBAR configuration */ in tegra_sor_parse_dt()
3675 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3683 struct tegra_sor *sor = data; in tegra_sor_irq() local
3686 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3687 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3690 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3697 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3699 if (sor->ops->audio_enable) in tegra_sor_irq()
3700 sor->ops->audio_enable(sor); in tegra_sor_irq()
3702 if (sor->ops->audio_disable) in tegra_sor_irq()
3703 sor->ops->audio_disable(sor); in tegra_sor_irq()
3713 struct tegra_sor *sor; in tegra_sor_probe() local
3716 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3717 if (!sor) in tegra_sor_probe()
3720 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3721 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3723 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3724 sor->soc->num_settings * in tegra_sor_probe()
3725 sizeof(*sor->settings), in tegra_sor_probe()
3727 if (!sor->settings) in tegra_sor_probe()
3730 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3734 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3737 if (!sor->aux) in tegra_sor_probe()
3740 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3741 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3744 if (!sor->aux) { in tegra_sor_probe()
3745 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3746 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3747 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3748 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3763 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3764 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3767 err = tegra_sor_parse_dt(sor); in tegra_sor_probe()
3771 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3777 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3778 err = sor->ops->probe(sor); in tegra_sor_probe()
3781 sor->ops->name, err); in tegra_sor_probe()
3786 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3787 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3788 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3796 sor->irq = err; in tegra_sor_probe()
3798 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3799 dev_name(sor->dev), sor); in tegra_sor_probe()
3805 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3806 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3807 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3818 * the power domain will have taken care of resetting the SOR in tegra_sor_probe()
3821 sor->rst = NULL; in tegra_sor_probe()
3824 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3825 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3826 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3831 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3845 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3846 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3847 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3848 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3854 sor->clk_out = sor->clk; in tegra_sor_probe()
3857 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3858 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3859 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3864 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3865 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3866 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3871 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3872 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3873 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3882 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3883 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3884 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3885 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3894 sor->clk_pad = NULL; in tegra_sor_probe()
3898 * The bootloader may have set up the SOR such that it's module clock in tegra_sor_probe()
3900 * without properly having set up other bits of the SOR. in tegra_sor_probe()
3902 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3908 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
3911 host1x_client_init(&sor->client); in tegra_sor_probe()
3912 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3913 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3919 if (!sor->clk_pad) { in tegra_sor_probe()
3922 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3923 sor->index); in tegra_sor_probe()
3929 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3931 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3935 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3936 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3939 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3940 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3941 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3946 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3956 host1x_client_exit(&sor->client); in tegra_sor_probe()
3959 if (sor->aux) in tegra_sor_probe()
3960 sor->output.ddc = NULL; in tegra_sor_probe()
3962 tegra_output_remove(&sor->output); in tegra_sor_probe()
3964 if (sor->aux) in tegra_sor_probe()
3965 put_device(sor->aux->dev); in tegra_sor_probe()
3972 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
3974 host1x_client_unregister(&sor->client); in tegra_sor_remove()
3978 if (sor->aux) { in tegra_sor_remove()
3979 put_device(sor->aux->dev); in tegra_sor_remove()
3980 sor->output.ddc = NULL; in tegra_sor_remove()
3983 tegra_output_remove(&sor->output); in tegra_sor_remove()
3988 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_suspend() local
3991 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
3997 if (sor->hdmi_supply) { in tegra_sor_suspend()
3998 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
4000 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4010 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_resume() local
4013 if (sor->hdmi_supply) { in tegra_sor_resume()
4014 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4019 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4023 if (sor->hdmi_supply) in tegra_sor_resume()
4024 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4038 .name = "tegra-sor",