Lines Matching full:pll1
45 u32 pll1; member
143 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
158 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
176 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
221 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
239 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
258 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
277 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
300 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
318 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
337 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
356 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
840 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()