Lines Matching refs:tegra_dsi_readl
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() function
219 offset, tegra_dsi_readl(dsi, offset)); in tegra_dsi_show_regs()
460 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_enable()
518 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_configure()
632 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_idle()
646 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_video_disable()
737 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_disable()
751 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
757 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
763 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_soft_reset()
920 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_encoder_enable()
1224 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1268 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1285 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_transmit()
1302 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_for_response()
1353 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_host_transfer()
1360 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1387 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1416 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_host_transfer()