Lines Matching full:dpaux
26 #include "dpaux.h"
76 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, in tegra_dpaux_readl() argument
79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
86 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, in tegra_dpaux_writel() argument
89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
93 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, in tegra_dpaux_write_fifo() argument
105 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); in tegra_dpaux_write_fifo()
109 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, in tegra_dpaux_read_fifo() argument
118 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); in tegra_dpaux_read_fifo()
129 struct tegra_dpaux *dpaux = to_dpaux(aux); in tegra_dpaux_transfer() local
196 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); in tegra_dpaux_transfer()
197 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
200 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); in tegra_dpaux_transfer()
205 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
207 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
209 status = wait_for_completion_timeout(&dpaux->complete, timeout); in tegra_dpaux_transfer()
214 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); in tegra_dpaux_transfer()
215 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); in tegra_dpaux_transfer()
261 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); in tegra_dpaux_transfer()
274 struct tegra_dpaux *dpaux = work_to_dpaux(work); in tegra_dpaux_hotplug() local
276 if (dpaux->output) in tegra_dpaux_hotplug()
277 drm_helper_hpd_irq_event(dpaux->output->connector.dev); in tegra_dpaux_hotplug()
282 struct tegra_dpaux *dpaux = data; in tegra_dpaux_irq() local
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); in tegra_dpaux_irq()
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); in tegra_dpaux_irq()
290 schedule_work(&dpaux->work); in tegra_dpaux_irq()
297 complete(&dpaux->complete); in tegra_dpaux_irq()
308 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux) in tegra_dpaux_pad_power_down() argument
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_down()
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_down()
317 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux) in tegra_dpaux_pad_power_up() argument
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_up()
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_up()
326 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function) in tegra_dpaux_pad_config() argument
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
349 tegra_dpaux_pad_power_down(dpaux); in tegra_dpaux_pad_config()
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); in tegra_dpaux_pad_config()
357 tegra_dpaux_pad_power_up(dpaux); in tegra_dpaux_pad_config()
371 "dpaux-io",
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl); in tegra_dpaux_set_mux() local
436 return tegra_dpaux_pad_config(dpaux, function); in tegra_dpaux_set_mux()
449 struct tegra_dpaux *dpaux; in tegra_dpaux_probe() local
453 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); in tegra_dpaux_probe()
454 if (!dpaux) in tegra_dpaux_probe()
457 dpaux->soc = of_device_get_match_data(&pdev->dev); in tegra_dpaux_probe()
458 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); in tegra_dpaux_probe()
459 init_completion(&dpaux->complete); in tegra_dpaux_probe()
460 INIT_LIST_HEAD(&dpaux->list); in tegra_dpaux_probe()
461 dpaux->dev = &pdev->dev; in tegra_dpaux_probe()
463 dpaux->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dpaux_probe()
464 if (IS_ERR(dpaux->regs)) in tegra_dpaux_probe()
465 return PTR_ERR(dpaux->regs); in tegra_dpaux_probe()
467 dpaux->irq = platform_get_irq(pdev, 0); in tegra_dpaux_probe()
468 if (dpaux->irq < 0) in tegra_dpaux_probe()
469 return dpaux->irq; in tegra_dpaux_probe()
472 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); in tegra_dpaux_probe()
473 if (IS_ERR(dpaux->rst)) { in tegra_dpaux_probe()
476 PTR_ERR(dpaux->rst)); in tegra_dpaux_probe()
477 return PTR_ERR(dpaux->rst); in tegra_dpaux_probe()
481 dpaux->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dpaux_probe()
482 if (IS_ERR(dpaux->clk)) { in tegra_dpaux_probe()
484 PTR_ERR(dpaux->clk)); in tegra_dpaux_probe()
485 return PTR_ERR(dpaux->clk); in tegra_dpaux_probe()
488 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dpaux_probe()
489 if (IS_ERR(dpaux->clk_parent)) { in tegra_dpaux_probe()
491 PTR_ERR(dpaux->clk_parent)); in tegra_dpaux_probe()
492 return PTR_ERR(dpaux->clk_parent); in tegra_dpaux_probe()
495 err = clk_set_rate(dpaux->clk_parent, 270000000); in tegra_dpaux_probe()
502 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd"); in tegra_dpaux_probe()
503 if (IS_ERR(dpaux->vdd)) { in tegra_dpaux_probe()
504 if (PTR_ERR(dpaux->vdd) != -ENODEV) { in tegra_dpaux_probe()
505 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER) in tegra_dpaux_probe()
508 PTR_ERR(dpaux->vdd)); in tegra_dpaux_probe()
510 return PTR_ERR(dpaux->vdd); in tegra_dpaux_probe()
513 dpaux->vdd = NULL; in tegra_dpaux_probe()
516 platform_set_drvdata(pdev, dpaux); in tegra_dpaux_probe()
520 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, in tegra_dpaux_probe()
521 dev_name(dpaux->dev), dpaux); in tegra_dpaux_probe()
523 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", in tegra_dpaux_probe()
524 dpaux->irq, err); in tegra_dpaux_probe()
528 disable_irq(dpaux->irq); in tegra_dpaux_probe()
530 dpaux->aux.transfer = tegra_dpaux_transfer; in tegra_dpaux_probe()
531 dpaux->aux.dev = &pdev->dev; in tegra_dpaux_probe()
533 drm_dp_aux_init(&dpaux->aux); in tegra_dpaux_probe()
536 * Assume that by default the DPAUX/I2C pads will be used for HDMI, in tegra_dpaux_probe()
539 * The DPAUX code paths reconfigure the pads in AUX mode, but there in tegra_dpaux_probe()
543 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C); in tegra_dpaux_probe()
548 dpaux->desc.name = dev_name(&pdev->dev); in tegra_dpaux_probe()
549 dpaux->desc.pins = tegra_dpaux_pins; in tegra_dpaux_probe()
550 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins); in tegra_dpaux_probe()
551 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops; in tegra_dpaux_probe()
552 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops; in tegra_dpaux_probe()
553 dpaux->desc.owner = THIS_MODULE; in tegra_dpaux_probe()
555 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); in tegra_dpaux_probe()
556 if (IS_ERR(dpaux->pinctrl)) { in tegra_dpaux_probe()
558 err = PTR_ERR(dpaux->pinctrl); in tegra_dpaux_probe()
565 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); in tegra_dpaux_probe()
566 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); in tegra_dpaux_probe()
569 list_add_tail(&dpaux->list, &dpaux_list); in tegra_dpaux_probe()
572 err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux); in tegra_dpaux_probe()
574 dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err); in tegra_dpaux_probe()
588 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); in tegra_dpaux_remove() local
590 cancel_work_sync(&dpaux->work); in tegra_dpaux_remove()
593 tegra_dpaux_pad_power_down(dpaux); in tegra_dpaux_remove()
599 list_del(&dpaux->list); in tegra_dpaux_remove()
605 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); in tegra_dpaux_suspend() local
608 if (dpaux->rst) { in tegra_dpaux_suspend()
609 err = reset_control_assert(dpaux->rst); in tegra_dpaux_suspend()
618 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_suspend()
619 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_suspend()
626 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); in tegra_dpaux_resume() local
629 err = clk_prepare_enable(dpaux->clk); in tegra_dpaux_resume()
635 err = clk_prepare_enable(dpaux->clk_parent); in tegra_dpaux_resume()
643 if (dpaux->rst) { in tegra_dpaux_resume()
644 err = reset_control_deassert(dpaux->rst); in tegra_dpaux_resume()
656 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_resume()
658 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_resume()
685 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
686 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
687 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
688 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
695 .name = "tegra-dpaux",
705 struct tegra_dpaux *dpaux; in drm_dp_aux_find_by_of_node() local
709 list_for_each_entry(dpaux, &dpaux_list, list) in drm_dp_aux_find_by_of_node()
710 if (np == dpaux->dev->of_node) { in drm_dp_aux_find_by_of_node()
712 return &dpaux->aux; in drm_dp_aux_find_by_of_node()
722 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_attach() local
732 dpaux->output = output; in drm_dp_aux_attach()
737 if (dpaux->vdd) { in drm_dp_aux_attach()
738 err = regulator_enable(dpaux->vdd); in drm_dp_aux_attach()
758 enable_irq(dpaux->irq); in drm_dp_aux_attach()
764 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detach() local
769 disable_irq(dpaux->irq); in drm_dp_aux_detach()
771 if (dpaux->output->panel) { in drm_dp_aux_detach()
774 if (dpaux->vdd) { in drm_dp_aux_detach()
775 err = regulator_disable(dpaux->vdd); in drm_dp_aux_detach()
794 dpaux->output = NULL; in drm_dp_aux_detach()
802 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detect() local
805 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); in drm_dp_aux_detect()
815 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_enable() local
817 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX); in drm_dp_aux_enable()
822 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_disable() local
824 tegra_dpaux_pad_power_down(dpaux); in drm_dp_aux_disable()