17 #define I2C_ADDR	0x69
22 			{ 0x00b3, 0x0000 },
23 			{ 0x2153, 0x0000 },
24 			{ 0x40f3, 0x0000 },
28 			{ 0x00b3, 0x0000 },
29 			{ 0x2153, 0x0000 },
30 			{ 0x40a2, 0x0001 },
34 			{ 0x00b3, 0x0000 },
35 			{ 0x2142, 0x0001 },
36 			{ 0x40a2, 0x0001 },
40 			{ 0x0072, 0x0001 },
41 			{ 0x2142, 0x0001 },
42 			{ 0x40a2, 0x0001 },
46 			{ 0x0072, 0x0001 },
47 			{ 0x2142, 0x0001 },
48 			{ 0x4061, 0x0002 },
52 			{ 0x0072, 0x0001 },
53 			{ 0x2145, 0x0002 },
54 			{ 0x4061, 0x0002 },
58 			{ 0x0051, 0x0002 },
59 			{ 0x2145, 0x0002 },
60 			{ 0x4061, 0x0002 },
64 			{ 0x0051, 0x0002 },
65 			{ 0x2145, 0x0002 },
66 			{ 0x4064, 0x0003 },
70 			{ 0x0051, 0x0002 },
71 			{ 0x214c, 0x0003 },
72 			{ 0x4064, 0x0003 },
76 			{ 0x0040, 0x0003 },
77 			{ 0x214c, 0x0003 },
78 			{ 0x4064, 0x0003 },
82 			{ 0x0040, 0x0003 },
83 			{ 0x214c, 0x0003 },
84 			{ 0x5a64, 0x0003 },
88 			{ 0x0040, 0x0003 },
89 			{ 0x3b4c, 0x0003 },
90 			{ 0x5a64, 0x0003 },
94 			{ 0x1a40, 0x0003 },
95 			{ 0x3b4c, 0x0003 },
96 			{ 0x5a64, 0x0003 },
99 		~0UL, {
100 			{ 0x0000, 0x0000 },
101 			{ 0x0000, 0x0000 },
102 			{ 0x0000, 0x0000 },
109 	{ 27000000,  { 0x0012, 0x0000, 0x0000 }, },
110 	{ 74250000,  { 0x0013, 0x001a, 0x001b }, },
111 	{ 148500000, { 0x0019, 0x0033, 0x0034 }, },
112 	{ 297000000, { 0x0019, 0x001b, 0x001b }, },
113 	{ 594000000, { 0x0010, 0x001b, 0x001b }, },
114 	{ ~0UL,      { 0x0000, 0x0000, 0x0000 }, }
119 	{ 27000000,  0x8009, 0x0007, 0x02b0 },
120 	{ 74250000,  0x8009, 0x0006, 0x022d },
121 	{ 148500000, 0x8029, 0x0006, 0x0270 },
122 	{ 297000000, 0x8039, 0x0005, 0x01ab },
123 	{ 594000000, 0x8029, 0x0000, 0x008a },
124 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
130 	u32 val = 0;  in sun8i_hdmi_phy_set_polarity()
156 	dw_hdmi_phy_gen2_txpwron(hdmi, 0);  in sun8i_a83t_hdmi_phy_config()
161 	dw_hdmi_phy_gen2_pddq(hdmi, 0);  in sun8i_a83t_hdmi_phy_config()
171 		dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);  in sun8i_a83t_hdmi_phy_config()
172 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);  in sun8i_a83t_hdmi_phy_config()
173 		dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);  in sun8i_a83t_hdmi_phy_config()
174 		dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);  in sun8i_a83t_hdmi_phy_config()
175 		dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);  in sun8i_a83t_hdmi_phy_config()
176 		dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);  in sun8i_a83t_hdmi_phy_config()
178 		dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);  in sun8i_a83t_hdmi_phy_config()
179 		dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);  in sun8i_a83t_hdmi_phy_config()
180 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);  in sun8i_a83t_hdmi_phy_config()
181 		dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);  in sun8i_a83t_hdmi_phy_config()
182 		dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);  in sun8i_a83t_hdmi_phy_config()
183 		dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);  in sun8i_a83t_hdmi_phy_config()
185 		dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);  in sun8i_a83t_hdmi_phy_config()
186 		dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);  in sun8i_a83t_hdmi_phy_config()
187 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);  in sun8i_a83t_hdmi_phy_config()
188 		dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);  in sun8i_a83t_hdmi_phy_config()
189 		dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);  in sun8i_a83t_hdmi_phy_config()
190 		dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);  in sun8i_a83t_hdmi_phy_config()
192 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);  in sun8i_a83t_hdmi_phy_config()
193 		dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);  in sun8i_a83t_hdmi_phy_config()
194 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);  in sun8i_a83t_hdmi_phy_config()
195 		dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);  in sun8i_a83t_hdmi_phy_config()
196 		dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);  in sun8i_a83t_hdmi_phy_config()
197 		dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);  in sun8i_a83t_hdmi_phy_config()
200 	dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);  in sun8i_a83t_hdmi_phy_config()
201 	dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  in sun8i_a83t_hdmi_phy_config()
202 	dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);  in sun8i_a83t_hdmi_phy_config()
206 	return 0;  in sun8i_a83t_hdmi_phy_config()
213 	dw_hdmi_phy_gen2_txpwron(hdmi, 0);  in sun8i_a83t_hdmi_phy_disable()
217 			   SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);  in sun8i_a83t_hdmi_phy_disable()
239 	u32 b_offset = 0;  in sun8i_h3_hdmi_phy_config()
292 	ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |  in sun8i_h3_hdmi_phy_config()
341 			   SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);  in sun8i_h3_hdmi_phy_config()
365 	val = min(val + b_offset, (u32)0x3f);  in sun8i_h3_hdmi_phy_config()
380 	return 0;  in sun8i_h3_hdmi_phy_config()
391 	regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);  in sun8i_h3_hdmi_phy_disable()
420 			   0xffff0000, 0x80c00000);  in sun50i_hdmi_phy_init_h6()
446 	regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);  in sun8i_hdmi_phy_init_h3()
508 			   SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0);  in sun8i_hdmi_phy_init_h3()
511 	regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);  in sun8i_hdmi_phy_init_h3()
553 	return 0;  in sun8i_hdmi_phy_init()
671 	return 0;  in sun8i_hdmi_phy_get()
687 	regs = devm_platform_ioremap_resource(pdev, 0);  in sun8i_hdmi_phy_probe()
709 		phy->clk_pll0 = devm_clk_get(dev, "pll-0");  in sun8i_hdmi_phy_probe()
712 					     "Could not get pll-0 clock\n");  in sun8i_hdmi_phy_probe()
729 	return 0;  in sun8i_hdmi_phy_probe()