Lines Matching +full:0 +full:xfff
20 #define SUN4I_TCON_GCTL_REG 0x0
22 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
23 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
24 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
26 #define SUN4I_TCON_GINT0_REG 0x4
34 #define SUN4I_TCON_GINT1_REG 0x8
36 #define SUN4I_TCON_FRM_CTL_REG 0x10
42 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
43 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
44 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
45 #define SUN4I_TCON0_FRM_SEED_LR_REG 0x20
46 #define SUN4I_TCON0_FRM_SEED_LG_REG 0x24
47 #define SUN4I_TCON0_FRM_SEED_LB_REG 0x28
48 #define SUN4I_TCON0_FRM_TBL0_REG 0x2c
49 #define SUN4I_TCON0_FRM_TBL1_REG 0x30
50 #define SUN4I_TCON0_FRM_TBL2_REG 0x34
51 #define SUN4I_TCON0_FRM_TBL3_REG 0x38
53 #define SUN4I_TCON0_CTL_REG 0x40
59 #define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0)
61 #define SUN4I_TCON0_DCLK_REG 0x44
63 #define SUN4I_TCON0_DCLK_DIV_SHIFT (0)
66 #define SUN4I_TCON0_BASIC0_REG 0x48
67 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
68 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
70 #define SUN4I_TCON0_BASIC1_REG 0x4c
71 #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
72 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
74 #define SUN4I_TCON0_BASIC2_REG 0x50
75 #define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16)
76 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
78 #define SUN4I_TCON0_BASIC3_REG 0x54
79 #define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16)
80 #define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff)
82 #define SUN4I_TCON0_HV_IF_REG 0x58
84 #define SUN4I_TCON0_CPU_IF_REG 0x60
89 #define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0)
91 #define SUN4I_TCON0_CPU_WR_REG 0x64
92 #define SUN4I_TCON0_CPU_RD0_REG 0x68
93 #define SUN4I_TCON0_CPU_RDA_REG 0x6c
94 #define SUN4I_TCON0_TTL0_REG 0x70
95 #define SUN4I_TCON0_TTL1_REG 0x74
96 #define SUN4I_TCON0_TTL2_REG 0x78
97 #define SUN4I_TCON0_TTL3_REG 0x7c
98 #define SUN4I_TCON0_TTL4_REG 0x80
100 #define SUN4I_TCON0_LVDS_IF_REG 0x84
104 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26)
109 #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4)
110 #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0)
111 #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf)
112 #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0)
114 #define SUN4I_TCON0_IO_POL_REG 0x88
121 #define SUN4I_TCON0_IO_TRI_REG 0x8c
124 #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0)
126 #define SUN4I_TCON1_CTL_REG 0x90
131 #define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0)
133 #define SUN4I_TCON1_BASIC0_REG 0x94
134 #define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
135 #define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff)
137 #define SUN4I_TCON1_BASIC1_REG 0x98
138 #define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16)
139 #define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff)
141 #define SUN4I_TCON1_BASIC2_REG 0x9c
142 #define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16)
143 #define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff)
145 #define SUN4I_TCON1_BASIC3_REG 0xa0
146 #define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
147 #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
149 #define SUN4I_TCON1_BASIC4_REG 0xa4
150 #define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16)
151 #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
153 #define SUN4I_TCON1_BASIC5_REG 0xa8
154 #define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16)
155 #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
157 #define SUN4I_TCON1_IO_POL_REG 0xf0
163 #define SUN4I_TCON1_IO_TRI_REG 0xf4
165 #define SUN4I_TCON_ECC_FIFO_REG 0xf8
168 #define SUN4I_TCON_CEU_CTL_REG 0x100
169 #define SUN4I_TCON_CEU_MUL_RR_REG 0x110
170 #define SUN4I_TCON_CEU_MUL_RG_REG 0x114
171 #define SUN4I_TCON_CEU_MUL_RB_REG 0x118
172 #define SUN4I_TCON_CEU_ADD_RC_REG 0x11c
173 #define SUN4I_TCON_CEU_MUL_GR_REG 0x120
174 #define SUN4I_TCON_CEU_MUL_GG_REG 0x124
175 #define SUN4I_TCON_CEU_MUL_GB_REG 0x128
176 #define SUN4I_TCON_CEU_ADD_GC_REG 0x12c
177 #define SUN4I_TCON_CEU_MUL_BR_REG 0x130
178 #define SUN4I_TCON_CEU_MUL_BG_REG 0x134
179 #define SUN4I_TCON_CEU_MUL_BB_REG 0x138
180 #define SUN4I_TCON_CEU_ADD_BC_REG 0x13c
181 #define SUN4I_TCON_CEU_RANGE_R_REG 0x140
182 #define SUN4I_TCON_CEU_RANGE_G_REG 0x144
183 #define SUN4I_TCON_CEU_RANGE_B_REG 0x148
185 #define SUN4I_TCON0_CPU_TRI0_REG 0x160
186 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space) ((((space) - 1) & 0xfff) << 16)
187 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size) (((size) - 1) & 0xfff)
189 #define SUN4I_TCON0_CPU_TRI1_REG 0x164
190 #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num) (((num) - 1) & 0xffff)
192 #define SUN4I_TCON0_CPU_TRI2_REG 0x168
193 #define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay) (((delay) & 0xffff) << 16)
194 #define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set) ((set) & 0xfff)
196 #define SUN4I_TCON_SAFE_PERIOD_REG 0x1f0
197 #define SUN4I_TCON_SAFE_PERIOD_NUM(num) (((num) & 0xfff) << 16)
198 #define SUN4I_TCON_SAFE_PERIOD_MODE(mode) ((mode) & 0x3)
200 #define SUN4I_TCON_MUX_CTRL_REG 0x200
202 #define SUN4I_TCON0_LVDS_ANA0_REG 0x220
213 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20)
218 #define SUN4I_TCON0_LVDS_ANA1_REG 0x224
219 #define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f << 10)
220 #define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f << 00)
222 #define SUN4I_TCON1_FILL_CTL_REG 0x300
223 #define SUN4I_TCON1_FILL_BEG0_REG 0x304
224 #define SUN4I_TCON1_FILL_END0_REG 0x308
225 #define SUN4I_TCON1_FILL_DATA0_REG 0x30c
226 #define SUN4I_TCON1_FILL_BEG1_REG 0x310
227 #define SUN4I_TCON1_FILL_END1_REG 0x314
228 #define SUN4I_TCON1_FILL_DATA1_REG 0x318
229 #define SUN4I_TCON1_FILL_BEG2_REG 0x31c
230 #define SUN4I_TCON1_FILL_END2_REG 0x320
231 #define SUN4I_TCON1_FILL_DATA2_REG 0x324
232 #define SUN4I_TCON1_GAMMA_TABLE_REG 0x400
239 bool has_channel_0; /* a83t does not have channel 0 on second TCON */