Lines Matching full:tcon
84 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
91 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
92 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
95 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
98 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
99 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
102 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
118 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun4i_tcon_setup_lvds_phy() argument
121 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
130 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
137 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
142 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun6i_tcon_setup_lvds_phy() argument
147 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
168 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
173 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_lvds_set_status() argument
178 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
181 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
182 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
184 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
189 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_set_status() argument
214 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
216 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
221 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
223 sun4i_tcon_channel_set_status(tcon, channel, enabled); in sun4i_tcon_set_status()
226 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) in sun4i_tcon_enable_vblank() argument
239 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
244 * This function is a helper for TCON output muxing. The TCON output
245 * muxing control register in earlier SoCs (without the TCON TOP block)
252 struct sun4i_tcon *tcon; in sun4i_get_tcon0() local
254 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
255 if (tcon->id == 0) in sun4i_get_tcon0()
256 return tcon; in sun4i_get_tcon0()
264 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_set_mux() argument
269 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
270 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
289 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); in sun4i_tcon_get_clk_delay()
294 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_dithering() argument
310 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
311 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
312 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
313 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
314 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
315 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
316 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
317 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
318 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
319 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
343 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
346 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_cpu() argument
361 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
362 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
363 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes) in sun4i_tcon0_mode_set_cpu()
367 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_cpu()
372 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_cpu()
374 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
378 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
393 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
398 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
402 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
408 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
416 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
421 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
425 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_lvds() argument
433 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
435 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
436 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
437 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_lvds()
440 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_lvds()
445 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_lvds()
449 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
462 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
475 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
485 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
494 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
497 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
502 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
505 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_rgb() argument
515 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
517 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
518 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
519 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_rgb()
522 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_rgb()
527 sun4i_tcon0_mode_set_dithering(tcon, connector); in sun4i_tcon0_mode_set_rgb()
531 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
544 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
557 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
565 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
582 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
590 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
595 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
598 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon1_mode_set() argument
605 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
608 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
612 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
621 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
626 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
631 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
636 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
644 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
670 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
678 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
683 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
692 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
703 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
707 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
712 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon_mode_set() argument
719 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); in sun4i_tcon_mode_set()
722 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
725 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); in sun4i_tcon_mode_set()
726 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
730 sun4i_tcon1_mode_set(tcon, mode); in sun4i_tcon_mode_set()
731 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
755 struct sun4i_tcon *tcon = private; in sun4i_tcon_handler() local
756 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
757 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
761 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
772 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
785 struct sun4i_tcon *tcon) in sun4i_tcon_init_clocks() argument
787 tcon->clk = devm_clk_get_enabled(dev, "ahb"); in sun4i_tcon_init_clocks()
788 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
789 dev_err(dev, "Couldn't get the TCON bus clock\n"); in sun4i_tcon_init_clocks()
790 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
793 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
794 tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
795 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
796 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); in sun4i_tcon_init_clocks()
797 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
801 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
802 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
803 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
804 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); in sun4i_tcon_init_clocks()
805 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
813 struct sun4i_tcon *tcon) in sun4i_tcon_init_irq() argument
823 dev_name(dev), tcon); in sun4i_tcon_init_irq()
840 struct sun4i_tcon *tcon) in sun4i_tcon_init_regmap() argument
849 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
851 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
852 dev_err(dev, "Couldn't create the TCON regmap\n"); in sun4i_tcon_init_regmap()
853 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
856 /* Make sure the TCON is disabled and all IRQs are off */ in sun4i_tcon_init_regmap()
857 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
858 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
859 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
862 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
863 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
870 * the TCON is always tied to just one backend. Hence we can traverse
871 * the of_graph upwards to find the backend our tcon is connected to,
876 * registered and binded before the TCON, we can just go through the
897 * This only works if there is only one path from the TCON in sun4i_tcon_find_engine_traverse()
925 * more than one input and one output (TCON TOP) exits, correct in sun4i_tcon_find_engine_traverse()
950 * connection between components, up to and including the TCON, of
983 * Once we know the TCON's id, we can look through the list of
1020 * Because TCON is added to the list at the end of the probe in sun4i_tcon_get_index()
1021 * (after this function is called), index of the current TCON in sun4i_tcon_get_index()
1022 * will be same as current TCON list size. in sun4i_tcon_get_index()
1032 * we assumed the TCON was always tied to just one backend. However
1033 * this proved not to be the case. On the A31, the TCON can select
1035 * the backend can choose which TCON to output to.
1038 * connection between components, up to and including the TCON, of
1044 * However the connections between the backend and TCON were assumed
1047 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1050 * This function first checks if the TCON node has 2 input endpoints.
1055 * have endpoint connections between the backend and TCON across
1075 * connections between the backend and TCON? in sun4i_tcon_find_engine()
1084 * contains TCON TOP, chances are that there are either more in sun4i_tcon_find_engine()
1086 * (H6). In that case it's easier just use TCON index in list in sun4i_tcon_find_engine()
1089 * TCON TOP, remaining 2 TCONs can't be connected to anything in sun4i_tcon_find_engine()
1116 struct sun4i_tcon *tcon; in sun4i_tcon_bind() local
1127 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in sun4i_tcon_bind()
1128 if (!tcon) in sun4i_tcon_bind()
1130 dev_set_drvdata(dev, tcon); in sun4i_tcon_bind()
1131 tcon->drm = drm; in sun4i_tcon_bind()
1132 tcon->dev = dev; in sun4i_tcon_bind()
1133 tcon->id = engine->id; in sun4i_tcon_bind()
1134 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1136 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1137 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1139 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1142 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1156 /* Make sure our TCON is reset */ in sun4i_tcon_bind()
1157 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1163 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1171 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1172 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1174 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1175 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1177 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1189 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1190 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1191 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1192 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1196 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1204 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1215 ret = sun4i_tcon_init_clocks(dev, tcon); in sun4i_tcon_bind()
1217 dev_err(dev, "Couldn't init our TCON clocks\n"); in sun4i_tcon_bind()
1221 ret = sun4i_tcon_init_regmap(dev, tcon); in sun4i_tcon_bind()
1223 dev_err(dev, "Couldn't init our TCON regmap\n"); in sun4i_tcon_bind()
1227 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1228 ret = sun4i_dclk_create(dev, tcon); in sun4i_tcon_bind()
1230 dev_err(dev, "Couldn't create our TCON dot clock\n"); in sun4i_tcon_bind()
1235 ret = sun4i_tcon_init_irq(dev, tcon); in sun4i_tcon_bind()
1237 dev_err(dev, "Couldn't init our TCON interrupts\n"); in sun4i_tcon_bind()
1241 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1242 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1244 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1248 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1250 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1257 ret = sun4i_lvds_init(drm, tcon); in sun4i_tcon_bind()
1261 ret = sun4i_rgb_init(drm, tcon); in sun4i_tcon_bind()
1268 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1274 * the CRTC is tied to the TCON, while the layers are in sun4i_tcon_bind()
1279 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1281 tcon->id); in sun4i_tcon_bind()
1282 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1284 tcon->id); in sun4i_tcon_bind()
1287 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1292 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1293 sun4i_dclk_free(tcon); in sun4i_tcon_bind()
1295 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1302 struct sun4i_tcon *tcon = dev_get_drvdata(dev); in sun4i_tcon_unbind() local
1304 list_del(&tcon->list); in sun4i_tcon_unbind()
1305 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1306 sun4i_dclk_free(tcon); in sun4i_tcon_unbind()
1339 /* platform specific TCON muxing callbacks */
1340 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, in sun4i_a10_tcon_set_mux() argument
1359 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1364 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, in sun5i_a13_tcon_set_mux() argument
1377 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1380 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, in sun6i_tcon_set_mux() argument
1400 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1405 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, in sun8i_r40_tcon_tv_set_mux() argument
1412 /* find TCON TOP platform device and TCON id */ in sun8i_r40_tcon_tv_set_mux()
1414 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1421 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1440 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1545 /* sun4i_drv uses this list to check if a device node is a TCON */
1547 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1548 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1549 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1550 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1551 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1554 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1555 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1556 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1557 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1558 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1559 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1560 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1561 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1562 { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
1563 { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
1573 .name = "sun4i-tcon",