1 // SPDX-License-Identifier: GPL-2.0
70  * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72  * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi)  in sti_hdmi_tx3g4c28phy_start()  argument
78 	u32 ckpxpll = hdmi->mode.clock * 1000;  in sti_hdmi_tx3g4c28phy_start()
114 	 * Configure and power up the PHY PLL  in sti_hdmi_tx3g4c28phy_start()
116 	hdmi->event_received = false;  in sti_hdmi_tx3g4c28phy_start()
118 	hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG);  in sti_hdmi_tx3g4c28phy_start()
121 	wait_event_interruptible_timeout(hdmi->wait_event,  in sti_hdmi_tx3g4c28phy_start()
122 					 hdmi->event_received == true,  in sti_hdmi_tx3g4c28phy_start()
126 	if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {  in sti_hdmi_tx3g4c28phy_start()
127 		DRM_ERROR("hdmi phy pll not locked\n");  in sti_hdmi_tx3g4c28phy_start()
131 	DRM_DEBUG_DRIVER("got PHY PLL Lock\n");  in sti_hdmi_tx3g4c28phy_start()
142 	 * To configure the source termination and pre-emphasis appropriately  in sti_hdmi_tx3g4c28phy_start()
143 	 * for different high speed TMDS clock frequencies a phy configuration  in sti_hdmi_tx3g4c28phy_start()
151 			hdmi_write(hdmi, val, HDMI_SRZ_CFG);  in sti_hdmi_tx3g4c28phy_start()
154 			hdmi_write(hdmi, val, HDMI_SRZ_ICNTL);  in sti_hdmi_tx3g4c28phy_start()
157 			hdmi_write(hdmi, val, HDMI_SRZ_CALCODE_EXT);  in sti_hdmi_tx3g4c28phy_start()
168 	 * Default, power up the serializer with no pre-emphasis or  in sti_hdmi_tx3g4c28phy_start()
171 	hdmi_write(hdmi, val,  HDMI_SRZ_CFG);  in sti_hdmi_tx3g4c28phy_start()
172 	hdmi_write(hdmi, 0x0, HDMI_SRZ_ICNTL);  in sti_hdmi_tx3g4c28phy_start()
173 	hdmi_write(hdmi, 0x0, HDMI_SRZ_CALCODE_EXT);  in sti_hdmi_tx3g4c28phy_start()
182  * sti_hdmi_tx3g4c28phy_stop - Stop hdmi phy macro cell tx3g4c28
184  * @hdmi: pointer on the hdmi internal structure
186 static void sti_hdmi_tx3g4c28phy_stop(struct sti_hdmi *hdmi)  in sti_hdmi_tx3g4c28phy_stop()  argument
192 	hdmi->event_received = false;  in sti_hdmi_tx3g4c28phy_stop()
197 	hdmi_write(hdmi, val, HDMI_SRZ_CFG);  in sti_hdmi_tx3g4c28phy_stop()
198 	hdmi_write(hdmi, 0, HDMI_SRZ_PLL_CFG);  in sti_hdmi_tx3g4c28phy_stop()
201 	wait_event_interruptible_timeout(hdmi->wait_event,  in sti_hdmi_tx3g4c28phy_stop()
202 					 hdmi->event_received == true,  in sti_hdmi_tx3g4c28phy_stop()
206 	if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)  in sti_hdmi_tx3g4c28phy_stop()
207 		DRM_ERROR("hdmi phy pll not well disabled\n");  in sti_hdmi_tx3g4c28phy_stop()