262 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)  in vop2_writel()  function
888 	vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);  in vop2_crtc_enable_irq()
889 	vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);  in vop2_crtc_enable_irq()
896 	vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);  in vop2_crtc_disable_irq()
938 	vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd);  in rk3588_vop2_power_domain_enable_all()
964 		vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);  in vop2_enable()
969 	vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);  in vop2_enable()
978 	vop2_writel(vop2, RK3568_SYS0_INT_CLR,  in vop2_enable()
980 	vop2_writel(vop2, RK3568_SYS0_INT_EN,  in vop2_enable()
982 	vop2_writel(vop2, RK3568_SYS1_INT_CLR,  in vop2_enable()
984 	vop2_writel(vop2, RK3568_SYS1_INT_EN,  in vop2_enable()
1534 	vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),  in vop2_post_config()
1644 	vop2_writel(vop2, RK3568_DSP_IF_EN, die);  in rk3568_set_intf_mux()
1645 	vop2_writel(vop2, RK3568_DSP_IF_POL, dip);  in rk3568_set_intf_mux()
1896 	vop2_writel(vop2, RK3568_DSP_IF_EN, die);  in rk3588_set_intf_mux()
1897 	vop2_writel(vop2, RK3568_DSP_IF_CTRL, div);  in rk3588_set_intf_mux()
1898 	vop2_writel(vop2, RK3568_DSP_IF_POL, dip);  in rk3588_set_intf_mux()
2040 	vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),  in vop2_crtc_atomic_enable()
2188 	vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,  in vop2_setup_cluster_alpha()
2190 	vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,  in vop2_setup_cluster_alpha()
2192 	vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,  in vop2_setup_cluster_alpha()
2194 	vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,  in vop2_setup_cluster_alpha()
2271 		vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,  in vop2_setup_alpha()
2273 		vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,  in vop2_setup_alpha()
2275 		vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,  in vop2_setup_alpha()
2277 		vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,  in vop2_setup_alpha()
2291 			vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,  in vop2_setup_alpha()
2293 			vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,  in vop2_setup_alpha()
2295 			vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,  in vop2_setup_alpha()
2297 			vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,  in vop2_setup_alpha()
2300 			vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);  in vop2_setup_alpha()
2326 	vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);  in vop2_setup_layer_mixer()
2415 	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);  in vop2_setup_layer_mixer()
2416 	vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);  in vop2_setup_layer_mixer()
2455 	vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);  in vop2_setup_dly_for_windows()
2456 	vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);  in vop2_setup_dly_for_windows()
2588 		vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);  in vop2_isr()
2621 	vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);  in vop2_isr()
2623 	vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);  in vop2_isr()