Lines Matching refs:polflags

1574 static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags)  in rk3568_set_intf_mux()  argument
1589 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); in rk3568_set_intf_mux()
1590 if (polflags & POLFLAG_DCLK_INV) in rk3568_set_intf_mux()
1600 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags); in rk3568_set_intf_mux()
1607 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags); in rk3568_set_intf_mux()
1614 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); in rk3568_set_intf_mux()
1621 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags); in rk3568_set_intf_mux()
1628 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); in rk3568_set_intf_mux()
1635 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); in rk3568_set_intf_mux()
1794 static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) in rk3588_set_intf_mux() argument
1822 val = rk3588_get_hdmi_pol(polflags); in rk3588_set_intf_mux()
1834 val = rk3588_get_hdmi_pol(polflags); in rk3588_set_intf_mux()
1879 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags); in rk3588_set_intf_mux()
1886 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags); in rk3588_set_intf_mux()
1903 static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags) in vop2_set_intf_mux() argument
1908 return rk3568_set_intf_mux(vp, ep_id, polflags); in vop2_set_intf_mux()
1910 return rk3588_set_intf_mux(vp, ep_id, polflags); in vop2_set_intf_mux()
1944 u32 val, polflags; in vop2_crtc_atomic_enable() local
1971 polflags = 0; in vop2_crtc_atomic_enable()
1973 polflags |= POLFLAG_DCLK_INV; in vop2_crtc_atomic_enable()
1975 polflags |= BIT(HSYNC_POSITIVE); in vop2_crtc_atomic_enable()
1977 polflags |= BIT(VSYNC_POSITIVE); in vop2_crtc_atomic_enable()
1987 clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); in vop2_crtc_atomic_enable()