67 #define VOP_REG_SET(vop, group, name, v) \  macro
247 	VOP_REG_SET(vop, common, cfg_done, 1);  in vop_cfg_done()
693 	VOP_REG_SET(vop, common, standby, 1);  in vop_enable()
758 	VOP_REG_SET(vop, common, standby, 1);  in vop_crtc_atomic_disable()
1294 		VOP_REG_SET(vop, common, dsp_lut_en, 0);  in vop_crtc_gamma_set()
1321 	VOP_REG_SET(vop, common, dsp_lut_en, 1);  in vop_crtc_gamma_set()
1322 	VOP_REG_SET(vop, common, update_gamma_lut, 1);  in vop_crtc_gamma_set()
1339 		VOP_REG_SET(vop, common, update_gamma_lut, 0);  in vop_crtc_gamma_set()
1405 	VOP_REG_SET(vop, output, pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1406 	VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);  in vop_crtc_atomic_enable()
1410 		VOP_REG_SET(vop, output, rgb_dclk_pol, 1);  in vop_crtc_atomic_enable()
1411 		VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1412 		VOP_REG_SET(vop, output, rgb_en, 1);  in vop_crtc_atomic_enable()
1415 		VOP_REG_SET(vop, output, edp_dclk_pol, 1);  in vop_crtc_atomic_enable()
1416 		VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1417 		VOP_REG_SET(vop, output, edp_en, 1);  in vop_crtc_atomic_enable()
1420 		VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);  in vop_crtc_atomic_enable()
1421 		VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1422 		VOP_REG_SET(vop, output, hdmi_en, 1);  in vop_crtc_atomic_enable()
1425 		VOP_REG_SET(vop, output, mipi_dclk_pol, 1);  in vop_crtc_atomic_enable()
1426 		VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1427 		VOP_REG_SET(vop, output, mipi_en, 1);  in vop_crtc_atomic_enable()
1428 		VOP_REG_SET(vop, output, mipi_dual_channel_en,  in vop_crtc_atomic_enable()
1432 		VOP_REG_SET(vop, output, dp_dclk_pol, 0);  in vop_crtc_atomic_enable()
1433 		VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);  in vop_crtc_atomic_enable()
1434 		VOP_REG_SET(vop, output, dp_en, 1);  in vop_crtc_atomic_enable()
1449 		VOP_REG_SET(vop, common, pre_dither_down, 1);  in vop_crtc_atomic_enable()
1451 		VOP_REG_SET(vop, common, pre_dither_down, 0);  in vop_crtc_atomic_enable()
1454 		VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);  in vop_crtc_atomic_enable()
1455 		VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);  in vop_crtc_atomic_enable()
1456 		VOP_REG_SET(vop, common, dither_down_en, 1);  in vop_crtc_atomic_enable()
1458 		VOP_REG_SET(vop, common, dither_down_en, 0);  in vop_crtc_atomic_enable()
1461 	VOP_REG_SET(vop, common, out_mode, s->output_mode);  in vop_crtc_atomic_enable()
1463 	VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);  in vop_crtc_atomic_enable()
1466 	VOP_REG_SET(vop, modeset, hact_st_end, val);  in vop_crtc_atomic_enable()
1467 	VOP_REG_SET(vop, modeset, hpost_st_end, val);  in vop_crtc_atomic_enable()
1469 	VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);  in vop_crtc_atomic_enable()
1472 	VOP_REG_SET(vop, modeset, vact_st_end, val);  in vop_crtc_atomic_enable()
1473 	VOP_REG_SET(vop, modeset, vpost_st_end, val);  in vop_crtc_atomic_enable()
1475 	VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);  in vop_crtc_atomic_enable()
1479 	VOP_REG_SET(vop, common, standby, 0);  in vop_crtc_atomic_enable()
1588 		VOP_REG_SET(vop, common, dma_stop, 0);  in vop_crtc_atomic_flush()
2067 	VOP_REG_SET(vop, misc, global_regdone_en, 1);  in vop_initial()
2068 	VOP_REG_SET(vop, common, dsp_blank, 0);  in vop_initial()