1 /* SPDX-License-Identifier: GPL-2.0-only */
4  *    Zheng Yang <zhengyang@rock-chips.com>
5  *    Yakir Yang <ykk@rock-chips.com>
18 #define m_RST_ANALOG			(1 << 6)
20 #define v_NOT_RST_ANALOG		(1 << 6)
21 #define m_RST_DIGITAL			(1 << 5)
23 #define v_NOT_RST_DIGITAL		(1 << 5)
24 #define m_REG_CLK_INV			(1 << 4)
26 #define v_REG_CLK_INV			(1 << 4)
27 #define m_VCLK_INV			(1 << 3)
29 #define v_VCLK_INV			(1 << 3)
30 #define m_REG_CLK_SOURCE		(1 << 2)
32 #define v_REG_CLK_SOURCE_SYS		(1 << 2)
33 #define m_POWER				(1 << 1)
34 #define v_PWR_ON			(0 << 1)
35 #define v_PWR_OFF			(1 << 1)
36 #define m_INT_POL			(1 << 0)
37 #define v_INT_POL_HIGH			1
41 #define m_VIDEO_INPUT_FORMAT		(7 << 1)
42 #define m_DE_SOURCE			(1 << 0)
43 #define v_VIDEO_INPUT_FORMAT(n)		(n << 1)  argument
44 #define v_DE_EXTERNAL			1
55 #define m_VIDEO_INPUT_CSP		(1 << 0)
56 #define v_VIDEO_OUTPUT_COLOR(n)		(((n) & 0x3) << 6)  argument
57 #define v_VIDEO_INPUT_BITS(n)		(n << 4)  argument
58 #define v_VIDEO_INPUT_CSP(n)		(n << 0)  argument
61 	VIDEO_INPUT_10BITS = 1,
67 #define m_VIDEO_AUTO_CSC		(1 << 7)
68 #define v_VIDEO_AUTO_CSC(n)		(n << 7)  argument
69 #define m_VIDEO_C0_C2_SWAP		(1 << 0)
70 #define v_VIDEO_C0_C2_SWAP(n)		(n << 0)  argument
73 	C0_C2_CHANGE_DISABLE = 1,
75 	AUTO_CSC_ENABLE = 1,
79 #define m_COLOR_DEPTH_NOT_INDICATED	(1 << 4)
80 #define m_SOF				(1 << 3)
81 #define m_COLOR_RANGE			(1 << 2)
82 #define m_CSC				(1 << 0)
83 #define v_COLOR_DEPTH_NOT_INDICATED(n)	((n) << 4)  argument
85 #define v_SOF_DISABLE			(1 << 3)
86 #define v_COLOR_RANGE_FULL		(1 << 2)
88 #define v_CSC_ENABLE			1
92 #define m_AVMUTE_CLEAR			(1 << 7)
93 #define m_AVMUTE_ENABLE			(1 << 6)
94 #define m_AUDIO_MUTE			(1 << 1)
95 #define m_VIDEO_BLACK			(1 << 0)
96 #define v_AVMUTE_CLEAR(n)		(n << 7)  argument
97 #define v_AVMUTE_ENABLE(n)		(n << 6)  argument
98 #define v_AUDIO_MUTE(n)			(n << 1)  argument
99 #define v_VIDEO_MUTE(n)			(n << 0)  argument
102 #define v_HSYNC_POLARITY(n)		(n << 3)  argument
103 #define v_VSYNC_POLARITY(n)		(n << 2)  argument
104 #define v_INETLACE(n)			(n << 1)  argument
105 #define v_EXTERANL_VIDEO(n)		(n << 0)  argument
126 	CTS_SOURCE_EXTERNAL = 1,
128 #define v_CTS_SOURCE(n)			(n << 7)  argument
132 	DOWNSAMPLE_1_2 = 1,
135 #define v_DOWN_SAMPLE(n)		(n << 5)  argument
139 	AUDIO_SOURCE_SPDIF = 1,
141 #define v_AUDIO_SOURCE(n)		(n << 3)  argument
143 #define v_MCLK_ENABLE(n)		(n << 2)  argument
146 	MCLK_256FS = 1,
150 #define v_MCLK_RATIO(n)			(n)  argument
165 	I2S_CHANNEL_1_2 = 1,
170 #define v_I2S_CHANNEL(n)		((n) << 2)  argument
173 	I2S_LEFT_JUSTIFIED = 1,
176 #define v_I2S_MODE(n)			(n)  argument
180 #define v_SPIDF_FREQ(n)			(n)  argument
191 #define m_AUDIO_STATUS_NLPCM		(1 << 7)
192 #define m_AUDIO_STATUS_USE		(1 << 6)
193 #define m_AUDIO_STATUS_COPYRIGHT	(1 << 5)
196 #define v_AUDIO_STATUS_NLPCM(n)		((n & 1) << 7)  argument
215 #define m_PACKET_GCP_EN			(1 << 7)
216 #define m_PACKET_MSI_EN			(1 << 6)
217 #define m_PACKET_SDI_EN			(1 << 5)
218 #define m_PACKET_VSI_EN			(1 << 4)
219 #define v_PACKET_GCP_EN(n)		((n & 1) << 7)  argument
220 #define v_PACKET_MSI_EN(n)		((n & 1) << 6)  argument
221 #define v_PACKET_SDI_EN(n)		((n & 1) << 5)  argument
222 #define v_PACKET_VSI_EN(n)		((n & 1) << 4)  argument
235 	AVI_COLOR_MODE_YCBCR422 = 1,
239 	AVI_COLORIMETRY_SMPTE_170M = 1,
244 	AVI_CODED_FRAME_ASPECT_4_3 = 1,
254 #define m_HDMI_DVI			(1 << 1)
255 #define v_HDMI_DVI(n)			(n << 1)  argument
259 #define	m_INT_ACTIVE_VSYNC		(1 << 5)
260 #define m_INT_EDID_READY		(1 << 2)
264 #define m_INT_HDCP_ERR			(1 << 7)
265 #define m_INT_BKSV_FLAG			(1 << 6)
266 #define m_INT_HDCP_OK			(1 << 4)
269 #define m_HOTPLUG			(1 << 7)
270 #define m_MASK_INT_HOTPLUG		(1 << 5)
271 #define m_INT_HOTPLUG			(1 << 1)
272 #define v_MASK_INT_HOTPLUG(n)		((n & 0x1) << 5)  argument
278 #define m_TMDS_CLK_SOURCE		(1 << 5)
280 #define v_TMDS_FROM_GEN			(1 << 5)
281 #define m_PHASE_CLK			(1 << 4)
283 #define v_SYNC_PHASE			(1 << 4)
284 #define m_TMDS_CURRENT_PWR		(1 << 3)
286 #define v_CAT_OFF_CURRENT		(1 << 3)
287 #define m_BANDGAP_PWR			(1 << 2)
289 #define v_BANDGAP_PWR_DOWN		(1 << 2)
290 #define m_PLL_PWR			(1 << 1)
291 #define v_PLL_PWR_UP			(0 << 1)
292 #define v_PLL_PWR_DOWN			(1 << 1)
293 #define m_TMDS_CHG_PWR			(1 << 0)
295 #define v_TMDS_CHG_PWR_DOWN		(1 << 0)
298 #define v_CLK_CHG_PWR(n)		((n & 1) << 3)  argument
299 #define v_DATA_CHG_PWR(n)		((n & 7) << 0)  argument
302 #define v_CLK_MAIN_DRIVER(n)		(n << 4)  argument
303 #define v_DATA_MAIN_DRIVER(n)		(n << 0)  argument
306 #define v_PRE_EMPHASIS(n)		((n & 7) << 4)  argument
307 #define v_CLK_PRE_DRIVER(n)		((n & 3) << 2)  argument
308 #define v_DATA_PRE_DRIVER(n)		((n & 3) << 0)  argument
311 #define v_FEEDBACK_DIV_LOW(n)			(n & 0xff)  argument
313 #define v_FEEDBACK_DIV_HIGH(n)			(n & 1)  argument
316 #define v_PRE_DIV_RATIO(n)		(n & 0x1f)  argument
319 #define m_ADJUST_FOR_HISENSE		(1 << 6)
320 #define m_REJECT_RX_BROADCAST		(1 << 5)
321 #define m_BUSFREETIME_ENABLE		(1 << 2)
322 #define m_REJECT_RX			(1 << 1)
323 #define m_START_TX			(1 << 0)
333 #define m_TX_DONE			(1 << 3)
334 #define m_TX_NOACK			(1 << 2)
335 #define m_TX_BROADCAST_REJ		(1 << 1)
336 #define m_TX_BUSNOTFREE			(1 << 0)
339 #define m_RX_LA_ERR			(1 << 4)
340 #define m_RX_GLITCH			(1 << 3)
341 #define m_RX_DONE			(1 << 0)