Lines Matching +full:mipi +full:- +full:dsi2
1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
274 /* dual-channel */
282 /* being a phy for other mipi hosts */
365 return -EINVAL; in max_mbps_to_parameter()
370 writel(val, dsi->base + reg); in dsi_write()
396 * ns2bc - Nanoseconds to byte clock cycles
400 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
404 * ns2ui - Nanoseconds to UI time periods
408 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
416 if (dsi->phy) in dw_mipi_dsi_phy_init()
422 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
423 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
424 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
425 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
426 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
427 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
428 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
429 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
431 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
433 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
435 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
437 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
441 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
443 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
463 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
465 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
471 * Only in this way can we get correct mipi phy pll frequency. in dw_mipi_dsi_phy_init()
476 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
522 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
532 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
534 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
538 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
539 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
546 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
558 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; in dw_mipi_dsi_get_lane_mbps()
566 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
567 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
569 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
571 dsi->format); in dw_mipi_dsi_get_lane_mbps()
575 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
582 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
587 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
588 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, in dw_mipi_dsi_get_lane_mbps()
590 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
591 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
592 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
597 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
616 * Due to the use of a "by 2 pre-scaler," the range of the in dw_mipi_dsi_get_lane_mbps()
630 delta = abs(fout - tmp); in dw_mipi_dsi_get_lane_mbps()
640 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
641 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
642 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
643 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
645 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
646 return -EINVAL; in dw_mipi_dsi_get_lane_mbps()
668 /* Table A-3 High-Speed Transition Times */
722 i--; in dw_mipi_dsi_phy_get_timing()
739 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
740 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
741 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
743 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
744 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
745 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
747 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
748 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
749 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
755 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
756 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
757 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
768 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
770 s->output_mode = ROCKCHIP_OUT_MODE_P888; in dw_mipi_dsi_encoder_atomic_check()
773 s->output_mode = ROCKCHIP_OUT_MODE_P666; in dw_mipi_dsi_encoder_atomic_check()
776 s->output_mode = ROCKCHIP_OUT_MODE_P565; in dw_mipi_dsi_encoder_atomic_check()
780 return -EINVAL; in dw_mipi_dsi_encoder_atomic_check()
783 s->output_type = DRM_MODE_CONNECTOR_DSI; in dw_mipi_dsi_encoder_atomic_check()
784 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
785 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; in dw_mipi_dsi_encoder_atomic_check()
795 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
796 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
805 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
807 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
812 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
813 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
815 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
827 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
830 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, in rockchip_dsi_drm_create_encoder()
831 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
850 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
852 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
857 match->compatible))) { in dw_mipi_dsi_rockchip_find_second()
861 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
868 /* same display device in port1-ep0 for both */ in dw_mipi_dsi_rockchip_find_second()
870 struct dw_mipi_dsi_rockchip *dsi2; in dw_mipi_dsi_rockchip_find_second() local
885 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
887 dsi2 = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_find_second()
888 if (!dsi2) { in dw_mipi_dsi_rockchip_find_second()
890 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
893 return &pdev->dev; in dw_mipi_dsi_rockchip_find_second()
919 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
920 "clock-master"); in dw_mipi_dsi_rockchip_bind()
921 master2 = of_property_read_bool(second->of_node, in dw_mipi_dsi_rockchip_bind()
922 "clock-master"); in dw_mipi_dsi_rockchip_bind()
925 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
926 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
930 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
931 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
934 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
936 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
940 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
941 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
943 return -ENODEV; in dw_mipi_dsi_rockchip_bind()
946 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
947 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
951 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
952 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
953 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
955 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
962 * With the GRF clock running, write lane and dual-mode configurations in dw_mipi_dsi_rockchip_bind()
967 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
969 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
974 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
975 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
977 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
984 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
985 dev->of_node, 0, 0); in dw_mipi_dsi_rockchip_bind()
987 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
993 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
998 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
1000 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
1001 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
1002 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1013 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1016 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1018 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1020 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1022 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1023 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1024 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1039 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1041 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1042 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1043 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1044 return -EBUSY; in dw_mipi_dsi_rockchip_host_attach()
1047 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1048 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1050 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1052 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1075 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1076 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1077 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1091 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1093 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1094 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1095 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1111 * Just make the rest of Rockchip-DRM happy in dw_mipi_dsi_rockchip_dphy_bind()
1135 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1137 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1138 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1139 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1140 return -EBUSY; in dw_mipi_dsi_dphy_init()
1143 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1144 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1146 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1150 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1151 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1155 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1157 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1161 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1162 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1163 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1171 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1173 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1174 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1175 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1184 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1186 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1187 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1188 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1195 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; in dw_mipi_dsi_dphy_configure()
1199 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); in dw_mipi_dsi_dphy_configure()
1203 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1204 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1214 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1215 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1217 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1219 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1220 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1224 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1226 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1230 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1232 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1236 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1238 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1242 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1244 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1248 /* do soc-variant specific init */ in dw_mipi_dsi_dphy_power_on()
1249 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1250 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1252 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1271 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1272 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1277 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1279 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1281 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1283 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1292 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1294 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1298 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1299 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1301 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1304 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1305 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1307 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1326 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1327 * to do this before rockchip_drm_drv tries to re-enable() any panels. in dw_mipi_dsi_rockchip_resume()
1329 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1330 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1332 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1337 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1338 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1340 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1352 struct device *dev = &pdev->dev; in dw_mipi_dsi_rockchip_probe()
1353 struct device_node *np = dev->of_node; in dw_mipi_dsi_rockchip_probe()
1363 return -ENOMEM; in dw_mipi_dsi_rockchip_probe()
1365 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in dw_mipi_dsi_rockchip_probe()
1366 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1368 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1373 if (cdata[i].reg == res->start) { in dw_mipi_dsi_rockchip_probe()
1374 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1381 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1382 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1383 return -EINVAL; in dw_mipi_dsi_rockchip_probe()
1387 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1388 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1389 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1390 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); in dw_mipi_dsi_rockchip_probe()
1394 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1395 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1396 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1401 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1402 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1403 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1408 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1410 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1418 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1419 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1420 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1421 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1428 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1429 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1430 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1431 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1437 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1438 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1440 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1443 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1444 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1445 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1446 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1447 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1448 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1451 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1453 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1454 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1455 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); in dw_mipi_dsi_rockchip_probe()
1456 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1459 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1464 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1465 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1466 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1467 if (ret != -EPROBE_DEFER) in dw_mipi_dsi_rockchip_probe()
1480 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1547 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1561 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1566 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1568 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1572 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1574 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1583 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1584 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1596 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1688 .compatible = "rockchip,px30-mipi-dsi",
1691 .compatible = "rockchip,rk3128-mipi-dsi",
1694 .compatible = "rockchip,rk3288-mipi-dsi",
1697 .compatible = "rockchip,rk3399-mipi-dsi",
1700 .compatible = "rockchip,rk3568-mipi-dsi",
1703 .compatible = "rockchip,rv1126-mipi-dsi",
1716 .name = "dw-mipi-dsi-rockchip",
1718 * For dual-DSI display, one DSI pokes at the other DSI's