Lines Matching +full:1400 +full:mhz

314 /* The table is based on 27MHz DPHY pll reference clock. */
422 	 * 000 - between   80 and  200 MHz  in dw_mipi_dsi_phy_init()
423 	 * 001 - between  200 and  300 MHz  in dw_mipi_dsi_phy_init()
424 	 * 010 - between  300 and  500 MHz  in dw_mipi_dsi_phy_init()
425 	 * 011 - between  500 and  700 MHz  in dw_mipi_dsi_phy_init()
426 	 * 100 - between  700 and  900 MHz  in dw_mipi_dsi_phy_init()
427 	 * 101 - between  900 and 1100 MHz  in dw_mipi_dsi_phy_init()
428 	 * 110 - between 1100 and 1300 MHz  in dw_mipi_dsi_phy_init()
429 	 * 111 - between 1300 and 1500 MHz  in dw_mipi_dsi_phy_init()
600 	/* constraint: 5Mhz <= Fref / N <= 40MHz */  in dw_mipi_dsi_get_lane_mbps()
604 	/* constraint: 80MHz <= Fvco <= 1500Mhz */  in dw_mipi_dsi_get_lane_mbps()
706 	HSTT(1400, 172, 64, 144, 47),