Lines Matching +full:0 +full:x00100
13 #define DU0_REG_OFFSET 0x00000
14 #define DU1_REG_OFFSET 0x30000
15 #define DU2_REG_OFFSET 0x40000
16 #define DU3_REG_OFFSET 0x70000
22 #define DSYSR 0x00000 /* display 1 */
28 #define DSYSR_TVM_MASTER (0 << 6)
32 #define DSYSR_SCM_INT_NONE (0 << 4)
37 #define DSMR 0x00004
40 #define DSMR_DIPM_DISP (0 << 25)
50 #define DSMR_CDEM_CDE (0 << 13)
56 #define DSMR_CSY_VH_OR (0 << 6)
61 #define DSSR 0x00008
62 #define DSSR_VC1FB_DSA0 (0 << 30)
67 #define DSSR_VC0FB_DSA0 (0 << 28)
80 #define DSRCR 0x0000c
87 #define DSRCR_MASK 0x0000cbff
89 #define DIER 0x00010
97 #define CPCR 0x00014
103 #define DPPR 0x00018
112 #define DEFR 0x00020
113 #define DEFR_CODE (0x7773 << 16)
118 #define DEFR_DEFE (1 << 0)
120 #define DAPCR 0x00024
121 #define DAPCR_CODE (0x7773 << 16)
123 #define DAPCR_AP1E (1 << 0)
125 #define DCPCR 0x00028
126 #define DCPCR_CODE (0x7773 << 16)
132 #define DCPCR_DCE (1 << 0)
134 #define DEFR2 0x00034
135 #define DEFR2_CODE (0x7775 << 16)
136 #define DEFR2_DEFE2G (1 << 0)
138 #define DEFR3 0x00038
139 #define DEFR3_CODE (0x7776 << 16)
146 #define DEFR3_DEFE3 (1 << 0)
148 #define DEFR4 0x0003c
149 #define DEFR4_CODE (0x7777 << 16)
153 #define DVCSR 0x000d0
154 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16))
159 #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2))
165 #define DEFR5 0x000e0
166 #define DEFR5_CODE (0x66 << 24)
167 #define DEFR5_YCRGB2_DIS (0 << 14)
172 #define DEFR5_YCRGB1_DIS (0 << 12)
177 #define DEFR5_DEFE5 (1 << 0)
179 #define DDLTR 0x000e4
180 #define DDLTR_CODE (0x7766 << 16)
185 #define DEFR6 0x000e8
186 #define DEFR6_CODE (0x7778 << 16)
187 #define DEFR6_ODPM12_DSMR (0 << 10)
191 #define DEFR6_ODPM02_DSMR (0 << 8)
200 #define DEFR7 0x000ec
201 #define DEFR7_CODE (0x7779 << 16)
209 #define DD1SSR 0x20008
218 #define DD1SRCR 0x2000c
227 #define DD1IER 0x20010
236 #define DEFR8 0x20020
237 #define DEFR8_CODE (0x7790 << 16)
241 #define DEFR8_DEFE8 (1 << 0)
243 #define DOFLR 0x20024
244 #define DOFLR_CODE (0x7790 << 16)
256 #define DOFLR_RGBFL0 (1 << 0)
258 #define DIDSR 0x20028
259 #define DIDSR_CODE (0x7790 << 16)
260 #define DIDSR_LDCS_DCLKIN(n) (0 << (8 + (n) * 2))
268 #define DEFR10 0x20038
269 #define DEFR10_CODE (0x7795 << 16)
270 #define DEFR10_VSPF1_RGB (0 << 14)
272 #define DEFR10_DOCF1_RGB (0 << 12)
274 #define DEFR10_YCDF0_YCBCR444 (0 << 11)
276 #define DEFR10_VSPF0_RGB (0 << 10)
278 #define DEFR10_DOCF0_RGB (0 << 8)
280 #define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */
281 #define DEFR10_DEFE10 (1 << 0)
283 #define DPLLCR 0x20044
284 #define DPLLCR_CODE (0x95 << 24)
292 #define DPLLCR_INCS_DOTCLKIN0 (0 << 0)
295 #define DPLLC2R 0x20048
296 #define DPLLC2R_CODE (0x95 << 24)
299 #define DPLLC2R_FDPLL(n) ((n) << 0)
305 #define HDSR 0x00040
306 #define HDER 0x00044
307 #define VDSR 0x00048
308 #define VDER 0x0004c
309 #define HCR 0x00050
310 #define HSWR 0x00054
311 #define VCR 0x00058
312 #define VSPR 0x0005c
313 #define EQWR 0x00060
314 #define SPWR 0x00064
315 #define CLAMPSR 0x00070
316 #define CLAMPWR 0x00074
317 #define DESR 0x00078
318 #define DEWR 0x0007c
324 #define CP1TR 0x00080
325 #define CP2TR 0x00084
326 #define CP3TR 0x00088
327 #define CP4TR 0x0008c
329 #define DOOR 0x00090
331 #define CDER 0x00094
333 #define BPOR 0x00098
336 #define RINTOFSR 0x0009c
338 #define DSHPR 0x000c8
339 #define DSHPR_CODE (0x7776 << 16)
340 #define DSHPR_PRIH (0xa << 4)
341 #define DSHPR_PRIL_BPP16 (0x8 << 0)
342 #define DSHPR_PRIL_BPP32 (0x9 << 0)
348 #define PLANE_OFF 0x00100
350 #define PnMR 0x00100 /* plane 1 */
351 #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */
356 #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */
359 #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */
363 #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */
368 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
372 #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */
373 #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */
374 #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */
375 #define PnMR_DDDF_YC (3 << 0) /* YC */
376 #define PnMR_DDDF_MASK (3 << 0)
378 #define PnMWR 0x00104
380 #define PnALPHAR 0x00108
381 #define PnALPHAR_ABIT_1 (0 << 12)
385 #define PnDSXR 0x00110
386 #define PnDSYR 0x00114
387 #define PnDPXR 0x00118
388 #define PnDPYR 0x0011c
390 #define PnDSA0R 0x00120
391 #define PnDSA1R 0x00124
392 #define PnDSA2R 0x00128
393 #define PnDSA_MASK 0xfffffff0
395 #define PnSPXR 0x00130
396 #define PnSPYR 0x00134
397 #define PnWASPR 0x00138
398 #define PnWAMWR 0x0013c
400 #define PnBTR 0x00140
402 #define PnTC1R 0x00144
403 #define PnTC2R 0x00148
404 #define PnTC3R 0x0014c
405 #define PnTC3R_CODE (0x66 << 24)
407 #define PnMLR 0x00150
409 #define PnSWAPR 0x00180
414 #define PnSWAPR_SPBY (1 << 0)
416 #define PnDDCR 0x00184
417 #define PnDDCR_CODE (0x7775 << 16)
421 #define PnDDCR2 0x00188
422 #define PnDDCR2_CODE (0x7776 << 16)
426 #define PnDDCR2_DIVY (1 << 0)
428 #define PnDDCR4 0x00190
429 #define PnDDCR4_CODE (0x7766 << 16)
431 #define PnDDCR4_SDFS_RGB (0 << 4)
434 #define PnDDCR4_EDF_NONE (0 << 0)
435 #define PnDDCR4_EDF_ARGB8888 (1 << 0)
436 #define PnDDCR4_EDF_RGB888 (2 << 0)
437 #define PnDDCR4_EDF_RGB666 (3 << 0)
438 #define PnDDCR4_EDF_MASK (7 << 0)
440 #define APnMR 0x0a100
443 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */
446 #define APnMWR 0x0a104
448 #define APnDSXR 0x0a110
449 #define APnDSYR 0x0a114
450 #define APnDPXR 0x0a118
451 #define APnDPYR 0x0a11c
453 #define APnDSA0R 0x0a120
454 #define APnDSA1R 0x0a124
455 #define APnDSA2R 0x0a128
457 #define APnSPXR 0x0a130
458 #define APnSPYR 0x0a134
459 #define APnWASPR 0x0a138
460 #define APnWAMWR 0x0a13c
462 #define APnBTR 0x0a140
464 #define APnMLR 0x0a150
465 #define APnSWAPR 0x0a180
471 #define DCMR 0x0c100
472 #define DCMWR 0x0c104
473 #define DCSAR 0x0c120
474 #define DCMLR 0x0c150
480 #define CP1_000R 0x01000
481 #define CP1_255R 0x013fc
482 #define CP2_000R 0x02000
483 #define CP2_255R 0x023fc
484 #define CP3_000R 0x03000
485 #define CP3_255R 0x033fc
486 #define CP4_000R 0x04000
487 #define CP4_255R 0x043fc
493 #define ESCR02 0x10000
494 #define ESCR13 0x01000
496 #define ESCR_DCLKSEL_DCLKIN (0 << 20)
500 #define ESCR_SYNCSEL_OFF (0 << 8)
503 #define ESCR_FRQSEL_MASK (0x3f << 0)
505 #define OTAR02 0x10004
506 #define OTAR13 0x01004
512 #define DORCR 0x11000
515 #define DORCR_PG1D_DS0 (0 << 24)
521 #define DORCR_PG0D_DS0 (0 << 16)
527 #define DORCR_DPRS (1 << 0)
529 #define DPTSR 0x11004
533 #define DAPTSR 0x11008
537 #define DS1PR 0x11020
538 #define DS2PR 0x11024
544 #define YNCR 0x11080
545 #define YNOR 0x11084
546 #define CRNOR 0x11088
547 #define CBNOR 0x1108c
548 #define RCRCR 0x11090
549 #define GCRCR 0x11094
550 #define GCBCR 0x11098
551 #define BCBCR 0x1109c