Lines Matching +full:diff +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
35 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read()
37 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read()
42 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write()
44 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write()
49 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr()
51 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr()
52 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr()
57 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_set()
59 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_set()
60 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set); in rcar_du_crtc_set()
65 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_dsysr_clr_set()
67 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set; in rcar_du_crtc_dsysr_clr_set()
68 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr); in rcar_du_crtc_dsysr_clr_set()
71 /* -----------------------------------------------------------------------------
87 unsigned long best_diff = (unsigned long)-1; in rcar_du_dpll_divider()
88 unsigned long diff; in rcar_du_dpll_divider() local
95 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out in rcar_du_dpll_divider()
96 * +-> | | | in rcar_du_dpll_divider()
98 * +---------------- [1/N] <------------+ in rcar_du_dpll_divider()
100 * fclkout = fvco / P / FDPLL -- (1) in rcar_du_dpll_divider()
104 * fvco = fin * P * N / M -- (2) in rcar_du_dpll_divider()
122 for (n = 119; n > 38; n--) { in rcar_du_dpll_divider()
124 * This code only runs on 64-bit architectures, the in rcar_du_dpll_divider()
125 * unsigned long type can thus be used for 64-bit in rcar_du_dpll_divider()
127 * warning on 32-bit architectures. in rcar_du_dpll_divider()
144 diff = abs((long)output - (long)target); in rcar_du_dpll_divider()
145 if (best_diff > diff) { in rcar_du_dpll_divider()
146 best_diff = diff; in rcar_du_dpll_divider()
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
153 if (diff == 0) in rcar_du_dpll_divider()
160 dev_dbg(rcrtc->dev->dev, in rcar_du_dpll_divider()
161 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n", in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
168 unsigned long diff; member
176 unsigned long diff; in rcar_du_escr_divider() local
183 if (params->diff == 0) in rcar_du_escr_divider()
191 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1; in rcar_du_escr_divider()
192 diff = abs(rate / (div + 1) - target); in rcar_du_escr_divider()
198 if (diff < params->diff) { in rcar_du_escr_divider()
199 params->clk = clk; in rcar_du_escr_divider()
200 params->rate = rate; in rcar_du_escr_divider()
201 params->diff = diff; in rcar_du_escr_divider()
202 params->escr = escr | div; in rcar_du_escr_divider()
208 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; in rcar_du_crtc_set_display_timing()
209 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_set_display_timing()
210 unsigned long mode_clock = mode->clock * 1000; in rcar_du_crtc_set_display_timing()
215 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) { in rcar_du_crtc_set_display_timing()
223 * DU channels that have a display PLL can't use the internal in rcar_du_crtc_set_display_timing()
226 extclk = clk_get_rate(rcrtc->extclock); in rcar_du_crtc_set_display_timing()
234 if (rcrtc->index == 1) in rcar_du_crtc_set_display_timing()
241 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); in rcar_du_crtc_set_display_timing()
244 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) || in rcar_du_crtc_set_display_timing()
245 rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) { in rcar_du_crtc_set_display_timing()
254 struct du_clk_params params = { .diff = (unsigned long)-1 }; in rcar_du_crtc_set_display_timing()
256 rcar_du_escr_divider(rcrtc->clock, mode_clock, in rcar_du_crtc_set_display_timing()
258 if (rcrtc->extclock) in rcar_du_crtc_set_display_timing()
259 rcar_du_escr_divider(rcrtc->extclock, mode_clock, in rcar_du_crtc_set_display_timing()
262 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n", in rcar_du_crtc_set_display_timing()
263 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext", in rcar_du_crtc_set_display_timing()
271 * The ESCR register only exists in DU channels that can output to an in rcar_du_crtc_set_display_timing()
272 * LVDS or DPAT, and the OTAR register in DU channels that can output in rcar_du_crtc_set_display_timing()
275 if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs | in rcar_du_crtc_set_display_timing()
276 rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs | in rcar_du_crtc_set_display_timing()
277 rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs | in rcar_du_crtc_set_display_timing()
278 rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) & in rcar_du_crtc_set_display_timing()
279 BIT(rcrtc->index)) { in rcar_du_crtc_set_display_timing()
280 dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); in rcar_du_crtc_set_display_timing()
282 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); in rcar_du_crtc_set_display_timing()
285 if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs | in rcar_du_crtc_set_display_timing()
286 rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) & in rcar_du_crtc_set_display_timing()
287 BIT(rcrtc->index)) in rcar_du_crtc_set_display_timing()
288 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); in rcar_du_crtc_set_display_timing()
291 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) in rcar_du_crtc_set_display_timing()
292 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0) in rcar_du_crtc_set_display_timing()
293 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0) in rcar_du_crtc_set_display_timing()
303 if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2)) in rcar_du_crtc_set_display_timing()
307 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - in rcar_du_crtc_set_display_timing()
309 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + in rcar_du_crtc_set_display_timing()
310 mode->hdisplay - hdse_offset); in rcar_du_crtc_set_display_timing()
311 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - in rcar_du_crtc_set_display_timing()
312 mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
313 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); in rcar_du_crtc_set_display_timing()
315 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
316 mode->crtc_vsync_end - 2); in rcar_du_crtc_set_display_timing()
317 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
318 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
319 mode->crtc_vdisplay - 2); in rcar_du_crtc_set_display_timing()
320 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal - in rcar_du_crtc_set_display_timing()
321 mode->crtc_vsync_end + in rcar_du_crtc_set_display_timing()
322 mode->crtc_vsync_start - 1); in rcar_du_crtc_set_display_timing()
323 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); in rcar_du_crtc_set_display_timing()
325 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); in rcar_du_crtc_set_display_timing()
326 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); in rcar_du_crtc_set_display_timing()
331 return plane->plane.state->normalized_zpos; in plane_zpos()
337 return to_rcar_plane_state(plane->plane.state)->format; in plane_format()
343 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_update_planes()
351 for (i = 0; i < rcrtc->group->num_planes; ++i) { in rcar_du_crtc_update_planes()
352 struct rcar_du_plane *plane = &rcrtc->group->planes[i]; in rcar_du_crtc_update_planes()
355 if (plane->plane.state->crtc != &rcrtc->crtc || in rcar_du_crtc_update_planes()
356 !plane->plane.state->visible) in rcar_du_crtc_update_planes()
360 for (j = num_planes++; j > 0; --j) { in rcar_du_crtc_update_planes()
361 if (plane_zpos(planes[j-1]) <= plane_zpos(plane)) in rcar_du_crtc_update_planes()
363 planes[j] = planes[j-1]; in rcar_du_crtc_update_planes()
367 prio += plane_format(plane)->planes * 4; in rcar_du_crtc_update_planes()
372 struct drm_plane_state *state = plane->plane.state; in rcar_du_crtc_update_planes()
373 unsigned int index = to_rcar_plane_state(state)->hwindex; in rcar_du_crtc_update_planes()
375 prio -= 4; in rcar_du_crtc_update_planes()
379 if (plane_format(plane)->planes == 2) { in rcar_du_crtc_update_planes()
382 prio -= 4; in rcar_du_crtc_update_planes()
390 if (rcdu->info->gen < 3) { in rcar_du_crtc_update_planes()
391 dspr = (rcrtc->index % 2) + 1; in rcar_du_crtc_update_planes()
392 hwplanes = 1 << (rcrtc->index % 2); in rcar_du_crtc_update_planes()
394 dspr = (rcrtc->index % 2) ? 3 : 1; in rcar_du_crtc_update_planes()
395 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0); in rcar_du_crtc_update_planes()
408 mutex_lock(&rcrtc->group->lock); in rcar_du_crtc_update_planes()
410 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes in rcar_du_crtc_update_planes()
411 : rcrtc->group->dptsr_planes & ~hwplanes; in rcar_du_crtc_update_planes()
413 if (dptsr_planes != rcrtc->group->dptsr_planes) { in rcar_du_crtc_update_planes()
414 rcar_du_group_write(rcrtc->group, DPTSR, in rcar_du_crtc_update_planes()
416 rcrtc->group->dptsr_planes = dptsr_planes; in rcar_du_crtc_update_planes()
418 if (rcrtc->group->used_crtcs) in rcar_du_crtc_update_planes()
419 rcar_du_group_restart(rcrtc->group); in rcar_du_crtc_update_planes()
423 if (rcrtc->group->need_restart) in rcar_du_crtc_update_planes()
424 rcar_du_group_restart(rcrtc->group); in rcar_du_crtc_update_planes()
426 mutex_unlock(&rcrtc->group->lock); in rcar_du_crtc_update_planes()
428 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, in rcar_du_crtc_update_planes()
432 /* -----------------------------------------------------------------------------
439 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_finish_page_flip()
442 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
443 event = rcrtc->event; in rcar_du_crtc_finish_page_flip()
444 rcrtc->event = NULL; in rcar_du_crtc_finish_page_flip()
445 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
450 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
451 drm_crtc_send_vblank_event(&rcrtc->crtc, event); in rcar_du_crtc_finish_page_flip()
452 wake_up(&rcrtc->flip_wait); in rcar_du_crtc_finish_page_flip()
453 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_finish_page_flip()
455 drm_crtc_vblank_put(&rcrtc->crtc); in rcar_du_crtc_finish_page_flip()
460 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_page_flip_pending()
464 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_page_flip_pending()
465 pending = rcrtc->event != NULL; in rcar_du_crtc_page_flip_pending()
466 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_page_flip_pending()
473 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_wait_page_flip()
475 if (wait_event_timeout(rcrtc->flip_wait, in rcar_du_crtc_wait_page_flip()
480 dev_warn(rcdu->dev, "page flip timeout\n"); in rcar_du_crtc_wait_page_flip()
485 /* -----------------------------------------------------------------------------
492 struct drm_property_blob *drm_lut = state->gamma_lut; in rcar_du_cmm_check()
494 struct device *dev = rcrtc->dev->dev; in rcar_du_cmm_check()
502 drm_lut->length); in rcar_du_cmm_check()
503 return -EINVAL; in rcar_du_cmm_check()
511 struct drm_property_blob *drm_lut = crtc->state->gamma_lut; in rcar_du_cmm_setup()
515 if (!rcrtc->cmm) in rcar_du_cmm_setup()
519 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data; in rcar_du_cmm_setup()
521 rcar_cmm_setup(rcrtc->cmm, &cmm_config); in rcar_du_cmm_setup()
524 /* -----------------------------------------------------------------------------
536 rcar_du_group_set_routing(rcrtc->group); in rcar_du_crtc_setup()
539 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); in rcar_du_crtc_setup()
542 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_setup()
546 drm_crtc_vblank_on(&rcrtc->crtc); in rcar_du_crtc_setup()
554 * Guard against double-get, as the function is called from both the in rcar_du_crtc_get()
557 if (rcrtc->initialized) in rcar_du_crtc_get()
560 ret = clk_prepare_enable(rcrtc->clock); in rcar_du_crtc_get()
564 ret = clk_prepare_enable(rcrtc->extclock); in rcar_du_crtc_get()
568 ret = rcar_du_group_get(rcrtc->group); in rcar_du_crtc_get()
573 rcrtc->initialized = true; in rcar_du_crtc_get()
578 clk_disable_unprepare(rcrtc->extclock); in rcar_du_crtc_get()
580 clk_disable_unprepare(rcrtc->clock); in rcar_du_crtc_get()
586 rcar_du_group_put(rcrtc->group); in rcar_du_crtc_put()
588 clk_disable_unprepare(rcrtc->extclock); in rcar_du_crtc_put()
589 clk_disable_unprepare(rcrtc->clock); in rcar_du_crtc_put()
591 rcrtc->initialized = false; in rcar_du_crtc_put()
603 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; in rcar_du_crtc_start()
608 rcar_du_group_start_stop(rcrtc->group, true); in rcar_du_crtc_start()
613 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_disable_planes()
614 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_disable_planes()
627 spin_lock_irq(&rcrtc->vblank_lock); in rcar_du_crtc_disable_planes()
628 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); in rcar_du_crtc_disable_planes()
630 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1; in rcar_du_crtc_disable_planes()
631 spin_unlock_irq(&rcrtc->vblank_lock); in rcar_du_crtc_disable_planes()
633 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0, in rcar_du_crtc_disable_planes()
635 dev_warn(rcdu->dev, "vertical blanking timeout\n"); in rcar_du_crtc_disable_planes()
642 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_stop()
666 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_stop()
669 if (rcrtc->cmm) in rcar_du_crtc_stop()
670 rcar_cmm_disable(rcrtc->cmm); in rcar_du_crtc_stop()
679 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC)) in rcar_du_crtc_stop()
683 rcar_du_group_start_stop(rcrtc->group, false); in rcar_du_crtc_stop()
686 /* -----------------------------------------------------------------------------
704 rstate->outputs = 0; in rcar_du_crtc_atomic_check()
706 drm_for_each_encoder_mask(encoder, crtc->dev, in rcar_du_crtc_atomic_check()
707 crtc_state->encoder_mask) { in rcar_du_crtc_atomic_check()
711 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) in rcar_du_crtc_atomic_check()
715 rstate->outputs |= BIT(renc->output); in rcar_du_crtc_atomic_check()
725 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state); in rcar_du_crtc_atomic_enable()
726 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_atomic_enable()
728 if (rcrtc->cmm) in rcar_du_crtc_atomic_enable()
729 rcar_cmm_enable(rcrtc->cmm); in rcar_du_crtc_atomic_enable()
738 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { in rcar_du_crtc_atomic_enable()
739 bool dot_clk_only = rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0); in rcar_du_crtc_atomic_enable()
740 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index]; in rcar_du_crtc_atomic_enable()
742 &crtc->state->adjusted_mode; in rcar_du_crtc_atomic_enable()
744 rcar_lvds_pclk_enable(bridge, mode->clock * 1000, dot_clk_only); in rcar_du_crtc_atomic_enable()
751 if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) && in rcar_du_crtc_atomic_enable()
752 (rstate->outputs & in rcar_du_crtc_atomic_enable()
754 struct drm_bridge *bridge = rcdu->dsi[rcrtc->index]; in rcar_du_crtc_atomic_enable()
776 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_atomic_disable()
781 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) { in rcar_du_crtc_atomic_disable()
782 bool dot_clk_only = rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0); in rcar_du_crtc_atomic_disable()
783 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index]; in rcar_du_crtc_atomic_disable()
793 if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) && in rcar_du_crtc_atomic_disable()
794 (rstate->outputs & in rcar_du_crtc_atomic_disable()
796 struct drm_bridge *bridge = rcdu->dsi[rcrtc->index]; in rcar_du_crtc_atomic_disable()
805 spin_lock_irq(&crtc->dev->event_lock); in rcar_du_crtc_atomic_disable()
806 if (crtc->state->event) { in rcar_du_crtc_atomic_disable()
807 drm_crtc_send_vblank_event(crtc, crtc->state->event); in rcar_du_crtc_atomic_disable()
808 crtc->state->event = NULL; in rcar_du_crtc_atomic_disable()
810 spin_unlock_irq(&crtc->dev->event_lock); in rcar_du_crtc_atomic_disable()
818 WARN_ON(!crtc->state->enable); in rcar_du_crtc_atomic_begin()
825 * operation in .atomic_enable() will in that case be a no-op, and the in rcar_du_crtc_atomic_begin()
829 * following get call will be a no-op. There is thus no need to balance in rcar_du_crtc_atomic_begin()
835 if (crtc->state->color_mgmt_changed && !crtc->state->active_changed) in rcar_du_crtc_atomic_begin()
838 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_atomic_begin()
846 struct drm_device *dev = rcrtc->crtc.dev; in rcar_du_crtc_atomic_flush()
851 if (crtc->state->event) { in rcar_du_crtc_atomic_flush()
854 spin_lock_irqsave(&dev->event_lock, flags); in rcar_du_crtc_atomic_flush()
855 rcrtc->event = crtc->state->event; in rcar_du_crtc_atomic_flush()
856 crtc->state->event = NULL; in rcar_du_crtc_atomic_flush()
857 spin_unlock_irqrestore(&dev->event_lock, flags); in rcar_du_crtc_atomic_flush()
860 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) in rcar_du_crtc_atomic_flush()
869 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_mode_valid()
870 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; in rcar_du_crtc_mode_valid()
883 if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2)) in rcar_du_crtc_mode_valid()
886 if (mode->htotal - mode->hsync_start < min_sync_porch) in rcar_du_crtc_mode_valid()
889 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1); in rcar_du_crtc_mode_valid()
907 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_crc_init()
910 int i = -1; in rcar_du_crtc_crc_init()
913 if (rcdu->info->gen < 3) in rcar_du_crtc_crc_init()
917 count = rcrtc->vsp->num_planes + 1; in rcar_du_crtc_crc_init()
927 for (i = 0; i < rcrtc->vsp->num_planes; ++i) { in rcar_du_crtc_crc_init()
928 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane; in rcar_du_crtc_crc_init()
931 sprintf(name, "plane%u", plane->base.id); in rcar_du_crtc_crc_init()
937 rcrtc->sources = sources; in rcar_du_crtc_crc_init()
938 rcrtc->sources_count = count; in rcar_du_crtc_crc_init()
944 i--; in rcar_du_crtc_crc_init()
953 if (!rcrtc->sources) in rcar_du_crtc_crc_cleanup()
956 for (i = 0; i < rcrtc->sources_count; i++) in rcar_du_crtc_crc_cleanup()
957 kfree(rcrtc->sources[i]); in rcar_du_crtc_crc_cleanup()
958 kfree(rcrtc->sources); in rcar_du_crtc_crc_cleanup()
960 rcrtc->sources = NULL; in rcar_du_crtc_crc_cleanup()
961 rcrtc->sources_count = 0; in rcar_du_crtc_crc_cleanup()
970 if (WARN_ON(!crtc->state)) in rcar_du_crtc_atomic_duplicate_state()
973 state = to_rcar_crtc_state(crtc->state); in rcar_du_crtc_atomic_duplicate_state()
978 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state); in rcar_du_crtc_atomic_duplicate_state()
980 return ©->state; in rcar_du_crtc_atomic_duplicate_state()
1003 if (crtc->state) { in rcar_du_crtc_reset()
1004 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state); in rcar_du_crtc_reset()
1005 crtc->state = NULL; in rcar_du_crtc_reset()
1012 state->crc.source = VSP1_DU_CRC_NONE; in rcar_du_crtc_reset()
1013 state->crc.index = 0; in rcar_du_crtc_reset()
1015 __drm_atomic_helper_crtc_reset(crtc, &state->state); in rcar_du_crtc_reset()
1024 rcrtc->vblank_enable = true; in rcar_du_crtc_enable_vblank()
1034 rcrtc->vblank_enable = false; in rcar_du_crtc_disable_vblank()
1065 for (i = 0; i < rcrtc->vsp->num_planes; ++i) { in rcar_du_crtc_parse_crc_source()
1066 if (index == rcrtc->vsp->planes[i].plane.base.id) in rcar_du_crtc_parse_crc_source()
1071 return -EINVAL; in rcar_du_crtc_parse_crc_source()
1083 return -EINVAL; in rcar_du_crtc_verify_crc_source()
1095 *count = rcrtc->sources_count; in rcar_du_crtc_get_crc_sources()
1096 return rcrtc->sources; in rcar_du_crtc_get_crc_sources()
1119 state = drm_atomic_state_alloc(crtc->dev); in rcar_du_crtc_set_crc_source()
1121 ret = -ENOMEM; in rcar_du_crtc_set_crc_source()
1125 state->acquire_ctx = &ctx; in rcar_du_crtc_set_crc_source()
1133 rcrtc_state->crc.source = source; in rcar_du_crtc_set_crc_source()
1134 rcrtc_state->crc.index = index; in rcar_du_crtc_set_crc_source()
1141 if (ret == -EDEADLK) { in rcar_du_crtc_set_crc_source()
1181 /* -----------------------------------------------------------------------------
1188 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_irq()
1192 spin_lock(&rcrtc->vblank_lock); in rcar_du_crtc_irq()
1203 if (rcrtc->vblank_count) { in rcar_du_crtc_irq()
1204 if (--rcrtc->vblank_count == 0) in rcar_du_crtc_irq()
1205 wake_up(&rcrtc->vblank_wait); in rcar_du_crtc_irq()
1209 spin_unlock(&rcrtc->vblank_lock); in rcar_du_crtc_irq()
1212 if (rcdu->info->gen < 3) { in rcar_du_crtc_irq()
1213 drm_crtc_handle_vblank(&rcrtc->crtc); in rcar_du_crtc_irq()
1223 /* -----------------------------------------------------------------------------
1234 struct rcar_du_device *rcdu = rgrp->dev; in rcar_du_crtc_create()
1235 struct platform_device *pdev = to_platform_device(rcdu->dev); in rcar_du_crtc_create()
1236 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex]; in rcar_du_crtc_create()
1237 struct drm_crtc *crtc = &rcrtc->crtc; in rcar_du_crtc_create()
1254 rcrtc->clock = devm_clk_get(rcdu->dev, name); in rcar_du_crtc_create()
1255 if (IS_ERR(rcrtc->clock)) { in rcar_du_crtc_create()
1256 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex); in rcar_du_crtc_create()
1257 return PTR_ERR(rcrtc->clock); in rcar_du_crtc_create()
1261 clk = devm_clk_get(rcdu->dev, clk_name); in rcar_du_crtc_create()
1263 rcrtc->extclock = clk; in rcar_du_crtc_create()
1264 } else if (PTR_ERR(clk) == -EPROBE_DEFER) { in rcar_du_crtc_create()
1265 return -EPROBE_DEFER; in rcar_du_crtc_create()
1266 } else if (rcdu->info->dpll_mask & BIT(hwindex)) { in rcar_du_crtc_create()
1268 * DU channels that have a display PLL can't use the internal in rcar_du_crtc_create()
1272 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret); in rcar_du_crtc_create()
1276 init_waitqueue_head(&rcrtc->flip_wait); in rcar_du_crtc_create()
1277 init_waitqueue_head(&rcrtc->vblank_wait); in rcar_du_crtc_create()
1278 spin_lock_init(&rcrtc->vblank_lock); in rcar_du_crtc_create()
1280 rcrtc->dev = rcdu; in rcar_du_crtc_create()
1281 rcrtc->group = rgrp; in rcar_du_crtc_create()
1282 rcrtc->mmio_offset = mmio_offsets[hwindex]; in rcar_du_crtc_create()
1283 rcrtc->index = hwindex; in rcar_du_crtc_create()
1284 rcrtc->dsysr = rcrtc->index % 2 ? 0 : DSYSR_DRES; in rcar_du_crtc_create()
1287 rcrtc->dsysr |= DSYSR_TVM_TVSYNC; in rcar_du_crtc_create()
1290 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane; in rcar_du_crtc_create()
1292 primary = &rgrp->planes[swindex % 2].plane; in rcar_du_crtc_create()
1294 ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL, in rcar_du_crtc_create()
1295 rcdu->info->gen <= 2 ? in rcar_du_crtc_create()
1302 if (rcdu->cmms[swindex]) { in rcar_du_crtc_create()
1303 rcrtc->cmm = rcdu->cmms[swindex]; in rcar_du_crtc_create()
1304 rgrp->cmms_mask |= BIT(hwindex % 2); in rcar_du_crtc_create()
1323 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex); in rcar_du_crtc_create()
1327 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags, in rcar_du_crtc_create()
1328 dev_name(rcdu->dev), rcrtc); in rcar_du_crtc_create()
1330 dev_err(rcdu->dev, in rcar_du_crtc_create()