45 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v2_2_fence_emit()
47 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
49 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
50 	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);  in uvd_v2_2_fence_emit()
51 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
52 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
54 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
55 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
56 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
57 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
58 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
79 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));  in uvd_v2_2_semaphore_emit()
80 	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
82 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));  in uvd_v2_2_semaphore_emit()
83 	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
85 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));  in uvd_v2_2_semaphore_emit()
86 	radeon_ring_write(ring, emit_wait ? 1 : 0);  in uvd_v2_2_semaphore_emit()
104 	/* RV770 uses V1.0 MC */  in uvd_v2_2_resume()
112 	/* program the VCPU memory controller bits 0-27 */  in uvd_v2_2_resume()
130 	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v2_2_resume()
131 	WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v2_2_resume()
134 	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v2_2_resume()
135 	WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v2_2_resume()
142 		chip_id = 0x01000005;  in uvd_v2_2_resume()
145 		chip_id = 0x01000006;  in uvd_v2_2_resume()
148 		chip_id = 0x01000007;  in uvd_v2_2_resume()
152 		chip_id = 0x01000008;  in uvd_v2_2_resume()
155 		chip_id = 0x01000009;  in uvd_v2_2_resume()
158 		chip_id = 0x0100000a;  in uvd_v2_2_resume()
161 		chip_id = 0x0100000b;  in uvd_v2_2_resume()
165 		chip_id = 0x0100000c;  in uvd_v2_2_resume()
168 		chip_id = 0x0100000e;  in uvd_v2_2_resume()
171 		chip_id = 0x0100000f;  in uvd_v2_2_resume()
174 		chip_id = 0x01000010;  in uvd_v2_2_resume()
177 		chip_id = 0x01000011;  in uvd_v2_2_resume()
180 		chip_id = 0x01000012;  in uvd_v2_2_resume()
183 		chip_id = 0x01000014;  in uvd_v2_2_resume()
186 		chip_id = 0x01000015;  in uvd_v2_2_resume()
190 		chip_id = 0x01000016;  in uvd_v2_2_resume()
193 		chip_id = 0x01000017;  in uvd_v2_2_resume()
198 	return 0;  in uvd_v2_2_resume()