Lines Matching +full:0 +full:x644
30 #define RCU_FW_VERSION 0x30c
32 #define RCU_PWR_GATING_SEQ0 0x408
33 #define RCU_PWR_GATING_SEQ1 0x40c
34 #define RCU_PWR_GATING_CNTL 0x410
35 # define PWR_GATING_EN (1 << 0)
36 # define RSVD_MASK (0x3 << 1)
38 # define PCV_MASK (0x1f << 3)
41 # define PCP_MASK (0xf << 8)
44 # define RPW_MASK (0xf << 16)
47 # define ID_MASK (0xf << 24)
50 # define PGS_MASK (0xf << 28)
53 #define RCU_ALTVDDNB_NOTIFY 0x430
54 #define RCU_LCLK_SCALING_CNTL 0x434
55 # define LCLK_SCALING_EN (1 << 0)
58 # define LCLK_SCALING_TIMER_PRESCALER_MASK (0xf << 4)
61 # define LCLK_SCALING_TIMER_PERIOD_MASK (0xf << 16)
64 #define RCU_PWR_GATING_CNTL_2 0x4a0
65 # define MPPU(x) ((x) << 0)
66 # define MPPU_MASK (0xffff << 0)
67 # define MPPU_SHIFT 0
69 # define MPPD_MASK (0xffff << 16)
71 #define RCU_PWR_GATING_CNTL_3 0x4a4
72 # define DPPU(x) ((x) << 0)
73 # define DPPU_MASK (0xffff << 0)
74 # define DPPU_SHIFT 0
76 # define DPPD_MASK (0xffff << 16)
78 #define RCU_PWR_GATING_CNTL_4 0x4a8
79 # define RT(x) ((x) << 0)
80 # define RT_MASK (0xffff << 0)
81 # define RT_SHIFT 0
83 # define IT_MASK (0xffff << 16)
87 #define RCU_PWR_GATING_CNTL_5 0x504
88 #define RCU_GPU_BOOST_DISABLE 0x508
90 #define MCU_M3ARB_INDEX 0x504
91 #define MCU_M3ARB_PARAMS 0x508
93 #define RCU_GNB_PWR_REP_TIMER_CNTL 0x50C
95 #define RCU_SclkDpmTdpLimit01 0x514
96 #define RCU_SclkDpmTdpLimit23 0x518
97 #define RCU_SclkDpmTdpLimit47 0x51C
98 #define RCU_SclkDpmTdpLimitPG 0x520
100 #define GNB_TDP_LIMIT 0x540
101 #define RCU_BOOST_MARGIN 0x544
102 #define RCU_THROTTLE_MARGIN 0x548
104 #define SMU_PCIE_PG_ARGS 0x58C
105 #define SMU_PCIE_PG_ARGS_2 0x598
106 #define SMU_PCIE_PG_ARGS_3 0x59C
109 #define RCU_STATUS 0x11c
123 #define GFX_INT_REQ 0x120
124 # define INT_REQ (1 << 0)
126 # define SERV_INDEX_MASK (0xff << 1)
128 #define GFX_INT_STATUS 0x124
129 # define INT_ACK (1 << 0)
132 #define CG_SCLK_CNTL 0x600
133 # define SCLK_DIVIDER(x) ((x) << 0)
134 # define SCLK_DIVIDER_MASK (0x7f << 0)
135 # define SCLK_DIVIDER_SHIFT 0
136 #define CG_SCLK_STATUS 0x604
139 #define CG_DCLK_CNTL 0x610
140 # define DCLK_DIVIDER_MASK 0x7f
142 #define CG_DCLK_STATUS 0x614
143 # define DCLK_STATUS (1 << 0)
144 #define CG_VCLK_CNTL 0x618
145 # define VCLK_DIVIDER_MASK 0x7f
147 #define CG_VCLK_STATUS 0x61c
149 #define GENERAL_PWRMGT 0x63c
152 #define SCLK_PWRMGT_CNTL 0x644
153 # define SCLK_PWRMGT_OFF (1 << 0)
168 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
170 # define TARG_SCLK_INDEX_MASK (0x7 << 6)
173 # define CURR_SCLK_INDEX_MASK (0x7 << 9)
176 # define TARG_INDEX_MASK (0x7 << 12)
179 # define CURR_INDEX_MASK (0x7 << 15)
182 #define CG_SCLK_DPM_CTRL 0x684
183 # define SCLK_FSTATE_0_DIV(x) ((x) << 0)
184 # define SCLK_FSTATE_0_DIV_MASK (0x7f << 0)
185 # define SCLK_FSTATE_0_DIV_SHIFT 0
188 # define SCLK_FSTATE_1_DIV_MASK (0x7f << 8)
192 # define SCLK_FSTATE_2_DIV_MASK (0x7f << 16)
196 # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24)
199 #define CG_SCLK_DPM_CTRL_2 0x688
200 #define CG_GCOOR 0x68c
201 # define PHC(x) ((x) << 0)
202 # define PHC_MASK (0x1f << 0)
203 # define PHC_SHIFT 0
205 # define SDC_MASK (0x3ff << 9)
208 # define SU_MASK (0xf << 23)
211 # define DIV_ID_MASK (0x7 << 28)
214 #define CG_FTV 0x690
215 #define CG_FFCT_0 0x694
216 # define UTC_0(x) ((x) << 0)
217 # define UTC_0_MASK (0x3ff << 0)
218 # define UTC_0_SHIFT 0
220 # define DTC_0_MASK (0x3ff << 10)
223 #define CG_GIT 0x6d8
224 # define CG_GICST(x) ((x) << 0)
225 # define CG_GICST_MASK (0xffff << 0)
226 # define CG_GICST_SHIFT 0
228 # define CG_GIPOT_MASK (0xffff << 16)
231 #define CG_SCLK_DPM_CTRL_3 0x6e0
232 # define FORCE_SCLK_STATE(x) ((x) << 0)
233 # define FORCE_SCLK_STATE_MASK (0x7 << 0)
234 # define FORCE_SCLK_STATE_SHIFT 0
237 # define GNB_TT_MASK (0xff << 8)
246 #define CG_SSP 0x6e8
247 # define SST(x) ((x) << 0)
248 # define SST_MASK (0xffff << 0)
249 # define SST_SHIFT 0
251 # define SSTU_MASK (0xffff << 16)
254 #define CG_ACPI_CNTL 0x70c
255 # define SCLK_ACPI_DIV(x) ((x) << 0)
256 # define SCLK_ACPI_DIV_MASK (0x7f << 0)
257 # define SCLK_ACPI_DIV_SHIFT 0
259 #define CG_SCLK_DPM_CTRL_4 0x71c
261 # define DC_HDC_MASK (0x3fff << 14)
264 # define DC_HU_MASK (0xf << 28)
266 #define CG_SCLK_DPM_CTRL_5 0x720
267 # define SCLK_FSTATE_BOOTUP(x) ((x) << 0)
268 # define SCLK_FSTATE_BOOTUP_MASK (0x7 << 0)
269 # define SCLK_FSTATE_BOOTUP_SHIFT 0
271 # define TT_TP_MASK (0xffff << 3)
274 # define TT_TU_MASK (0xff << 19)
276 #define CG_SCLK_DPM_CTRL_6 0x724
277 #define CG_AT_0 0x728
278 # define CG_R(x) ((x) << 0)
279 # define CG_R_MASK (0xffff << 0)
280 # define CG_R_SHIFT 0
282 # define CG_L_MASK (0xffff << 16)
284 #define CG_AT_1 0x72c
285 #define CG_AT_2 0x730
286 #define CG_THERMAL_INT 0x734
288 #define DIG_THERM_INTH_MASK 0x0000FF00
291 #define DIG_THERM_INTL_MASK 0x00FF0000
295 #define CG_AT_3 0x738
296 #define CG_AT_4 0x73c
297 #define CG_AT_5 0x740
298 #define CG_AT_6 0x744
299 #define CG_AT_7 0x748
301 #define CG_BSP_0 0x750
302 # define BSP(x) ((x) << 0)
303 # define BSP_MASK (0xffff << 0)
304 # define BSP_SHIFT 0
306 # define BSU_MASK (0xf << 16)
309 #define CG_CG_VOLTAGE_CNTL 0x770
310 # define REQ (1 << 0)
312 # define LEVEL_MASK (0x3 << 1)
317 # define PERIOD_MASK (0xffff << 8)
320 # define UNIT_MASK (0xf << 24)
323 #define CG_ACPI_VOLTAGE_CNTL 0x780
326 #define CG_DPM_VOLTAGE_CNTL 0x788
327 # define DPM_STATE0_LEVEL_MASK (0x3 << 0)
328 # define DPM_STATE0_LEVEL_SHIFT 0
331 #define CG_PWR_GATING_CNTL 0x7ac
332 # define DYN_PWR_DOWN_EN (1 << 0)
338 # define PGP_MASK (0xffff << 8)
341 # define PGU_MASK (0xf << 24)
344 #define CG_CGTT_LOCAL_0 0x7d0
345 #define CG_CGTT_LOCAL_1 0x7d4
347 #define DEEP_SLEEP_CNTL 0x818
350 # define HS_MASK (0xfff << 4)
353 #define DEEP_SLEEP_CNTL2 0x81c
354 # define LB_UFP_EN (1 << 0)
356 # define INOUT_C_MASK (0xff << 4)
359 #define CG_SCRATCH2 0x824
361 #define CG_SCLK_DPM_CTRL_11 0x830
363 #define HW_REV 0x5564
364 # define ATI_REV_ID_MASK (0xf << 28)
366 /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
368 #define DOUT_SCRATCH3 0x611c
370 #define GB_ADDR_CONFIG 0x98f8