Lines Matching defs:SMU7_Fusion_DpmTable
209 struct SMU7_Fusion_DpmTable { struct
210 uint32_t SystemFlags;
212 SMU7_PIDController GraphicsPIDController;
213 SMU7_PIDController GioPIDController;
215 uint8_t GraphicsDpmLevelCount;
216 uint8_t GIOLevelCount;
217 uint8_t UvdLevelCount;
218 uint8_t VceLevelCount;
220 uint8_t AcpLevelCount;
221 uint8_t SamuLevelCount;
222 uint16_t FpsHighT;
224 SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];
225 SMU7_Fusion_ACPILevel ACPILevel;
226 SMU7_Fusion_UvdLevel UvdLevel[SMU7_MAX_LEVELS_UVD];
227 SMU7_Fusion_ExtClkLevel VceLevel[SMU7_MAX_LEVELS_VCE];
228 SMU7_Fusion_ExtClkLevel AcpLevel[SMU7_MAX_LEVELS_ACP];
229 SMU7_Fusion_ExtClkLevel SamuLevel[SMU7_MAX_LEVELS_SAMU];
231 uint8_t UvdBootLevel;
232 uint8_t VceBootLevel;
233 uint8_t AcpBootLevel;
234 uint8_t SamuBootLevel;
235 uint8_t UVDInterval;
236 uint8_t VCEInterval;
237 uint8_t ACPInterval;
238 uint8_t SAMUInterval;
240 uint8_t GraphicsBootLevel;
241 uint8_t GraphicsInterval;
242 uint8_t GraphicsThermThrottleEnable;
243 uint8_t GraphicsVoltageChangeEnable;
245 uint8_t GraphicsClkSlowEnable;
246 uint8_t GraphicsClkSlowDivider;
247 uint16_t FpsLowT;
249 uint32_t DisplayCac;
250 uint32_t LowSclkInterruptT;
252 uint32_t DRAM_LOG_ADDR_H;
253 uint32_t DRAM_LOG_ADDR_L;
254 uint32_t DRAM_LOG_PHY_ADDR_H;
255 uint32_t DRAM_LOG_PHY_ADDR_L;
256 uint32_t DRAM_LOG_BUFF_SIZE;
284 typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; typedef