Lines Matching +full:1 +full:x
56 # define AUTO_INCREMENT_IND_0 (1 << 0)
69 # define RST_REG (1 << 0)
71 # define CK_DISABLE (1 << 0)
72 # define CKEN (1 << 24)
75 #define VGA_MEMORY_DISABLE (1 << 4)
78 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
81 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
86 #define SPLL_RESET (1 << 0)
87 #define SPLL_SLEEP (1 << 1)
88 #define SPLL_BYPASS_EN (1 << 3)
89 #define SPLL_REF_DIV(x) ((x) << 4) argument
91 #define SPLL_PDIV_A(x) ((x) << 20) argument
95 #define SCLK_MUX_SEL(x) ((x) << 0) argument
97 #define SPLL_CTLREQ_CHG (1 << 23)
98 #define SCLK_MUX_UPDATE (1 << 26)
100 #define SPLL_FB_DIV(x) ((x) << 0) argument
103 #define SPLL_DITHEN (1 << 28)
107 #define SPLL_CHG_STATUS (1 << 1)
109 #define SPLL_SW_DIR_CONTROL (1 << 0)
110 # define SPLL_REFCLK_SEL(x) ((x) << 26) argument
114 #define SSEN (1 << 0)
115 #define CLK_S(x) ((x) << 4) argument
119 #define CLK_V(x) ((x) << 0) argument
124 # define AUTOSCALE_ON_SS_CLEAR (1 << 9)
137 # define UPLL_PDIV_A(x) ((x) << 0) argument
139 # define UPLL_PDIV_B(x) ((x) << 8) argument
141 # define VCLK_SRC_SEL(x) ((x) << 20) argument
143 # define DCLK_SRC_SEL(x) ((x) << 25) argument
146 # define UPLL_FB_DIV(x) ((x) << 0) argument
156 # define MPLL_CLKOUT_SEL(x) ((x) << 8) argument
160 # define XTALIN_DIVIDE (1 << 1)
161 # define BCLK_AS_XCLK (1 << 2)
163 # define FORCE_BIF_REFCLK_EN (1 << 3)
164 # define MUX_TCLK_TO_XCLK (1 << 8)
167 # define CMON_CLK_SEL(x) ((x) << 0) argument
169 # define TMON_CLK_SEL(x) ((x) << 8) argument
172 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) argument
174 # define ZCLK_SEL(x) ((x) << 8) argument
178 #define DPM_EVENT_SRC(x) ((x) << 0) argument
180 #define DIG_THERM_DPM(x) ((x) << 14) argument
184 #define FDO_PWM_DUTY(x) ((x) << 9) argument
188 #define DIG_THERM_INTH(x) ((x) << 8) argument
191 #define DIG_THERM_INTL(x) ((x) << 16) argument
194 #define THERM_INT_MASK_HIGH (1 << 24)
195 #define THERM_INT_MASK_LOW (1 << 25)
198 #define TEMP_SEL(x) ((x) << 20) argument
202 #define ASIC_MAX_TEMP(x) ((x) << 0) argument
205 #define CTF_TEMP(x) ((x) << 9) argument
210 #define FDO_STATIC_DUTY(x) ((x) << 0) argument
214 #define FMAX_DUTY100(x) ((x) << 0) argument
218 #define TMIN(x) ((x) << 0) argument
221 #define FDO_PWM_MODE(x) ((x) << 11) argument
224 #define TACH_PWM_RESP_RATE(x) ((x) << 25) argument
229 # define EDGE_PER_REV(x) ((x) << 0) argument
232 # define TARGET_PERIOD(x) ((x) << 3) argument
236 # define TACH_PERIOD(x) ((x) << 0) argument
241 # define GLOBAL_PWRMGT_EN (1 << 0)
242 # define STATIC_PM_EN (1 << 1)
243 # define THERMAL_PROTECTION_DIS (1 << 2)
244 # define THERMAL_PROTECTION_TYPE (1 << 3)
245 # define SW_SMIO_INDEX(x) ((x) << 6) argument
246 # define SW_SMIO_INDEX_MASK (1 << 6)
248 # define VOLT_PWRMGT_EN (1 << 10)
249 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
252 # define SCLK_PWRMGT_OFF (1 << 0)
253 # define SCLK_LOW_D1 (1 << 1)
254 # define FIR_RESET (1 << 4)
255 # define FIR_FORCE_TREND_SEL (1 << 5)
256 # define FIR_TREND_MODE (1 << 6)
257 # define DYN_GFX_CLK_OFF_EN (1 << 7)
258 # define GFX_CLK_FORCE_ON (1 << 8)
259 # define GFX_CLK_REQUEST_OFF (1 << 9)
260 # define GFX_CLK_FORCE_OFF (1 << 10)
261 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
262 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
263 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
264 # define DYN_LIGHT_SLEEP_EN (1 << 14)
273 # define UTC_0(x) ((x) << 0) argument
275 # define DTC_0(x) ((x) << 10) argument
279 # define BSP(x) ((x) << 0) argument
281 # define BSU(x) ((x) << 16) argument
284 # define CG_R(x) ((x) << 0) argument
286 # define CG_L(x) ((x) << 16) argument
290 # define CG_GICST(x) ((x) << 0) argument
292 # define CG_GIPOT(x) ((x) << 16) argument
296 # define SST(x) ((x) << 0) argument
298 # define SSTU(x) ((x) << 16) argument
302 # define DISP1_GAP(x) ((x) << 0) argument
304 # define DISP2_GAP(x) ((x) << 2) argument
306 # define VBI_TIMER_COUNT(x) ((x) << 4) argument
308 # define VBI_TIMER_UNIT(x) ((x) << 20) argument
310 # define DISP1_GAP_MCHG(x) ((x) << 24) argument
312 # define DISP2_GAP_MCHG(x) ((x) << 26) argument
321 # define CAC_WINDOW(x) ((x) << 0) argument
329 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) argument
330 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
333 #define GRBM_RQ_PENDING (1 << 5)
334 #define VMC_BUSY (1 << 8)
335 #define MCB_BUSY (1 << 9)
336 #define MCB_NON_DISPLAY_BUSY (1 << 10)
337 #define MCC_BUSY (1 << 11)
338 #define MCD_BUSY (1 << 12)
339 #define SEM_BUSY (1 << 14)
340 #define IH_BUSY (1 << 17)
343 #define SOFT_RESET_BIF (1 << 1)
344 #define SOFT_RESET_DC (1 << 5)
345 #define SOFT_RESET_DMA1 (1 << 6)
346 #define SOFT_RESET_GRBM (1 << 8)
347 #define SOFT_RESET_HDP (1 << 9)
348 #define SOFT_RESET_IH (1 << 10)
349 #define SOFT_RESET_MC (1 << 11)
350 #define SOFT_RESET_ROM (1 << 14)
351 #define SOFT_RESET_SEM (1 << 15)
352 #define SOFT_RESET_VMC (1 << 17)
353 #define SOFT_RESET_DMA (1 << 20)
354 #define SOFT_RESET_TST (1 << 21)
355 #define SOFT_RESET_REGBB (1 << 22)
356 #define SOFT_RESET_ORB (1 << 23)
366 #define DMA_BUSY (1 << 5)
367 #define DMA1_BUSY (1 << 6)
370 #define ENABLE_L2_CACHE (1 << 0)
371 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
372 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) argument
373 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) argument
374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
375 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
376 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) argument
377 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) argument
379 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
380 #define INVALIDATE_L2_CACHE (1 << 1)
381 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) argument
383 #define INVALIDATE_ONLY_PTE_CACHES 1
386 #define BANK_SELECT(x) ((x) << 0) argument
387 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) argument
388 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
389 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
391 #define L2_BUSY (1 << 0)
393 #define ENABLE_CONTEXT (1 << 0)
394 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
395 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
396 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
397 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
398 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
399 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
400 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
401 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
402 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
403 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
404 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
405 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
406 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
407 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
425 * bit 1: pde0
432 #define MEMORY_CLIENT_RW_MASK (1 << 24)
458 #define MC_CG_ENABLE (1 << 18)
459 #define MC_LS_ENABLE (1 << 19)
475 #define ENABLE_L1_TLB (1 << 0)
476 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
478 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
482 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
508 #define CHANSIZE_OVERRIDE (1 << 11)
516 #define STATE0(x) ((x) << 0) argument
519 #define STATE1(x) ((x) << 5) argument
522 #define STATE2(x) ((x) << 10) argument
525 #define STATE3(x) ((x) << 15) argument
530 #define TRAIN_DONE_D0 (1 << 30)
531 #define TRAIN_DONE_D1 (1 << 31)
534 #define RUN_MASK (1 << 0)
539 #define MEM_FALL_OUT_CMD (1 << 8)
557 #define MC_SEQ_MISC0_REV_ID_VALUE 1
597 # define DLL_SPEED(x) ((x) << 0) argument
599 # define DLL_READY (1 << 6)
600 # define MC_INT_CNTL (1 << 7)
601 # define MRDCK0_PDNB (1 << 8)
602 # define MRDCK1_PDNB (1 << 9)
603 # define MRDCK0_RESET (1 << 16)
604 # define MRDCK1_RESET (1 << 17)
605 # define DLL_READY_READ (1 << 24)
607 # define MRDCK0_BYPASS (1 << 24)
608 # define MRDCK1_BYPASS (1 << 25)
611 # define MPLL_MCLK_SEL (1 << 11)
613 #define BWCTRL(x) ((x) << 20) argument
616 #define VCO_MODE(x) ((x) << 0) argument
618 #define CLKFRAC(x) ((x) << 4) argument
620 #define CLKF(x) ((x) << 16) argument
624 #define YCLK_POST_DIV(x) ((x) << 0) argument
627 #define YCLK_SEL(x) ((x) << 4) argument
628 #define YCLK_SEL_MASK (1 << 4)
631 #define CLKV(x) ((x) << 0) argument
634 #define CLKS(x) ((x) << 0) argument
638 #define CLOCK_GATING_DIS (1 << 23)
645 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
647 #define HDP_LS_ENABLE (1 << 0)
652 # define IH_RB_ENABLE (1 << 0)
653 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ argument
654 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
655 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
656 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ argument
657 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
658 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
662 # define RB_OVERFLOW (1 << 0)
667 # define ENABLE_INTR (1 << 0)
668 # define IH_MC_SWAP(x) ((x) << 1) argument
670 # define IH_MC_SWAP_16BIT 1
673 # define RPTR_REARM (1 << 4)
674 # define MC_WRREQ_CREDIT(x) ((x) << 15) argument
675 # define MC_WR_CLEAN_CNT(x) ((x) << 20) argument
676 # define MC_VMID(x) ((x) << 25) argument
681 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
682 # define IH_DUMMY_RD_EN (1 << 1)
683 # define IH_REQ_NONSNOOP_EN (1 << 3)
684 # define GEN_IH_INT_EN (1 << 8)
690 #define FB_READ_EN (1 << 0)
691 #define FB_WRITE_EN (1 << 1)
697 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) argument
698 # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
702 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) argument
705 #define HDMI_CONNECTION (1 << 16)
706 #define DP_CONNECTION (1 << 17)
722 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) argument
724 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) argument
725 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) argument
726 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ argument
738 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) argument
739 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) argument
742 * x = legal delay value
746 # define HBR_CAPABLE (1 << 0) /* enabled by default */
749 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) argument
750 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) argument
752 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) argument
754 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) argument
756 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) argument
758 # define DESCRIPTION0(x) (((x) & 0xff) << 0) argument
759 # define DESCRIPTION1(x) (((x) & 0xff) << 8) argument
760 # define DESCRIPTION2(x) (((x) & 0xff) << 16) argument
761 # define DESCRIPTION3(x) (((x) & 0xff) << 24) argument
763 # define DESCRIPTION4(x) (((x) & 0xff) << 0) argument
764 # define DESCRIPTION5(x) (((x) & 0xff) << 8) argument
765 # define DESCRIPTION6(x) (((x) & 0xff) << 16) argument
766 # define DESCRIPTION7(x) (((x) & 0xff) << 24) argument
768 # define DESCRIPTION8(x) (((x) & 0xff) << 0) argument
769 # define DESCRIPTION9(x) (((x) & 0xff) << 8) argument
770 # define DESCRIPTION10(x) (((x) & 0xff) << 16) argument
771 # define DESCRIPTION11(x) (((x) & 0xff) << 24) argument
773 # define DESCRIPTION12(x) (((x) & 0xff) << 0) argument
774 # define DESCRIPTION13(x) (((x) & 0xff) << 8) argument
775 # define DESCRIPTION14(x) (((x) & 0xff) << 16) argument
776 # define DESCRIPTION15(x) (((x) & 0xff) << 24) argument
778 # define DESCRIPTION16(x) (((x) & 0xff) << 0) argument
779 # define DESCRIPTION17(x) (((x) & 0xff) << 8) argument
782 # define AUDIO_ENABLED (1 << 31)
789 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) argument
793 #define PRIORITY_OFF (1 << 16)
794 #define PRIORITY_ALWAYS_ON (1 << 20)
798 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) argument
800 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) argument
801 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) argument
805 # define VLINE_OCCURRED (1 << 0)
806 # define VLINE_ACK (1 << 4)
807 # define VLINE_STAT (1 << 12)
808 # define VLINE_INTERRUPT (1 << 16)
809 # define VLINE_INTERRUPT_TYPE (1 << 17)
812 # define VBLANK_OCCURRED (1 << 0)
813 # define VBLANK_ACK (1 << 4)
814 # define VBLANK_STAT (1 << 12)
815 # define VBLANK_INTERRUPT (1 << 16)
816 # define VBLANK_INTERRUPT_TYPE (1 << 17)
820 # define VBLANK_INT_MASK (1 << 0)
821 # define VLINE_INT_MASK (1 << 4)
824 # define LB_D1_VLINE_INTERRUPT (1 << 2)
825 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
826 # define DC_HPD1_INTERRUPT (1 << 17)
827 # define DC_HPD1_RX_INTERRUPT (1 << 18)
828 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
829 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
830 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
831 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
833 # define LB_D2_VLINE_INTERRUPT (1 << 2)
834 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
835 # define DC_HPD2_INTERRUPT (1 << 17)
836 # define DC_HPD2_RX_INTERRUPT (1 << 18)
837 # define DISP_TIMER_INTERRUPT (1 << 24)
839 # define LB_D3_VLINE_INTERRUPT (1 << 2)
840 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
841 # define DC_HPD3_INTERRUPT (1 << 17)
842 # define DC_HPD3_RX_INTERRUPT (1 << 18)
844 # define LB_D4_VLINE_INTERRUPT (1 << 2)
845 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
846 # define DC_HPD4_INTERRUPT (1 << 17)
847 # define DC_HPD4_RX_INTERRUPT (1 << 18)
849 # define LB_D5_VLINE_INTERRUPT (1 << 2)
850 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
851 # define DC_HPD5_INTERRUPT (1 << 17)
852 # define DC_HPD5_RX_INTERRUPT (1 << 18)
854 # define LB_D6_VLINE_INTERRUPT (1 << 2)
855 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
856 # define DC_HPD6_INTERRUPT (1 << 17)
857 # define DC_HPD6_RX_INTERRUPT (1 << 18)
861 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
862 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
865 # define GRPH_PFLIP_INT_MASK (1 << 0)
866 # define GRPH_PFLIP_INT_TYPE (1 << 8)
876 # define DC_HPDx_INT_STATUS (1 << 0)
877 # define DC_HPDx_SENSE (1 << 1)
878 # define DC_HPDx_RX_INT_STATUS (1 << 8)
886 # define DC_HPDx_INT_ACK (1 << 0)
887 # define DC_HPDx_INT_POLARITY (1 << 8)
888 # define DC_HPDx_INT_EN (1 << 16)
889 # define DC_HPDx_RX_INT_ACK (1 << 20)
890 # define DC_HPDx_RX_INT_EN (1 << 24)
898 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) argument
899 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) argument
900 # define DC_HPDx_EN (1 << 28)
903 # define STUTTER_ENABLE (1 << 0)
910 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ argument
911 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
919 # define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24) argument
924 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) argument
927 * 1 = stream1
935 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
938 #define RLC_RQ_PENDING (1 << 0)
939 #define RLC_BUSY (1 << 8)
940 #define TC_BUSY (1 << 9)
944 #define RING2_RQ_PENDING (1 << 4)
945 #define SRBM_RQ_PENDING (1 << 5)
946 #define RING1_RQ_PENDING (1 << 6)
947 #define CF_RQ_PENDING (1 << 7)
948 #define PF_RQ_PENDING (1 << 8)
949 #define GDS_DMA_RQ_PENDING (1 << 9)
950 #define GRBM_EE_BUSY (1 << 10)
951 #define DB_CLEAN (1 << 12)
952 #define CB_CLEAN (1 << 13)
953 #define TA_BUSY (1 << 14)
954 #define GDS_BUSY (1 << 15)
955 #define VGT_BUSY (1 << 17)
956 #define IA_BUSY_NO_DMA (1 << 18)
957 #define IA_BUSY (1 << 19)
958 #define SX_BUSY (1 << 20)
959 #define SPI_BUSY (1 << 22)
960 #define BCI_BUSY (1 << 23)
961 #define SC_BUSY (1 << 24)
962 #define PA_BUSY (1 << 25)
963 #define DB_BUSY (1 << 26)
964 #define CP_COHERENCY_BUSY (1 << 28)
965 #define CP_BUSY (1 << 29)
966 #define CB_BUSY (1 << 30)
967 #define GUI_ACTIVE (1 << 31)
970 #define SE_DB_CLEAN (1 << 1)
971 #define SE_CB_CLEAN (1 << 2)
972 #define SE_BCI_BUSY (1 << 22)
973 #define SE_VGT_BUSY (1 << 23)
974 #define SE_PA_BUSY (1 << 24)
975 #define SE_TA_BUSY (1 << 25)
976 #define SE_SX_BUSY (1 << 26)
977 #define SE_SPI_BUSY (1 << 27)
978 #define SE_SC_BUSY (1 << 29)
979 #define SE_DB_BUSY (1 << 30)
980 #define SE_CB_BUSY (1 << 31)
983 #define SOFT_RESET_CP (1 << 0)
984 #define SOFT_RESET_CB (1 << 1)
985 #define SOFT_RESET_RLC (1 << 2)
986 #define SOFT_RESET_DB (1 << 3)
987 #define SOFT_RESET_GDS (1 << 4)
988 #define SOFT_RESET_PA (1 << 5)
989 #define SOFT_RESET_SC (1 << 6)
990 #define SOFT_RESET_BCI (1 << 7)
991 #define SOFT_RESET_SPI (1 << 8)
992 #define SOFT_RESET_SX (1 << 10)
993 #define SOFT_RESET_TC (1 << 11)
994 #define SOFT_RESET_TA (1 << 12)
995 #define SOFT_RESET_VGT (1 << 14)
996 #define SOFT_RESET_IA (1 << 15)
999 #define INSTANCE_INDEX(x) ((x) << 0) argument
1000 #define SH_INDEX(x) ((x) << 8) argument
1001 #define SE_INDEX(x) ((x) << 16) argument
1002 #define SH_BROADCAST_WRITES (1 << 29)
1003 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1004 #define SE_BROADCAST_WRITES (1 << 31)
1007 # define RDERR_INT_ENABLE (1 << 0)
1008 # define GUI_IDLE_INT_ENABLE (1 << 19)
1028 #define CP_CE_HALT (1 << 24)
1029 #define CP_PFP_HALT (1 << 26)
1030 #define CP_ME_HALT (1 << 28)
1040 #define ROQ_IB1_START(x) ((x) << 0) argument
1041 #define ROQ_IB2_START(x) ((x) << 8) argument
1043 #define MEQ1_START(x) ((x) << 0) argument
1044 #define MEQ2_START(x) ((x) << 8) argument
1051 #define CACHE_INVALIDATION(x) ((x) << 0) argument
1053 #define TC_ONLY 1
1055 #define AUTO_INVLD_EN(x) ((x) << 6) argument
1057 #define ES_AUTO 1
1083 #define CLIP_VTX_REORDER_ENA (1 << 0)
1084 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
1091 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
1092 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
1095 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) argument
1096 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) argument
1097 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) argument
1098 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) argument
1107 #define MIN_POWER(x) ((x) << 0) argument
1110 #define MAX_POWER(x) ((x) << 16) argument
1114 #define MAX_POWER_DELTA(x) ((x) << 0) argument
1117 #define STI_SIZE(x) ((x) << 16) argument
1120 #define LTI_RATIO(x) ((x) << 27) argument
1134 #define VTX_DONE_DELAY(x) ((x) << 0) argument
1135 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1142 #define OVERRIDE (1 << 21)
1143 #define LS_OVERRIDE (1 << 22)
1151 #define BACKEND_DISABLE(x) ((x) << 16) argument
1153 #define NUM_PIPES(x) ((x) << 0) argument
1156 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
1159 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
1162 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
1165 #define NUM_GPUS(x) ((x) << 20) argument
1168 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
1171 #define ROW_SIZE(x) ((x) << 28) argument
1176 # define MICRO_TILE_MODE(x) ((x) << 0) argument
1178 # define ADDR_SURF_THIN_MICRO_TILING 1
1180 # define ARRAY_MODE(x) ((x) << 2) argument
1182 # define ARRAY_LINEAR_ALIGNED 1
1185 # define PIPE_CONFIG(x) ((x) << 6) argument
1198 # define TILE_SPLIT(x) ((x) << 11) argument
1200 # define ADDR_SURF_TILE_SPLIT_128B 1
1206 # define BANK_WIDTH(x) ((x) << 14) argument
1208 # define ADDR_SURF_BANK_WIDTH_2 1
1211 # define BANK_HEIGHT(x) ((x) << 16) argument
1213 # define ADDR_SURF_BANK_HEIGHT_2 1
1216 # define MACRO_TILE_ASPECT(x) ((x) << 18) argument
1218 # define ADDR_SURF_MACRO_ASPECT_2 1
1221 # define NUM_BANKS(x) ((x) << 20) argument
1223 # define ADDR_SURF_4_BANK 1
1247 #define RB_BUFSZ(x) ((x) << 0) argument
1248 #define RB_BLKSZ(x) ((x) << 8) argument
1250 #define RB_NO_UPDATE (1 << 27)
1251 #define RB_RPTR_WR_ENA (1 << 31)
1279 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1280 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1281 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1282 # define TIME_STAMP_INT_ENABLE (1 << 26)
1283 # define CP_RINGID2_INT_ENABLE (1 << 29)
1284 # define CP_RINGID1_INT_ENABLE (1 << 30)
1285 # define CP_RINGID0_INT_ENABLE (1 << 31)
1289 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
1290 # define TIME_STAMP_INT_STAT (1 << 26)
1291 # define CP_RINGID2_INT_STAT (1 << 29)
1292 # define CP_RINGID1_INT_STAT (1 << 30)
1293 # define CP_RINGID0_INT_STAT (1 << 31)
1296 # define CP_MEM_LS_EN (1 << 0)
1301 # define RLC_ENABLE (1 << 0)
1305 # define LOAD_BALANCE_ENABLE (1 << 0)
1321 # define RLC_BUSY_STATUS (1 << 0)
1322 # define GFX_POWER_STATUS (1 << 1)
1323 # define GFX_CLOCK_STATUS (1 << 2)
1324 # define GFX_LS_STATUS (1 << 3)
1327 # define GFX_PG_ENABLE (1 << 0)
1328 # define GFX_PG_SRC (1 << 1)
1332 # define CGCG_EN (1 << 0)
1333 # define CGLS_EN (1 << 1)
1336 # define RLC_PUD(x) ((x) << 0) argument
1338 # define RLC_PDD(x) ((x) << 8) argument
1340 # define RLC_TTPD(x) ((x) << 16) argument
1342 # define RLC_MSD(x) ((x) << 24) argument
1349 # define MAX_PU_CU(x) ((x) << 0) argument
1352 # define AUTO_PG_EN (1 << 0)
1353 # define GRBM_REG_SGIT(x) ((x) << 3) argument
1355 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) argument
1373 # define RASTER_CONFIG_RB_MAP_1 1
1378 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1418 # define LS2_EXIT_TIME(x) ((x) << 17) argument
1422 # define MULTI_PIF (1 << 25)
1424 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) argument
1427 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) argument
1430 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) argument
1434 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) argument
1437 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) argument
1440 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) argument
1445 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) argument
1448 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) argument
1451 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) argument
1455 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) argument
1458 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) argument
1461 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) argument
1474 # define SLV_MEM_LS_EN (1 << 16)
1475 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1476 # define MST_MEM_LS_EN (1 << 18)
1477 # define REPLAY_MEM_LS_EN (1 << 19)
1479 # define LC_REVERSE_RCVR (1 << 0)
1480 # define LC_REVERSE_XMIT (1 << 1)
1487 # define P_IGNORE_EDB_ERR (1 << 6)
1491 # define LC_L0S_INACTIVITY(x) ((x) << 8) argument
1494 # define LC_L1_INACTIVITY(x) ((x) << 12) argument
1497 # define LC_PMI_TO_L1_DIS (1 << 16)
1498 # define LC_ASPM_TO_L1_DIS (1 << 24)
1503 # define LC_LINK_WIDTH_X1 1
1510 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1511 # define LC_RECONFIG_NOW (1 << 8)
1512 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1513 # define LC_RENEGOTIATE_EN (1 << 10)
1514 # define LC_SHORT_RECONFIG_EN (1 << 11)
1515 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1516 # define LC_UPCONFIGURE_DIS (1 << 13)
1517 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) argument
1521 # define LC_XMIT_N_FTS(x) ((x) << 0) argument
1524 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1527 # define LC_GEN2_EN_STRAP (1 << 0)
1528 # define LC_GEN3_EN_STRAP (1 << 1)
1529 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1532 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1533 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1534 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1535 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1536 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1539 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1541 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1542 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1543 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1544 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1545 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1548 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1549 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1552 # define LC_GO_TO_RECOVERY (1 << 30)
1554 # define LC_REDO_EQ (1 << 5)
1555 # define LC_SET_QUIESCE (1 << 13)
1569 # define DCM (1 << 0)
1570 # define CG_DT(x) ((x) << 2) argument
1572 # define CLK_OD(x) ((x) << 6) argument
1578 # define DYN_OR_EN (1 << 0)
1579 # define DYN_RR_EN (1 << 1)
1580 # define G_DIV_ID(x) ((x) << 2) argument
1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1604 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
1639 * 1 - memory (sync - via GRBM)
1645 #define WR_ONE_ADDR (1 << 16)
1646 #define WR_CONFIRM (1 << 20)
1647 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
1649 * 1 - pfp
1657 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1659 * 1 - <
1666 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1668 * 1 - mem
1670 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1672 * 1 - pfp
1677 /* 1. header
1685 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) argument
1687 * 1 - GDS
1689 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) argument
1691 * 1 - PFP
1693 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) argument
1695 * 1 - GDS
1698 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1700 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1701 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) argument
1703 * 1 - 8 in 16
1707 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) argument
1709 * 1 - 8 in 16
1713 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1715 * 1 - register
1717 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1719 * 1 - register
1721 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1722 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1723 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1726 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1727 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1728 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1729 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1730 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1731 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1732 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1733 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1734 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1735 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1736 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1737 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1738 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1739 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1740 # define PACKET3_TC_ACTION_ENA (1 << 23)
1741 # define PACKET3_CB_ACTION_ENA (1 << 25)
1742 # define PACKET3_DB_ACTION_ENA (1 << 26)
1743 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1744 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1746 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) argument
1749 #define EVENT_TYPE(x) ((x) << 0) argument
1750 #define EVENT_INDEX(x) ((x) << 8) argument
1752 * 1 - ZPASS_DONE
1760 #define INV_L2 (1 << 20)
1763 #define DATA_SEL(x) ((x) << 29) argument
1765 * 1 - send low 32bit data
1769 #define INT_SEL(x) ((x) << 24) argument
1771 * 1 - interrupt only (DATA_SEL = 0)
1816 # define DMA_RB_ENABLE (1 << 0)
1817 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1818 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1819 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1820 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1821 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1830 # define DMA_IB_ENABLE (1 << 0)
1831 # define DMA_IB_SWAP_ENABLE (1 << 4)
1834 # define TRAP_ENABLE (1 << 0)
1835 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1836 # define SEM_WAIT_INT_ENABLE (1 << 2)
1837 # define DATA_SWAP_ENABLE (1 << 3)
1838 # define FENCE_SWAP_ENABLE (1 << 4)
1839 # define CTXEMPTY_INT_ENABLE (1 << 28)
1841 # define DMA_IDLE (1 << 0)
1845 # define MEM_POWER_OVERRIDE (1 << 8)
1849 # define PG_CNTL_ENABLE (1 << 0)
1864 (1 << 26) | \
1865 (1 << 21) | \
1882 #define VCE_CLK_EN (1 << 0)
1891 #define VCE_ECPU_SOFT_RESET (1 << 0)
1892 #define VCE_FME_SOFT_RESET (1 << 2)
1904 # define CGC_DYN_CLOCK_MODE (1 << 16)
1909 # define VCE_FW_REG_STATUS_BUSY (1 << 0)
1910 # define VCE_FW_REG_STATUS_PASS (1 << 3)
1911 # define VCE_FW_REG_STATUS_DONE (1 << 11)
1940 # define VCEPLL_PDIV_A(x) ((x) << 0) argument
1942 # define VCEPLL_PDIV_B(x) ((x) << 8) argument
1944 # define EVCLK_SRC_SEL(x) ((x) << 20) argument
1946 # define ECCLK_SRC_SEL(x) ((x) << 25) argument
1949 # define VCEPLL_FB_DIV(x) ((x) << 0) argument