Lines Matching +full:0 +full:xc304
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
39 #define SI_MAX_BACKENDS_MASK 0xFF
40 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
42 #define SI_MAX_SIMDS_MASK 0x0FFF
43 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
45 #define SI_MAX_PIPES_MASK 0xFF
46 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47 #define SI_MAX_LDS_NUM 0xFFFF
49 #define SI_MAX_TCC_MASK 0xFFFF
52 #define SMC_IND_INDEX_0 0x200
53 #define SMC_IND_DATA_0 0x204
55 #define SMC_IND_ACCESS_CNTL 0x228
56 # define AUTO_INCREMENT_IND_0 (1 << 0)
57 #define SMC_MESSAGE_0 0x22c
58 #define SMC_RESP_0 0x230
61 #define SMC_CG_IND_START 0xc0030000
62 #define SMC_CG_IND_END 0xc0040000
64 #define CG_CGTT_LOCAL_0 0x400
65 #define CG_CGTT_LOCAL_1 0x401
68 #define SMC_SYSCON_RESET_CNTL 0x80000000
69 # define RST_REG (1 << 0)
70 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
71 # define CK_DISABLE (1 << 0)
74 #define VGA_HDP_CONTROL 0x328
77 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc
78 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
79 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
80 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0
85 #define CG_SPLL_FUNC_CNTL 0x600
86 #define SPLL_RESET (1 << 0)
90 #define SPLL_REF_DIV_MASK (0x3f << 4)
92 #define SPLL_PDIV_A_MASK (0x7f << 20)
94 #define CG_SPLL_FUNC_CNTL_2 0x604
95 #define SCLK_MUX_SEL(x) ((x) << 0)
96 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
99 #define CG_SPLL_FUNC_CNTL_3 0x608
100 #define SPLL_FB_DIV(x) ((x) << 0)
101 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
102 #define SPLL_FB_DIV_SHIFT 0
104 #define CG_SPLL_FUNC_CNTL_4 0x60c
106 #define SPLL_STATUS 0x614
108 #define SPLL_CNTL_MODE 0x618
109 #define SPLL_SW_DIR_CONTROL (1 << 0)
113 #define CG_SPLL_SPREAD_SPECTRUM 0x620
114 #define SSEN (1 << 0)
116 #define CLK_S_MASK (0xfff << 4)
118 #define CG_SPLL_SPREAD_SPECTRUM_2 0x624
119 #define CLK_V(x) ((x) << 0)
120 #define CLK_V_MASK (0x3ffffff << 0)
121 #define CLK_V_SHIFT 0
123 #define CG_SPLL_AUTOSCALE_CNTL 0x62c
127 #define CG_UPLL_FUNC_CNTL 0x634
128 # define UPLL_RESET_MASK 0x00000001
129 # define UPLL_SLEEP_MASK 0x00000002
130 # define UPLL_BYPASS_EN_MASK 0x00000004
131 # define UPLL_CTLREQ_MASK 0x00000008
132 # define UPLL_VCO_MODE_MASK 0x00000600
133 # define UPLL_REF_DIV_MASK 0x003F0000
134 # define UPLL_CTLACK_MASK 0x40000000
135 # define UPLL_CTLACK2_MASK 0x80000000
136 #define CG_UPLL_FUNC_CNTL_2 0x638
137 # define UPLL_PDIV_A(x) ((x) << 0)
138 # define UPLL_PDIV_A_MASK 0x0000007F
140 # define UPLL_PDIV_B_MASK 0x00007F00
142 # define VCLK_SRC_SEL_MASK 0x01F00000
144 # define DCLK_SRC_SEL_MASK 0x3E000000
145 #define CG_UPLL_FUNC_CNTL_3 0x63C
146 # define UPLL_FB_DIV(x) ((x) << 0)
147 # define UPLL_FB_DIV_MASK 0x01FFFFFF
148 #define CG_UPLL_FUNC_CNTL_4 0x644
149 # define UPLL_SPARE_ISPARE9 0x00020000
150 #define CG_UPLL_FUNC_CNTL_5 0x648
151 # define RESET_ANTI_MUX_MASK 0x00000200
152 #define CG_UPLL_SPREAD_SPECTRUM 0x650
153 # define SSEN_MASK 0x00000001
155 #define MPLL_BYPASSCLK_SEL 0x65c
157 # define MPLL_CLKOUT_SEL_MASK 0xFF00
159 #define CG_CLKPIN_CNTL 0x660
162 #define CG_CLKPIN_CNTL_2 0x664
166 #define THM_CLK_CNTL 0x66c
167 # define CMON_CLK_SEL(x) ((x) << 0)
168 # define CMON_CLK_SEL_MASK 0xFF
170 # define TMON_CLK_SEL_MASK 0xFF00
171 #define MISC_CLK_CNTL 0x670
172 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
173 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
175 # define ZCLK_SEL_MASK 0xFF00
177 #define CG_THERMAL_CTRL 0x700
178 #define DPM_EVENT_SRC(x) ((x) << 0)
179 #define DPM_EVENT_SRC_MASK (7 << 0)
181 #define DIG_THERM_DPM_MASK 0x003FC000
183 #define CG_THERMAL_STATUS 0x704
185 #define FDO_PWM_DUTY_MASK (0xff << 9)
187 #define CG_THERMAL_INT 0x708
189 #define DIG_THERM_INTH_MASK 0x0000FF00
192 #define DIG_THERM_INTL_MASK 0x00FF0000
197 #define CG_MULT_THERMAL_CTRL 0x710
199 #define TEMP_SEL_MASK (0xff << 20)
201 #define CG_MULT_THERMAL_STATUS 0x714
202 #define ASIC_MAX_TEMP(x) ((x) << 0)
203 #define ASIC_MAX_TEMP_MASK 0x000001ff
204 #define ASIC_MAX_TEMP_SHIFT 0
206 #define CTF_TEMP_MASK 0x0003fe00
209 #define CG_FDO_CTRL0 0x754
210 #define FDO_STATIC_DUTY(x) ((x) << 0)
211 #define FDO_STATIC_DUTY_MASK 0x000000FF
212 #define FDO_STATIC_DUTY_SHIFT 0
213 #define CG_FDO_CTRL1 0x758
214 #define FMAX_DUTY100(x) ((x) << 0)
215 #define FMAX_DUTY100_MASK 0x000000FF
216 #define FMAX_DUTY100_SHIFT 0
217 #define CG_FDO_CTRL2 0x75C
218 #define TMIN(x) ((x) << 0)
219 #define TMIN_MASK 0x000000FF
220 #define TMIN_SHIFT 0
225 #define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
228 #define CG_TACH_CTRL 0x770
229 # define EDGE_PER_REV(x) ((x) << 0)
230 # define EDGE_PER_REV_MASK (0x7 << 0)
231 # define EDGE_PER_REV_SHIFT 0
233 # define TARGET_PERIOD_MASK 0xfffffff8
235 #define CG_TACH_STATUS 0x774
236 # define TACH_PERIOD(x) ((x) << 0)
237 # define TACH_PERIOD_MASK 0xffffffff
238 # define TACH_PERIOD_SHIFT 0
240 #define GENERAL_PWRMGT 0x780
241 # define GLOBAL_PWRMGT_EN (1 << 0)
250 #define CG_TPC 0x784
251 #define SCLK_PWRMGT_CNTL 0x788
252 # define SCLK_PWRMGT_OFF (1 << 0)
266 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x798
267 # define CURRENT_STATE_INDEX_MASK (0xf << 4)
270 #define CG_FTV 0x7bc
272 #define CG_FFCT_0 0x7c0
273 # define UTC_0(x) ((x) << 0)
274 # define UTC_0_MASK (0x3ff << 0)
276 # define DTC_0_MASK (0x3ff << 10)
278 #define CG_BSP 0x7fc
279 # define BSP(x) ((x) << 0)
280 # define BSP_MASK (0xffff << 0)
282 # define BSU_MASK (0xf << 16)
283 #define CG_AT 0x800
284 # define CG_R(x) ((x) << 0)
285 # define CG_R_MASK (0xffff << 0)
287 # define CG_L_MASK (0xffff << 16)
289 #define CG_GIT 0x804
290 # define CG_GICST(x) ((x) << 0)
291 # define CG_GICST_MASK (0xffff << 0)
293 # define CG_GIPOT_MASK (0xffff << 16)
295 #define CG_SSP 0x80c
296 # define SST(x) ((x) << 0)
297 # define SST_MASK (0xffff << 0)
299 # define SSTU_MASK (0xf << 16)
301 #define CG_DISPLAY_GAP_CNTL 0x828
302 # define DISP1_GAP(x) ((x) << 0)
303 # define DISP1_GAP_MASK (3 << 0)
307 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
315 #define CG_ULV_CONTROL 0x878
316 #define CG_ULV_PARAMETER 0x87c
318 #define SMC_SCRATCH0 0x884
320 #define CG_CAC_CTRL 0x8b8
321 # define CAC_WINDOW(x) ((x) << 0)
322 # define CAC_WINDOW_MASK 0x00ffffff
324 #define DMIF_ADDR_CONFIG 0xBD4
326 #define DMIF_ADDR_CALC 0xC00
328 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
329 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
332 #define SRBM_STATUS 0xE50
342 #define SRBM_SOFT_RESET 0x0E60
358 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
359 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
361 #define SRBM_READ_ERROR 0xE98
362 #define SRBM_INT_CNTL 0xEA0
363 #define SRBM_INT_ACK 0xEA8
365 #define SRBM_STATUS2 0x0EC4
369 #define VM_L2_CNTL 0x1400
370 #define ENABLE_L2_CACHE (1 << 0)
378 #define VM_L2_CNTL2 0x1404
379 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
382 #define INVALIDATE_PTE_AND_PDE_CACHES 0
385 #define VM_L2_CNTL3 0x1408
386 #define BANK_SELECT(x) ((x) << 0)
390 #define VM_L2_STATUS 0x140C
391 #define L2_BUSY (1 << 0)
392 #define VM_CONTEXT0_CNTL 0x1410
393 #define ENABLE_CONTEXT (1 << 0)
407 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
408 #define VM_CONTEXT1_CNTL 0x1414
409 #define VM_CONTEXT0_CNTL2 0x1430
410 #define VM_CONTEXT1_CNTL2 0x1434
411 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
412 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
413 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
414 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
415 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
416 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
417 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
418 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
420 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
421 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
422 #define PROTECTIONS_MASK (0xf << 0)
423 #define PROTECTIONS_SHIFT 0
424 /* bit 0: range
430 #define MEMORY_CLIENT_ID_MASK (0xff << 12)
434 #define FAULT_VMID_MASK (0xf << 25)
437 #define VM_INVALIDATE_REQUEST 0x1478
438 #define VM_INVALIDATE_RESPONSE 0x147c
440 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
441 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
443 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
444 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
445 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
446 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
447 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
448 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
449 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
450 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
451 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
452 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
454 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
455 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
457 #define VM_L2_CG 0x15c0
461 #define MC_SHARED_CHMAP 0x2004
463 #define NOOFCHAN_MASK 0x0000f000
464 #define MC_SHARED_CHREMAP 0x2008
466 #define MC_VM_FB_LOCATION 0x2024
467 #define MC_VM_AGP_TOP 0x2028
468 #define MC_VM_AGP_BOT 0x202C
469 #define MC_VM_AGP_BASE 0x2030
470 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
471 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
472 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
474 #define MC_VM_MX_L1_TLB_CNTL 0x2064
475 #define ENABLE_L1_TLB (1 << 0)
477 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
481 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
484 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
486 #define MC_HUB_MISC_HUB_CG 0x20b8
487 #define MC_HUB_MISC_VM_CG 0x20bc
489 #define MC_HUB_MISC_SIP_CG 0x20c0
491 #define MC_XPB_CLK_GAT 0x2478
493 #define MC_CITF_MISC_RD_CG 0x2648
494 #define MC_CITF_MISC_WR_CG 0x264c
495 #define MC_CITF_MISC_VM_CG 0x2650
497 #define MC_ARB_RAMCFG 0x2760
498 #define NOOFBANK_SHIFT 0
499 #define NOOFBANK_MASK 0x00000003
501 #define NOOFRANK_MASK 0x00000004
503 #define NOOFROWS_MASK 0x00000038
505 #define NOOFCOLS_MASK 0x000000C0
507 #define CHANSIZE_MASK 0x00000100
510 #define NOOFGROUPS_MASK 0x00001000
512 #define MC_ARB_DRAM_TIMING 0x2774
513 #define MC_ARB_DRAM_TIMING2 0x2778
515 #define MC_ARB_BURST_TIME 0x2808
516 #define STATE0(x) ((x) << 0)
517 #define STATE0_MASK (0x1f << 0)
518 #define STATE0_SHIFT 0
520 #define STATE1_MASK (0x1f << 5)
523 #define STATE2_MASK (0x1f << 10)
526 #define STATE3_MASK (0x1f << 15)
529 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
533 #define MC_SEQ_SUP_CNTL 0x28c8
534 #define RUN_MASK (1 << 0)
535 #define MC_SEQ_SUP_PGM 0x28cc
536 #define MC_PMG_AUTO_CMD 0x28d0
538 #define MC_IO_PAD_CNTL_D0 0x29d0
541 #define MC_SEQ_RAS_TIMING 0x28a0
542 #define MC_SEQ_CAS_TIMING 0x28a4
543 #define MC_SEQ_MISC_TIMING 0x28a8
544 #define MC_SEQ_MISC_TIMING2 0x28ac
545 #define MC_SEQ_PMG_TIMING 0x28b0
546 #define MC_SEQ_RD_CTL_D0 0x28b4
547 #define MC_SEQ_RD_CTL_D1 0x28b8
548 #define MC_SEQ_WR_CTL_D0 0x28bc
549 #define MC_SEQ_WR_CTL_D1 0x28c0
551 #define MC_SEQ_MISC0 0x2a00
553 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
556 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
559 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
561 #define MC_SEQ_MISC1 0x2a04
562 #define MC_SEQ_RESERVE_M 0x2a08
563 #define MC_PMG_CMD_EMRS 0x2a0c
565 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
566 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
568 #define MC_SEQ_MISC5 0x2a54
569 #define MC_SEQ_MISC6 0x2a58
571 #define MC_SEQ_MISC7 0x2a64
573 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
574 #define MC_SEQ_CAS_TIMING_LP 0x2a70
575 #define MC_SEQ_MISC_TIMING_LP 0x2a74
576 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
577 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
578 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
579 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
580 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
582 #define MC_PMG_CMD_MRS 0x2aac
584 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
585 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
587 #define MC_PMG_CMD_MRS1 0x2b44
588 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
589 #define MC_SEQ_PMG_TIMING_LP 0x2b4c
591 #define MC_SEQ_WR_CTL_2 0x2b54
592 #define MC_SEQ_WR_CTL_2_LP 0x2b58
593 #define MC_PMG_CMD_MRS2 0x2b5c
594 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
596 #define MCLK_PWRMGT_CNTL 0x2ba0
597 # define DLL_SPEED(x) ((x) << 0)
598 # define DLL_SPEED_MASK (0x1f << 0)
606 #define DLL_CNTL 0x2ba4
610 #define MPLL_CNTL_MODE 0x2bb0
612 #define MPLL_FUNC_CNTL 0x2bb4
614 #define BWCTRL_MASK (0xff << 20)
615 #define MPLL_FUNC_CNTL_1 0x2bb8
616 #define VCO_MODE(x) ((x) << 0)
617 #define VCO_MODE_MASK (3 << 0)
619 #define CLKFRAC_MASK (0xfff << 4)
621 #define CLKF_MASK (0xfff << 16)
622 #define MPLL_FUNC_CNTL_2 0x2bbc
623 #define MPLL_AD_FUNC_CNTL 0x2bc0
624 #define YCLK_POST_DIV(x) ((x) << 0)
625 #define YCLK_POST_DIV_MASK (7 << 0)
626 #define MPLL_DQ_FUNC_CNTL 0x2bc4
630 #define MPLL_SS1 0x2bcc
631 #define CLKV(x) ((x) << 0)
632 #define CLKV_MASK (0x3ffffff << 0)
633 #define MPLL_SS2 0x2bd0
634 #define CLKS(x) ((x) << 0)
635 #define CLKS_MASK (0xfff << 0)
637 #define HDP_HOST_PATH_CNTL 0x2C00
639 #define HDP_NONSURFACE_BASE 0x2C04
640 #define HDP_NONSURFACE_INFO 0x2C08
641 #define HDP_NONSURFACE_SIZE 0x2C0C
643 #define HDP_ADDR_CONFIG 0x2F48
644 #define HDP_MISC_CNTL 0x2F4C
645 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
646 #define HDP_MEM_POWER_LS 0x2F50
647 #define HDP_LS_ENABLE (1 << 0)
649 #define ATC_MISC_CG 0x3350
651 #define IH_RB_CNTL 0x3e00
652 # define IH_RB_ENABLE (1 << 0)
659 #define IH_RB_BASE 0x3e04
660 #define IH_RB_RPTR 0x3e08
661 #define IH_RB_WPTR 0x3e0c
662 # define RB_OVERFLOW (1 << 0)
663 # define WPTR_OFFSET_MASK 0x3fffc
664 #define IH_RB_WPTR_ADDR_HI 0x3e10
665 #define IH_RB_WPTR_ADDR_LO 0x3e14
666 #define IH_CNTL 0x3e18
667 # define ENABLE_INTR (1 << 0)
669 # define IH_MC_SWAP_NONE 0
678 #define CONFIG_MEMSIZE 0x5428
680 #define INTERRUPT_CNTL 0x5468
681 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
685 #define INTERRUPT_CNTL2 0x546c
687 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
689 #define BIF_FB_EN 0x5490
690 #define FB_READ_EN (1 << 0)
693 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
696 #define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00
697 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
699 #define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04
701 #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
702 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
703 #define SPEAKER_ALLOCATION_MASK (0x7f << 0)
704 #define SPEAKER_ALLOCATION_SHIFT 0
708 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
709 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
710 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
711 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
712 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
713 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
714 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
715 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
716 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (defaul…
717 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
718 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
719 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
720 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
721 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
722 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
724 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
725 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
726 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
737 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
738 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
739 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
741 * 0 = invalid
745 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
746 # define HBR_CAPABLE (1 << 0) /* enabled by default */
748 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
749 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
750 # define PRODUCT_ID(x) (((x) & 0xffff) << 16)
751 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
752 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
753 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
754 # define PORT_ID0(x) (((x) & 0xffffffff) << 0)
755 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
756 # define PORT_ID1(x) (((x) & 0xffffffff) << 0)
757 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
758 # define DESCRIPTION0(x) (((x) & 0xff) << 0)
759 # define DESCRIPTION1(x) (((x) & 0xff) << 8)
760 # define DESCRIPTION2(x) (((x) & 0xff) << 16)
761 # define DESCRIPTION3(x) (((x) & 0xff) << 24)
762 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
763 # define DESCRIPTION4(x) (((x) & 0xff) << 0)
764 # define DESCRIPTION5(x) (((x) & 0xff) << 8)
765 # define DESCRIPTION6(x) (((x) & 0xff) << 16)
766 # define DESCRIPTION7(x) (((x) & 0xff) << 24)
767 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
768 # define DESCRIPTION8(x) (((x) & 0xff) << 0)
769 # define DESCRIPTION9(x) (((x) & 0xff) << 8)
770 # define DESCRIPTION10(x) (((x) & 0xff) << 16)
771 # define DESCRIPTION11(x) (((x) & 0xff) << 24)
772 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
773 # define DESCRIPTION12(x) (((x) & 0xff) << 0)
774 # define DESCRIPTION13(x) (((x) & 0xff) << 8)
775 # define DESCRIPTION14(x) (((x) & 0xff) << 16)
776 # define DESCRIPTION15(x) (((x) & 0xff) << 24)
777 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
778 # define DESCRIPTION16(x) (((x) & 0xff) << 0)
779 # define DESCRIPTION17(x) (((x) & 0xff) << 8)
781 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
784 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
788 #define DC_LB_MEMORY_SPLIT 0x6b0c
791 #define PRIORITY_A_CNT 0x6b18
792 #define PRIORITY_MARK_MASK 0x7fff
795 #define PRIORITY_B_CNT 0x6b1c
797 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
799 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
800 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
803 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
804 #define VLINE_STATUS 0x6bb8
805 # define VLINE_OCCURRED (1 << 0)
810 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
811 #define VBLANK_STATUS 0x6bbc
812 # define VBLANK_OCCURRED (1 << 0)
818 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
819 #define INT_MASK 0x6b40
820 # define VBLANK_INT_MASK (1 << 0)
823 #define DISP_INTERRUPT_STATUS 0x60f4
832 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
838 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
843 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
848 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
853 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
859 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
860 #define GRPH_INT_STATUS 0x6858
861 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
863 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
864 #define GRPH_INT_CONTROL 0x685c
865 # define GRPH_PFLIP_INT_MASK (1 << 0)
868 #define DAC_AUTODETECT_INT_CONTROL 0x67c8
870 #define DC_HPD1_INT_STATUS 0x601c
871 #define DC_HPD2_INT_STATUS 0x6028
872 #define DC_HPD3_INT_STATUS 0x6034
873 #define DC_HPD4_INT_STATUS 0x6040
874 #define DC_HPD5_INT_STATUS 0x604c
875 #define DC_HPD6_INT_STATUS 0x6058
876 # define DC_HPDx_INT_STATUS (1 << 0)
880 #define DC_HPD1_INT_CONTROL 0x6020
881 #define DC_HPD2_INT_CONTROL 0x602c
882 #define DC_HPD3_INT_CONTROL 0x6038
883 #define DC_HPD4_INT_CONTROL 0x6044
884 #define DC_HPD5_INT_CONTROL 0x6050
885 #define DC_HPD6_INT_CONTROL 0x605c
886 # define DC_HPDx_INT_ACK (1 << 0)
892 #define DC_HPD1_CONTROL 0x6024
893 #define DC_HPD2_CONTROL 0x6030
894 #define DC_HPD3_CONTROL 0x603c
895 #define DC_HPD4_CONTROL 0x6048
896 #define DC_HPD5_CONTROL 0x6054
897 #define DC_HPD6_CONTROL 0x6060
898 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
902 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4
903 # define STUTTER_ENABLE (1 << 0)
905 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
906 #define CRTC_STATUS_FRAME_COUNT 0x6e98
909 #define DCCG_AUDIO_DTO_SOURCE 0x05ac
910 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
911 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
913 #define DCCG_AUDIO_DTO0_PHASE 0x05b0
914 #define DCCG_AUDIO_DTO0_MODULE 0x05b4
915 #define DCCG_AUDIO_DTO1_PHASE 0x05c0
916 #define DCCG_AUDIO_DTO1_MODULE 0x05c4
918 #define DENTIST_DISPCLK_CNTL 0x0490
919 # define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
920 # define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
923 #define AFMT_AUDIO_SRC_CONTROL 0x713c
924 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
926 * 0 = stream0
934 #define GRBM_CNTL 0x8000
935 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
937 #define GRBM_STATUS2 0x8008
938 #define RLC_RQ_PENDING (1 << 0)
942 #define GRBM_STATUS 0x8010
943 #define CMDFIFO_AVAIL_MASK 0x0000000F
968 #define GRBM_STATUS_SE0 0x8014
969 #define GRBM_STATUS_SE1 0x8018
982 #define GRBM_SOFT_RESET 0x8020
983 #define SOFT_RESET_CP (1 << 0)
998 #define GRBM_GFX_INDEX 0x802C
999 #define INSTANCE_INDEX(x) ((x) << 0)
1006 #define GRBM_INT_CNTL 0x8060
1007 # define RDERR_INT_ENABLE (1 << 0)
1010 #define CP_STRMOUT_CNTL 0x84FC
1011 #define SCRATCH_REG0 0x8500
1012 #define SCRATCH_REG1 0x8504
1013 #define SCRATCH_REG2 0x8508
1014 #define SCRATCH_REG3 0x850C
1015 #define SCRATCH_REG4 0x8510
1016 #define SCRATCH_REG5 0x8514
1017 #define SCRATCH_REG6 0x8518
1018 #define SCRATCH_REG7 0x851C
1020 #define SCRATCH_UMSK 0x8540
1021 #define SCRATCH_ADDR 0x8544
1023 #define CP_SEM_WAIT_TIMER 0x85BC
1025 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
1027 #define CP_ME_CNTL 0x86D8
1032 #define CP_COHER_CNTL2 0x85E8
1034 #define CP_RB2_RPTR 0x86f8
1035 #define CP_RB1_RPTR 0x86fc
1036 #define CP_RB0_RPTR 0x8700
1037 #define CP_RB_WPTR_DELAY 0x8704
1039 #define CP_QUEUE_THRESHOLDS 0x8760
1040 #define ROQ_IB1_START(x) ((x) << 0)
1042 #define CP_MEQ_THRESHOLDS 0x8764
1043 #define MEQ1_START(x) ((x) << 0)
1046 #define CP_PERFMON_CNTL 0x87FC
1048 #define VGT_VTX_VECT_EJECT_REG 0x88B0
1050 #define VGT_CACHE_INVALIDATION 0x88C4
1051 #define CACHE_INVALIDATION(x) ((x) << 0)
1052 #define VC_ONLY 0
1056 #define NO_AUTO 0
1060 #define VGT_ESGS_RING_SIZE 0x88C8
1061 #define VGT_GSVS_RING_SIZE 0x88CC
1063 #define VGT_GS_VERTEX_REUSE 0x88D4
1065 #define VGT_PRIMITIVE_TYPE 0x8958
1066 #define VGT_INDEX_TYPE 0x895C
1068 #define VGT_NUM_INDICES 0x8970
1069 #define VGT_NUM_INSTANCES 0x8974
1071 #define VGT_TF_RING_SIZE 0x8988
1073 #define VGT_HS_OFFCHIP_PARAM 0x89B0
1075 #define VGT_TF_MEMORY_BASE 0x89B8
1077 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1078 #define INACTIVE_CUS_MASK 0xFFFF0000
1080 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1082 #define PA_CL_ENHANCE 0x8A14
1083 #define CLIP_VTX_REORDER_ENA (1 << 0)
1086 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
1088 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
1090 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1091 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1094 #define PA_SC_FIFO_SIZE 0x8BCC
1095 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1100 #define PA_SC_ENHANCE 0x8BF0
1102 #define SQ_CONFIG 0x8C00
1104 #define SQC_CACHES 0x8C08
1106 #define SQ_POWER_THROTTLE 0x8e58
1107 #define MIN_POWER(x) ((x) << 0)
1108 #define MIN_POWER_MASK (0x3fff << 0)
1109 #define MIN_POWER_SHIFT 0
1111 #define MAX_POWER_MASK (0x3fff << 16)
1112 #define MAX_POWER_SHIFT 0
1113 #define SQ_POWER_THROTTLE2 0x8e5c
1114 #define MAX_POWER_DELTA(x) ((x) << 0)
1115 #define MAX_POWER_DELTA_MASK (0x3fff << 0)
1116 #define MAX_POWER_DELTA_SHIFT 0
1118 #define STI_SIZE_MASK (0x3ff << 16)
1121 #define LTI_RATIO_MASK (0xf << 27)
1124 #define SX_DEBUG_1 0x9060
1126 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
1127 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
1128 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
1129 #define SPI_PS_MAX_WAVE_ID 0x90EC
1131 #define SPI_CONFIG_CNTL 0x9100
1133 #define SPI_CONFIG_CNTL_1 0x913C
1134 #define VTX_DONE_DELAY(x) ((x) << 0)
1137 #define CGTS_TCC_DISABLE 0x9148
1138 #define CGTS_USER_TCC_DISABLE 0x914C
1139 #define TCC_DISABLE_MASK 0xFFFF0000
1141 #define CGTS_SM_CTRL_REG 0x9150
1145 #define SPI_LB_CU_MASK 0x9354
1147 #define TA_CNTL_AUX 0x9508
1148 #define TA_CS_BC_BASE_ADDR 0x950C
1150 #define CC_RB_BACKEND_DISABLE 0x98F4
1152 #define GB_ADDR_CONFIG 0x98F8
1153 #define NUM_PIPES(x) ((x) << 0)
1154 #define NUM_PIPES_MASK 0x00000007
1155 #define NUM_PIPES_SHIFT 0
1157 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1160 #define NUM_SHADER_ENGINES_MASK 0x00003000
1163 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1166 #define NUM_GPUS_MASK 0x00700000
1169 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
1172 #define ROW_SIZE_MASK 0x30000000
1175 #define GB_TILE_MODE0 0x9910
1176 # define MICRO_TILE_MODE(x) ((x) << 0)
1177 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
1181 # define ARRAY_LINEAR_GENERAL 0
1186 # define ADDR_SURF_P2 0
1199 # define ADDR_SURF_TILE_SPLIT_64B 0
1207 # define ADDR_SURF_BANK_WIDTH_1 0
1212 # define ADDR_SURF_BANK_HEIGHT_1 0
1217 # define ADDR_SURF_MACRO_ASPECT_1 0
1222 # define ADDR_SURF_2_BANK 0
1227 #define CB_PERFCOUNTER0_SELECT0 0x9a20
1228 #define CB_PERFCOUNTER0_SELECT1 0x9a24
1229 #define CB_PERFCOUNTER1_SELECT0 0x9a28
1230 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
1231 #define CB_PERFCOUNTER2_SELECT0 0x9a30
1232 #define CB_PERFCOUNTER2_SELECT1 0x9a34
1233 #define CB_PERFCOUNTER3_SELECT0 0x9a38
1234 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
1236 #define CB_CGTT_SCLK_CTRL 0x9a60
1238 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1239 #define BACKEND_DISABLE_MASK 0x00FF0000
1242 #define TCP_CHAN_STEER_LO 0xac0c
1243 #define TCP_CHAN_STEER_HI 0xac10
1245 #define CP_RB0_BASE 0xC100
1246 #define CP_RB0_CNTL 0xC104
1247 #define RB_BUFSZ(x) ((x) << 0)
1253 #define CP_RB0_RPTR_ADDR 0xC10C
1254 #define CP_RB0_RPTR_ADDR_HI 0xC110
1255 #define CP_RB0_WPTR 0xC114
1257 #define CP_PFP_UCODE_ADDR 0xC150
1258 #define CP_PFP_UCODE_DATA 0xC154
1259 #define CP_ME_RAM_RADDR 0xC158
1260 #define CP_ME_RAM_WADDR 0xC15C
1261 #define CP_ME_RAM_DATA 0xC160
1263 #define CP_CE_UCODE_ADDR 0xC168
1264 #define CP_CE_UCODE_DATA 0xC16C
1266 #define CP_RB1_BASE 0xC180
1267 #define CP_RB1_CNTL 0xC184
1268 #define CP_RB1_RPTR_ADDR 0xC188
1269 #define CP_RB1_RPTR_ADDR_HI 0xC18C
1270 #define CP_RB1_WPTR 0xC190
1271 #define CP_RB2_BASE 0xC194
1272 #define CP_RB2_CNTL 0xC198
1273 #define CP_RB2_RPTR_ADDR 0xC19C
1274 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
1275 #define CP_RB2_WPTR 0xC1A4
1276 #define CP_INT_CNTL_RING0 0xC1A8
1277 #define CP_INT_CNTL_RING1 0xC1AC
1278 #define CP_INT_CNTL_RING2 0xC1B0
1286 #define CP_INT_STATUS_RING0 0xC1B4
1287 #define CP_INT_STATUS_RING1 0xC1B8
1288 #define CP_INT_STATUS_RING2 0xC1BC
1295 #define CP_MEM_SLP_CNTL 0xC1E4
1296 # define CP_MEM_LS_EN (1 << 0)
1298 #define CP_DEBUG 0xC1FC
1300 #define RLC_CNTL 0xC300
1301 # define RLC_ENABLE (1 << 0)
1302 #define RLC_RL_BASE 0xC304
1303 #define RLC_RL_SIZE 0xC308
1304 #define RLC_LB_CNTL 0xC30C
1305 # define LOAD_BALANCE_ENABLE (1 << 0)
1306 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
1307 #define RLC_LB_CNTR_MAX 0xC314
1308 #define RLC_LB_CNTR_INIT 0xC318
1310 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
1312 #define RLC_UCODE_ADDR 0xC32C
1313 #define RLC_UCODE_DATA 0xC330
1315 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
1316 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
1317 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
1318 #define RLC_MC_CNTL 0xC344
1319 #define RLC_UCODE_CNTL 0xC348
1320 #define RLC_STAT 0xC34C
1321 # define RLC_BUSY_STATUS (1 << 0)
1326 #define RLC_PG_CNTL 0xC35C
1327 # define GFX_PG_ENABLE (1 << 0)
1330 #define RLC_CGTT_MGCG_OVERRIDE 0xC400
1331 #define RLC_CGCG_CGLS_CTRL 0xC404
1332 # define CGCG_EN (1 << 0)
1335 #define RLC_TTOP_D 0xC414
1336 # define RLC_PUD(x) ((x) << 0)
1337 # define RLC_PUD_MASK (0xff << 0)
1339 # define RLC_PDD_MASK (0xff << 8)
1341 # define RLC_TTPD_MASK (0xff << 16)
1343 # define RLC_MSD_MASK (0xff << 24)
1345 #define RLC_LB_INIT_CU_MASK 0xC41C
1347 #define RLC_PG_AO_CU_MASK 0xC42C
1348 #define RLC_MAX_PG_CU 0xC430
1349 # define MAX_PU_CU(x) ((x) << 0)
1350 # define MAX_PU_CU_MASK (0xff << 0)
1351 #define RLC_AUTO_PG_CTRL 0xC434
1352 # define AUTO_PG_EN (1 << 0)
1354 # define GRBM_REG_SGIT_MASK (0xffff << 3)
1356 # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
1358 #define RLC_SERDES_WR_MASTER_MASK_0 0xC454
1359 #define RLC_SERDES_WR_MASTER_MASK_1 0xC458
1360 #define RLC_SERDES_WR_CTRL 0xC45C
1362 #define RLC_SERDES_MASTER_BUSY_0 0xC464
1363 #define RLC_SERDES_MASTER_BUSY_1 0xC468
1365 #define RLC_GCPM_GENERAL_3 0xC478
1367 #define DB_RENDER_CONTROL 0x28000
1369 #define DB_DEPTH_INFO 0x2803c
1371 #define PA_SC_RASTER_CONFIG 0x28350
1372 # define RASTER_CONFIG_RB_MAP_0 0
1377 #define VGT_EVENT_INITIATOR 0x28a90
1378 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1379 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1380 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1381 # define CACHE_FLUSH_TS (4 << 0)
1382 # define CACHE_FLUSH (6 << 0)
1383 # define CS_PARTIAL_FLUSH (7 << 0)
1384 # define VGT_STREAMOUT_RESET (10 << 0)
1385 # define END_OF_PIPE_INCR_DE (11 << 0)
1386 # define END_OF_PIPE_IB_END (12 << 0)
1387 # define RST_PIX_CNT (13 << 0)
1388 # define VS_PARTIAL_FLUSH (15 << 0)
1389 # define PS_PARTIAL_FLUSH (16 << 0)
1390 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1391 # define ZPASS_DONE (21 << 0)
1392 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1393 # define PERFCOUNTER_START (23 << 0)
1394 # define PERFCOUNTER_STOP (24 << 0)
1395 # define PIPELINESTAT_START (25 << 0)
1396 # define PIPELINESTAT_STOP (26 << 0)
1397 # define PERFCOUNTER_SAMPLE (27 << 0)
1398 # define SAMPLE_PIPELINESTAT (30 << 0)
1399 # define SAMPLE_STREAMOUTSTATS (32 << 0)
1400 # define RESET_VTX_CNT (33 << 0)
1401 # define VGT_FLUSH (36 << 0)
1402 # define BOTTOM_OF_PIPE_TS (40 << 0)
1403 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
1404 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1405 # define FLUSH_AND_INV_DB_META (44 << 0)
1406 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1407 # define FLUSH_AND_INV_CB_META (46 << 0)
1408 # define CS_DONE (47 << 0)
1409 # define PS_DONE (48 << 0)
1410 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1411 # define THREAD_TRACE_START (51 << 0)
1412 # define THREAD_TRACE_STOP (52 << 0)
1413 # define THREAD_TRACE_FLUSH (54 << 0)
1414 # define THREAD_TRACE_FINISH (55 << 0)
1416 /* PIF PHY0 registers idx/data 0x8/0xc */
1417 #define PB0_PIF_CNTL 0x10
1419 # define LS2_EXIT_TIME_MASK (0x7 << 17)
1421 #define PB0_PIF_PAIRING 0x11
1423 #define PB0_PIF_PWRDOWN_0 0x12
1425 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1428 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1431 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1433 #define PB0_PIF_PWRDOWN_1 0x13
1435 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1438 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1441 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1444 #define PB0_PIF_PWRDOWN_2 0x17
1446 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1449 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1452 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1454 #define PB0_PIF_PWRDOWN_3 0x18
1456 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1459 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1462 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1464 /* PIF PHY1 registers idx/data 0x10/0x14 */
1465 #define PB1_PIF_CNTL 0x10
1466 #define PB1_PIF_PAIRING 0x11
1467 #define PB1_PIF_PWRDOWN_0 0x12
1468 #define PB1_PIF_PWRDOWN_1 0x13
1470 #define PB1_PIF_PWRDOWN_2 0x17
1471 #define PB1_PIF_PWRDOWN_3 0x18
1472 /* PCIE registers idx/data 0x30/0x34 */
1473 #define PCIE_CNTL2 0x1c /* PCIE */
1478 #define PCIE_LC_STATUS1 0x28 /* PCIE */
1479 # define LC_REVERSE_RCVR (1 << 0)
1481 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1483 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1486 #define PCIE_P_CNTL 0x40 /* PCIE */
1489 /* PCIE PORT registers idx/data 0x38/0x3c */
1490 #define PCIE_LC_CNTL 0xa0
1492 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
1495 # define LC_L1_INACTIVITY_MASK (0xf << 12)
1499 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1500 # define LC_LINK_WIDTH_SHIFT 0
1501 # define LC_LINK_WIDTH_MASK 0x7
1502 # define LC_LINK_WIDTH_X0 0
1509 # define LC_LINK_WIDTH_RD_MASK 0x70
1518 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1520 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1521 # define LC_XMIT_N_FTS(x) ((x) << 0)
1522 # define LC_XMIT_N_FTS_MASK (0xff << 0)
1523 # define LC_XMIT_N_FTS_SHIFT 0
1525 # define LC_N_FTS_MASK (0xff << 24)
1526 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1527 # define LC_GEN2_EN_STRAP (1 << 0)
1530 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1537 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1539 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1547 #define PCIE_LC_CNTL2 0xb1
1551 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1553 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1560 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1561 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1562 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1563 #define UVD_NO_OP 0xEFFC
1564 #define UVD_RBC_RB_RPTR 0xF690
1565 #define UVD_RBC_RB_WPTR 0xF694
1566 #define UVD_STATUS 0xf6bc
1568 #define UVD_CGC_CTRL 0xF4B0
1569 # define DCM (1 << 0)
1571 # define CG_DT_MASK (0xf << 2)
1573 # define CLK_OD_MASK (0x1f << 6)
1576 #define UVD_CGC_MEM_CTRL 0xC0
1577 #define UVD_CGC_CTRL2 0xC1
1578 # define DYN_OR_EN (1 << 0)
1581 # define G_DIV_ID_MASK (0x7 << 2)
1587 (((reg) >> 2) & 0xFFFF) | \
1588 ((n) & 0x3FFF) << 16)
1589 #define CP_PACKET2 0x80000000
1590 #define PACKET2_PAD_SHIFT 0
1591 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1596 (((op) & 0xFF) << 8) | \
1597 ((n) & 0x3FFF) << 16)
1602 #define PACKET3_NOP 0x10
1603 #define PACKET3_SET_BASE 0x11
1604 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1607 #define PACKET3_CLEAR_STATE 0x12
1608 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1609 #define PACKET3_DISPATCH_DIRECT 0x15
1610 #define PACKET3_DISPATCH_INDIRECT 0x16
1611 #define PACKET3_ALLOC_GDS 0x1B
1612 #define PACKET3_WRITE_GDS_RAM 0x1C
1613 #define PACKET3_ATOMIC_GDS 0x1D
1614 #define PACKET3_ATOMIC 0x1E
1615 #define PACKET3_OCCLUSION_QUERY 0x1F
1616 #define PACKET3_SET_PREDICATION 0x20
1617 #define PACKET3_REG_RMW 0x21
1618 #define PACKET3_COND_EXEC 0x22
1619 #define PACKET3_PRED_EXEC 0x23
1620 #define PACKET3_DRAW_INDIRECT 0x24
1621 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1622 #define PACKET3_INDEX_BASE 0x26
1623 #define PACKET3_DRAW_INDEX_2 0x27
1624 #define PACKET3_CONTEXT_CONTROL 0x28
1625 #define PACKET3_INDEX_TYPE 0x2A
1626 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1627 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1628 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1629 #define PACKET3_NUM_INSTANCES 0x2F
1630 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1631 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
1632 #define PACKET3_INDIRECT_BUFFER 0x32
1633 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1634 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1635 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1636 #define PACKET3_WRITE_DATA 0x37
1638 /* 0 - register
1648 /* 0 - me
1652 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1653 #define PACKET3_MEM_SEMAPHORE 0x39
1654 #define PACKET3_MPEG_INDEX 0x3A
1655 #define PACKET3_COPY_DW 0x3B
1656 #define PACKET3_WAIT_REG_MEM 0x3C
1657 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1658 /* 0 - always
1667 /* 0 - reg
1671 /* 0 - me
1674 #define PACKET3_MEM_WRITE 0x3D
1675 #define PACKET3_COPY_DATA 0x40
1676 #define PACKET3_CP_DMA 0x41
1678 * 2. SRC_ADDR_LO or DATA [31:0]
1680 * SRC_ADDR_HI [7:0]
1681 * 4. DST_ADDR_LO [31:0]
1682 * 5. DST_ADDR_HI [7:0]
1683 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1686 /* 0 - DST_ADDR
1690 /* 0 - ME
1694 /* 0 - SRC_ADDR
1702 /* 0 - none
1708 /* 0 - none
1714 /* 0 - memory
1718 /* 0 - memory
1724 #define PACKET3_PFP_SYNC_ME 0x42
1725 #define PACKET3_SURFACE_SYNC 0x43
1726 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1745 #define PACKET3_ME_INITIALIZE 0x44
1747 #define PACKET3_COND_WRITE 0x45
1748 #define PACKET3_EVENT_WRITE 0x46
1749 #define EVENT_TYPE(x) ((x) << 0)
1751 /* 0 - any non-TS event
1762 #define PACKET3_EVENT_WRITE_EOP 0x47
1764 /* 0 - discard
1770 /* 0 - none
1771 * 1 - interrupt only (DATA_SEL = 0)
1774 #define PACKET3_EVENT_WRITE_EOS 0x48
1775 #define PACKET3_PREAMBLE_CNTL 0x4A
1778 #define PACKET3_ONE_REG_WRITE 0x57
1779 #define PACKET3_LOAD_CONFIG_REG 0x5F
1780 #define PACKET3_LOAD_CONTEXT_REG 0x60
1781 #define PACKET3_LOAD_SH_REG 0x61
1782 #define PACKET3_SET_CONFIG_REG 0x68
1783 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1784 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1785 #define PACKET3_SET_CONTEXT_REG 0x69
1786 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1787 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1788 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1789 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1790 #define PACKET3_SET_SH_REG 0x76
1791 #define PACKET3_SET_SH_REG_START 0x0000b000
1792 #define PACKET3_SET_SH_REG_END 0x0000c000
1793 #define PACKET3_SET_SH_REG_OFFSET 0x77
1794 #define PACKET3_ME_WRITE 0x7A
1795 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1796 #define PACKET3_SCRATCH_RAM_READ 0x7E
1797 #define PACKET3_CE_WRITE 0x7F
1798 #define PACKET3_LOAD_CONST_RAM 0x80
1799 #define PACKET3_WRITE_CONST_RAM 0x81
1800 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1801 #define PACKET3_DUMP_CONST_RAM 0x83
1802 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1803 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1804 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1805 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1806 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1807 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1808 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1809 #define PACKET3_SWITCH_BUFFER 0x8B
1811 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1812 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1813 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1815 #define DMA_RB_CNTL 0xd000
1816 # define DMA_RB_ENABLE (1 << 0)
1822 #define DMA_RB_BASE 0xd004
1823 #define DMA_RB_RPTR 0xd008
1824 #define DMA_RB_WPTR 0xd00c
1826 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1827 #define DMA_RB_RPTR_ADDR_LO 0xd020
1829 #define DMA_IB_CNTL 0xd024
1830 # define DMA_IB_ENABLE (1 << 0)
1832 #define DMA_IB_RPTR 0xd028
1833 #define DMA_CNTL 0xd02c
1834 # define TRAP_ENABLE (1 << 0)
1840 #define DMA_STATUS_REG 0xd034
1841 # define DMA_IDLE (1 << 0)
1842 #define DMA_TILING_CONFIG 0xd0b8
1844 #define DMA_POWER_CNTL 0xd0bc
1846 #define DMA_CLK_CTRL 0xd0c0
1848 #define DMA_PG 0xd0d4
1849 # define PG_CNTL_ENABLE (1 << 0)
1850 #define DMA_PGFSM_CONFIG 0xd0d8
1851 #define DMA_PGFSM_WRITE 0xd0dc
1853 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1854 (((b) & 0x1) << 26) | \
1855 (((t) & 0x1) << 23) | \
1856 (((s) & 0x1) << 22) | \
1857 (((n) & 0xFFFFF) << 0))
1859 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1860 (((vmid) & 0xF) << 20) | \
1861 (((n) & 0xFFFFF) << 0))
1866 (((n) & 0xFFFFF) << 0))
1869 #define DMA_PACKET_WRITE 0x2
1870 #define DMA_PACKET_COPY 0x3
1871 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1872 #define DMA_PACKET_SEMAPHORE 0x5
1873 #define DMA_PACKET_FENCE 0x6
1874 #define DMA_PACKET_TRAP 0x7
1875 #define DMA_PACKET_SRBM_WRITE 0x9
1876 #define DMA_PACKET_CONSTANT_FILL 0xd
1877 #define DMA_PACKET_POLL_REG_MEM 0xe
1878 #define DMA_PACKET_NOP 0xf
1880 #define VCE_STATUS 0x20004
1881 #define VCE_VCPU_CNTL 0x20014
1882 #define VCE_CLK_EN (1 << 0)
1883 #define VCE_VCPU_CACHE_OFFSET0 0x20024
1884 #define VCE_VCPU_CACHE_SIZE0 0x20028
1885 #define VCE_VCPU_CACHE_OFFSET1 0x2002c
1886 #define VCE_VCPU_CACHE_SIZE1 0x20030
1887 #define VCE_VCPU_CACHE_OFFSET2 0x20034
1888 #define VCE_VCPU_CACHE_SIZE2 0x20038
1889 #define VCE_VCPU_SCRATCH7 0x200dc
1890 #define VCE_SOFT_RESET 0x20120
1891 #define VCE_ECPU_SOFT_RESET (1 << 0)
1893 #define VCE_RB_BASE_LO2 0x2016c
1894 #define VCE_RB_BASE_HI2 0x20170
1895 #define VCE_RB_SIZE2 0x20174
1896 #define VCE_RB_RPTR2 0x20178
1897 #define VCE_RB_WPTR2 0x2017c
1898 #define VCE_RB_BASE_LO 0x20180
1899 #define VCE_RB_BASE_HI 0x20184
1900 #define VCE_RB_SIZE 0x20188
1901 #define VCE_RB_RPTR 0x2018c
1902 #define VCE_RB_WPTR 0x20190
1903 #define VCE_CLOCK_GATING_A 0x202f8
1905 #define VCE_CLOCK_GATING_B 0x202fc
1906 #define VCE_UENC_CLOCK_GATING 0x205bc
1907 #define VCE_UENC_REG_CLOCK_GATING 0x205c0
1908 #define VCE_FW_REG_STATUS 0x20e10
1909 # define VCE_FW_REG_STATUS_BUSY (1 << 0)
1912 #define VCE_LMI_FW_START_KEYSEL 0x20e18
1913 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
1914 #define VCE_LMI_CTRL2 0x20e74
1915 #define VCE_LMI_CTRL 0x20e98
1916 #define VCE_LMI_VM_CTRL 0x20ea0
1917 #define VCE_LMI_SWAP_CNTL 0x20eb4
1918 #define VCE_LMI_SWAP_CNTL1 0x20eb8
1919 #define VCE_LMI_CACHE_CTRL 0x20ef4
1921 #define VCE_CMD_NO_OP 0x00000000
1922 #define VCE_CMD_END 0x00000001
1923 #define VCE_CMD_IB 0x00000002
1924 #define VCE_CMD_FENCE 0x00000003
1925 #define VCE_CMD_TRAP 0x00000004
1926 #define VCE_CMD_IB_AUTO 0x00000005
1927 #define VCE_CMD_SEMAPHORE 0x00000006
1930 #define CG_VCEPLL_FUNC_CNTL 0xc0030600
1931 # define VCEPLL_RESET_MASK 0x00000001
1932 # define VCEPLL_SLEEP_MASK 0x00000002
1933 # define VCEPLL_BYPASS_EN_MASK 0x00000004
1934 # define VCEPLL_CTLREQ_MASK 0x00000008
1935 # define VCEPLL_VCO_MODE_MASK 0x00000600
1936 # define VCEPLL_REF_DIV_MASK 0x003F0000
1937 # define VCEPLL_CTLACK_MASK 0x40000000
1938 # define VCEPLL_CTLACK2_MASK 0x80000000
1939 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601
1940 # define VCEPLL_PDIV_A(x) ((x) << 0)
1941 # define VCEPLL_PDIV_A_MASK 0x0000007F
1943 # define VCEPLL_PDIV_B_MASK 0x00007F00
1945 # define EVCLK_SRC_SEL_MASK 0x01F00000
1947 # define ECCLK_SRC_SEL_MASK 0x3E000000
1948 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602
1949 # define VCEPLL_FB_DIV(x) ((x) << 0)
1950 # define VCEPLL_FB_DIV_MASK 0x01FFFFFF
1951 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603
1952 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604
1953 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606
1954 # define VCEPLL_SSEN_MASK 0x00000001