Lines Matching refs:performance_level_count
2244 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2247 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2258 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()
2326 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2329 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2350 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
2967 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()
2972 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
2992 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3018 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3019 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3026 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3027 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3048 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3052 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3057 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3067 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3071 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3076 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3084 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3088 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3105 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3113 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3342 u32 levels = ps->performance_level_count; in si_dpm_force_performance_level()
4263 for (i = 0; i < state->performance_level_count; i++) { in si_do_program_memory_timing_parameters()
4907 for (i = 0; i < ps->performance_level_count - 1; i++) in si_populate_smc_sp()
4910 smc_state->levels[ps->performance_level_count - 1].bSP = in si_populate_smc_sp()
5034 if (state->performance_level_count >= 9) in si_populate_smc_t()
5037 if (state->performance_level_count < 2) { in si_populate_smc_t()
5045 for (i = 0; i <= state->performance_level_count - 2; i++) { in si_populate_smc_t()
5063 high_bsp = (i == state->performance_level_count - 2) ? in si_populate_smc_t()
5138 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) in si_convert_power_state_to_smc()
5141 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5155 for (i = 0; i < state->performance_level_count; i++) { in si_convert_power_state_to_smc()
5216 new_state->performance_level_count); in si_upload_sw_state()
5580 for (i = 0; i < state->performance_level_count; i++) { in si_convert_mc_reg_table_to_smc()
5642 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, in si_upload_mc_reg_table()
5662 for (i = 0; i < state->performance_level_count; i++) { in si_get_maximum_link_speed()
6680 ps->performance_level_count = index + 1; in si_parse_pplib_clock_info()
7039 if (current_index >= ps->performance_level_count) { in si_dpm_debugfs_print_current_performance_level()
7059 if (current_index >= ps->performance_level_count) { in si_dpm_get_current_sclk()
7077 if (current_index >= ps->performance_level_count) { in si_dpm_get_current_mclk()