Lines Matching +full:low +full:- +full:leakage
219 -1270850L,
492 -1270850L,
972 -1270850L,
1486 -1270850L,
1516 -1270850L,
1662 -1270850L,
1701 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1707 u16 v, s32 t, u32 ileakage, u32 *leakage) in si_calculate_leakage_for_v_and_t_formula() argument
1717 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1718 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1719 av = div64_s64(drm_int2fixp(coeff->av), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1720 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); in si_calculate_leakage_for_v_and_t_formula()
1721 t_ref = drm_int2fixp(coeff->t_ref); in si_calculate_leakage_for_v_and_t_formula()
1730 *leakage = drm_fixp2int(leakage_w * 1000); in si_calculate_leakage_for_v_and_t_formula()
1738 u32 *leakage) in si_calculate_leakage_for_v_and_t() argument
1740 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); in si_calculate_leakage_for_v_and_t()
1745 u32 ileakage, u32 *leakage) in si_calculate_leakage_for_v_formula() argument
1753 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), in si_calculate_leakage_for_v_formula()
1754 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); in si_calculate_leakage_for_v_formula()
1758 *leakage = drm_fixp2int(leakage_w * 1000); in si_calculate_leakage_for_v_formula()
1766 u32 *leakage) in si_calculate_leakage_for_v() argument
1768 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); in si_calculate_leakage_for_v()
1775 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1776 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1777 u32 k = dte_data->k; in si_update_dte_from_pl2()
1778 u32 t_max = dte_data->max_t; in si_update_dte_from_pl2()
1780 u32 t_0 = dte_data->t0; in si_update_dte_from_pl2()
1784 dte_data->tdep_count = 3; in si_update_dte_from_pl2()
1787 dte_data->r[i] = in si_update_dte_from_pl2()
1788 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / in si_update_dte_from_pl2()
1792 dte_data->tdep_r[1] = dte_data->r[4] * 2; in si_update_dte_from_pl2()
1795 dte_data->tdep_r[i] = dte_data->r[4]; in si_update_dte_from_pl2()
1808 if (rdev->family == CHIP_TAHITI) { in si_initialize_powertune_defaults()
1809 si_pi->cac_weights = cac_weights_tahiti; in si_initialize_powertune_defaults()
1810 si_pi->lcac_config = lcac_tahiti; in si_initialize_powertune_defaults()
1811 si_pi->cac_override = cac_override_tahiti; in si_initialize_powertune_defaults()
1812 si_pi->powertune_data = &powertune_data_tahiti; in si_initialize_powertune_defaults()
1813 si_pi->dte_data = dte_data_tahiti; in si_initialize_powertune_defaults()
1815 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1817 si_pi->dte_data.enable_dte_by_default = true; in si_initialize_powertune_defaults()
1820 si_pi->dte_data = dte_data_new_zealand; in si_initialize_powertune_defaults()
1826 si_pi->dte_data = dte_data_aruba_pro; in si_initialize_powertune_defaults()
1830 si_pi->dte_data = dte_data_malta; in si_initialize_powertune_defaults()
1834 si_pi->dte_data = dte_data_tahiti_pro; in si_initialize_powertune_defaults()
1838 if (si_pi->dte_data.enable_dte_by_default == true) in si_initialize_powertune_defaults()
1842 } else if (rdev->family == CHIP_PITCAIRN) { in si_initialize_powertune_defaults()
1843 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1846 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
1847 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
1848 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
1849 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
1850 si_pi->dte_data = dte_data_curacao_xt; in si_initialize_powertune_defaults()
1855 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
1856 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
1857 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
1858 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
1859 si_pi->dte_data = dte_data_curacao_pro; in si_initialize_powertune_defaults()
1864 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
1865 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
1866 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
1867 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
1868 si_pi->dte_data = dte_data_neptune_xt; in si_initialize_powertune_defaults()
1872 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
1873 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
1874 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
1875 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
1876 si_pi->dte_data = dte_data_pitcairn; in si_initialize_powertune_defaults()
1879 } else if (rdev->family == CHIP_VERDE) { in si_initialize_powertune_defaults()
1880 si_pi->lcac_config = lcac_cape_verde; in si_initialize_powertune_defaults()
1881 si_pi->cac_override = cac_override_cape_verde; in si_initialize_powertune_defaults()
1882 si_pi->powertune_data = &powertune_data_cape_verde; in si_initialize_powertune_defaults()
1884 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1889 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
1890 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
1893 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
1894 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
1899 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
1900 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
1904 si_pi->cac_weights = cac_weights_chelsea_xt; in si_initialize_powertune_defaults()
1905 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
1908 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
1909 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
1912 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
1913 si_pi->dte_data = dte_data_venus_xtx; in si_initialize_powertune_defaults()
1916 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
1917 si_pi->dte_data = dte_data_venus_xt; in si_initialize_powertune_defaults()
1923 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
1924 si_pi->dte_data = dte_data_venus_pro; in si_initialize_powertune_defaults()
1927 si_pi->cac_weights = cac_weights_cape_verde; in si_initialize_powertune_defaults()
1928 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
1931 } else if (rdev->family == CHIP_OLAND) { in si_initialize_powertune_defaults()
1932 switch (rdev->pdev->device) { in si_initialize_powertune_defaults()
1937 si_pi->cac_weights = cac_weights_mars_pro; in si_initialize_powertune_defaults()
1938 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
1939 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1940 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
1941 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
1948 si_pi->cac_weights = cac_weights_mars_xt; in si_initialize_powertune_defaults()
1949 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
1950 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1951 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
1952 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
1958 si_pi->cac_weights = cac_weights_oland_pro; in si_initialize_powertune_defaults()
1959 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
1960 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1961 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
1962 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
1966 si_pi->cac_weights = cac_weights_oland_xt; in si_initialize_powertune_defaults()
1967 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
1968 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1969 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
1970 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
1974 si_pi->cac_weights = cac_weights_oland; in si_initialize_powertune_defaults()
1975 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
1976 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1977 si_pi->powertune_data = &powertune_data_oland; in si_initialize_powertune_defaults()
1978 si_pi->dte_data = dte_data_oland; in si_initialize_powertune_defaults()
1981 } else if (rdev->family == CHIP_HAINAN) { in si_initialize_powertune_defaults()
1982 si_pi->cac_weights = cac_weights_hainan; in si_initialize_powertune_defaults()
1983 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
1984 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
1985 si_pi->powertune_data = &powertune_data_hainan; in si_initialize_powertune_defaults()
1986 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
1993 ni_pi->enable_power_containment = false; in si_initialize_powertune_defaults()
1994 ni_pi->enable_cac = false; in si_initialize_powertune_defaults()
1995 ni_pi->enable_sq_ramping = false; in si_initialize_powertune_defaults()
1996 si_pi->enable_dte = false; in si_initialize_powertune_defaults()
1998 if (si_pi->powertune_data->enable_powertune_by_default) { in si_initialize_powertune_defaults()
1999 ni_pi->enable_power_containment= true; in si_initialize_powertune_defaults()
2000 ni_pi->enable_cac = true; in si_initialize_powertune_defaults()
2001 if (si_pi->dte_data.enable_dte_by_default) { in si_initialize_powertune_defaults()
2002 si_pi->enable_dte = true; in si_initialize_powertune_defaults()
2004 si_update_dte_from_pl2(rdev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2007 ni_pi->enable_sq_ramping = true; in si_initialize_powertune_defaults()
2010 ni_pi->driver_calculate_cac_leakage = true; in si_initialize_powertune_defaults()
2011 ni_pi->cac_configuration_required = true; in si_initialize_powertune_defaults()
2013 if (ni_pi->cac_configuration_required) { in si_initialize_powertune_defaults()
2014 ni_pi->support_cac_long_term_average = true; in si_initialize_powertune_defaults()
2015 si_pi->dyn_powertune_data.l2_lta_window_size = in si_initialize_powertune_defaults()
2016 si_pi->powertune_data->l2_lta_window_size_default; in si_initialize_powertune_defaults()
2017 si_pi->dyn_powertune_data.lts_truncate = in si_initialize_powertune_defaults()
2018 si_pi->powertune_data->lts_truncate_default; in si_initialize_powertune_defaults()
2020 ni_pi->support_cac_long_term_average = false; in si_initialize_powertune_defaults()
2021 si_pi->dyn_powertune_data.l2_lta_window_size = 0; in si_initialize_powertune_defaults()
2022 si_pi->dyn_powertune_data.lts_truncate = 0; in si_initialize_powertune_defaults()
2025 si_pi->dyn_powertune_data.disable_uvd_powertune = false; in si_initialize_powertune_defaults()
2066 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2067 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2069 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2072 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2073 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2075 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2076 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2077 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2078 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2084 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2086 return -EINVAL; in si_calculate_adjusted_tdp_limits()
2097 if (ni_pi->enable_power_containment) { in si_populate_smc_tdp_limits()
2098 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits()
2100 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2107 return -EINVAL; in si_populate_smc_tdp_limits()
2113 rdev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2119 smc_table->dpm2Params.TDPLimit = in si_populate_smc_tdp_limits()
2121 smc_table->dpm2Params.NearTDPLimit = in si_populate_smc_tdp_limits()
2123 smc_table->dpm2Params.SafePowerLimit = in si_populate_smc_tdp_limits()
2127 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + in si_populate_smc_tdp_limits()
2129 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), in si_populate_smc_tdp_limits()
2131 si_pi->sram_end); in si_populate_smc_tdp_limits()
2135 if (si_pi->enable_ppm) { in si_populate_smc_tdp_limits()
2136 papm_parm = &si_pi->papm_parm; in si_populate_smc_tdp_limits()
2138 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); in si_populate_smc_tdp_limits()
2139 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); in si_populate_smc_tdp_limits()
2140 papm_parm->dGPU_T_Warning = cpu_to_be32(95); in si_populate_smc_tdp_limits()
2141 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); in si_populate_smc_tdp_limits()
2142 papm_parm->PlatformPowerLimit = 0xffffffff; in si_populate_smc_tdp_limits()
2143 papm_parm->NearTDPLimitPAPM = 0xffffffff; in si_populate_smc_tdp_limits()
2145 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2148 si_pi->sram_end); in si_populate_smc_tdp_limits()
2162 if (ni_pi->enable_power_containment) { in si_populate_smc_tdp_limits_2()
2163 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits_2()
2169 smc_table->dpm2Params.NearTDPLimit = in si_populate_smc_tdp_limits_2()
2170 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2171 smc_table->dpm2Params.SafePowerLimit = in si_populate_smc_tdp_limits_2()
2172 …cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2175 (si_pi->state_table_start + in si_populate_smc_tdp_limits_2()
2178 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), in si_populate_smc_tdp_limits_2()
2180 si_pi->sram_end); in si_populate_smc_tdp_limits_2()
2215 if (si_pi->dyn_powertune_data.disable_uvd_powertune && in si_should_disable_uvd_powertune()
2216 radeon_state->vclk && radeon_state->dclk) in si_should_disable_uvd_powertune()
2241 if (ni_pi->enable_power_containment == false) in si_populate_power_containment_values()
2244 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2245 return -EINVAL; in si_populate_power_containment_values()
2247 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2248 return -EINVAL; in si_populate_power_containment_values()
2252 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2253 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2254 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2255 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2256 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2258 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()
2259 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2260 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2267 return -EINVAL; in si_populate_power_containment_values()
2279 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2280 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2283 return -EINVAL; in si_populate_power_containment_values()
2285 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2286 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2294 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_power_containment_values()
2295 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2306 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2307 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2308 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2309 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2310 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
2323 bool enable_sq_ramping = ni_pi->enable_sq_ramping; in si_populate_sq_ramping_values()
2326 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2327 return -EINVAL; in si_populate_sq_ramping_values()
2329 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2330 return -EINVAL; in si_populate_sq_ramping_values()
2332 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2333 return -EINVAL; in si_populate_sq_ramping_values()
2350 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
2354 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2366 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); in si_populate_sq_ramping_values()
2367 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); in si_populate_sq_ramping_values()
2381 if (ni_pi->enable_power_containment) { in si_enable_power_containment()
2386 ret = -EINVAL; in si_enable_power_containment()
2387 ni_pi->pc_enabled = false; in si_enable_power_containment()
2389 ni_pi->pc_enabled = true; in si_enable_power_containment()
2395 ret = -EINVAL; in si_enable_power_containment()
2396 ni_pi->pc_enabled = false; in si_enable_power_containment()
2407 struct si_dte_data *dte_data = &si_pi->dte_data; in si_initialize_smc_dte_tables()
2414 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2416 if (si_pi->enable_dte == false) in si_initialize_smc_dte_tables()
2419 if (dte_data->k <= 0) in si_initialize_smc_dte_tables()
2420 return -EINVAL; in si_initialize_smc_dte_tables()
2424 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2425 return -ENOMEM; in si_initialize_smc_dte_tables()
2428 table_size = dte_data->k; in si_initialize_smc_dte_tables()
2433 tdep_count = dte_data->tdep_count; in si_initialize_smc_dte_tables()
2437 dte_tables->K = cpu_to_be32(table_size); in si_initialize_smc_dte_tables()
2438 dte_tables->T0 = cpu_to_be32(dte_data->t0); in si_initialize_smc_dte_tables()
2439 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); in si_initialize_smc_dte_tables()
2440 dte_tables->WindowSize = dte_data->window_size; in si_initialize_smc_dte_tables()
2441 dte_tables->temp_select = dte_data->temp_select; in si_initialize_smc_dte_tables()
2442 dte_tables->DTE_mode = dte_data->dte_mode; in si_initialize_smc_dte_tables()
2443 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); in si_initialize_smc_dte_tables()
2446 table_size--; in si_initialize_smc_dte_tables()
2449 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); in si_initialize_smc_dte_tables()
2450 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); in si_initialize_smc_dte_tables()
2453 dte_tables->Tdep_count = tdep_count; in si_initialize_smc_dte_tables()
2456 dte_tables->T_limits[i] = dte_data->t_limits[i]; in si_initialize_smc_dte_tables()
2457 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); in si_initialize_smc_dte_tables()
2458 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); in si_initialize_smc_dte_tables()
2461 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, in si_initialize_smc_dte_tables()
2462 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); in si_initialize_smc_dte_tables()
2473 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2479 return -EINVAL; in si_get_cac_std_voltage_max_min()
2484 for (i = 0; i < table->count; i++) { in si_get_cac_std_voltage_max_min()
2485 if (table->entries[i].vddc > *max) in si_get_cac_std_voltage_max_min()
2486 *max = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2487 if (table->entries[i].vddc < *min) in si_get_cac_std_voltage_max_min()
2488 *min = table->entries[i].vddc; in si_get_cac_std_voltage_max_min()
2491 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) in si_get_cac_std_voltage_max_min()
2492 return -EINVAL; in si_get_cac_std_voltage_max_min()
2494 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; in si_get_cac_std_voltage_max_min()
2497 return -EINVAL; in si_get_cac_std_voltage_max_min()
2502 return -EINVAL; in si_get_cac_std_voltage_max_min()
2509 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / in si_get_cac_std_voltage_step()
2519 u32 leakage; in si_init_dte_leakage_table() local
2532 voltage = vddc_max - (vddc_step * j); in si_init_dte_leakage_table()
2535 &si_pi->powertune_data->leakage_coefficients, in si_init_dte_leakage_table()
2538 si_pi->dyn_powertune_data.cac_leakage, in si_init_dte_leakage_table()
2539 &leakage); in si_init_dte_leakage_table()
2541 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; in si_init_dte_leakage_table()
2546 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = in si_init_dte_leakage_table()
2558 u32 leakage; in si_init_simplified_leakage_table() local
2567 voltage = vddc_max - (vddc_step * j); in si_init_simplified_leakage_table()
2570 &si_pi->powertune_data->leakage_coefficients, in si_init_simplified_leakage_table()
2571 si_pi->powertune_data->fixed_kt, in si_init_simplified_leakage_table()
2573 si_pi->dyn_powertune_data.cac_leakage, in si_init_simplified_leakage_table()
2574 &leakage); in si_init_simplified_leakage_table()
2576 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; in si_init_simplified_leakage_table()
2582 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = in si_init_simplified_leakage_table()
2599 if (ni_pi->enable_cac == false) in si_initialize_smc_cac_tables()
2604 return -ENOMEM; in si_initialize_smc_cac_tables()
2607 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); in si_initialize_smc_cac_tables()
2610 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2611 si_pi->dyn_powertune_data.dc_pwr_value = in si_initialize_smc_cac_tables()
2612 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; in si_initialize_smc_cac_tables()
2613 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); in si_initialize_smc_cac_tables()
2614 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; in si_initialize_smc_cac_tables()
2616 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; in si_initialize_smc_cac_tables()
2623 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); in si_initialize_smc_cac_tables()
2627 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) in si_initialize_smc_cac_tables()
2637 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
2639 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); in si_initialize_smc_cac_tables()
2640 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; in si_initialize_smc_cac_tables()
2641 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; in si_initialize_smc_cac_tables()
2642 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); in si_initialize_smc_cac_tables()
2643 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); in si_initialize_smc_cac_tables()
2644 cac_tables->R_LL = cpu_to_be32(load_line_slope); in si_initialize_smc_cac_tables()
2645 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); in si_initialize_smc_cac_tables()
2646 cac_tables->calculation_repeats = cpu_to_be32(2); in si_initialize_smc_cac_tables()
2647 cac_tables->dc_cac = cpu_to_be32(0); in si_initialize_smc_cac_tables()
2648 cac_tables->log2_PG_LKG_SCALE = 12; in si_initialize_smc_cac_tables()
2649 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; in si_initialize_smc_cac_tables()
2650 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); in si_initialize_smc_cac_tables()
2651 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); in si_initialize_smc_cac_tables()
2653 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, in si_initialize_smc_cac_tables()
2654 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); in si_initialize_smc_cac_tables()
2663 ni_pi->enable_cac = false; in si_initialize_smc_cac_tables()
2664 ni_pi->enable_power_containment = false; in si_initialize_smc_cac_tables()
2679 return -EINVAL; in si_program_cac_config_registers()
2681 while (config_regs->offset != 0xFFFFFFFF) { in si_program_cac_config_registers()
2682 switch (config_regs->type) { in si_program_cac_config_registers()
2684 offset = SMC_CG_IND_START + config_regs->offset; in si_program_cac_config_registers()
2689 data = RREG32(config_regs->offset << 2); in si_program_cac_config_registers()
2693 data &= ~config_regs->mask; in si_program_cac_config_registers()
2694 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); in si_program_cac_config_registers()
2696 switch (config_regs->type) { in si_program_cac_config_registers()
2698 offset = SMC_CG_IND_START + config_regs->offset; in si_program_cac_config_registers()
2703 WREG32(config_regs->offset << 2, data); in si_program_cac_config_registers()
2717 if ((ni_pi->enable_cac == false) || in si_initialize_hardware_cac_manager()
2718 (ni_pi->cac_configuration_required == false)) in si_initialize_hardware_cac_manager()
2721 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2724 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2727 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2743 if (ni_pi->enable_cac) { in si_enable_smc_cac()
2746 if (ni_pi->support_cac_long_term_average) { in si_enable_smc_cac()
2749 ni_pi->support_cac_long_term_average = false; in si_enable_smc_cac()
2754 ret = -EINVAL; in si_enable_smc_cac()
2755 ni_pi->cac_enabled = false; in si_enable_smc_cac()
2757 ni_pi->cac_enabled = true; in si_enable_smc_cac()
2760 if (si_pi->enable_dte) { in si_enable_smc_cac()
2763 ret = -EINVAL; in si_enable_smc_cac()
2766 } else if (ni_pi->cac_enabled) { in si_enable_smc_cac()
2767 if (si_pi->enable_dte) in si_enable_smc_cac()
2772 ni_pi->cac_enabled = false; in si_enable_smc_cac()
2774 if (ni_pi->support_cac_long_term_average) in si_enable_smc_cac()
2794 if (si_pi->spll_table_start == 0) in si_init_smc_spll_table()
2795 return -EINVAL; in si_init_smc_spll_table()
2799 return -ENOMEM; in si_init_smc_spll_table()
2816 ret = -EINVAL; in si_init_smc_spll_table()
2818 ret = -EINVAL; in si_init_smc_spll_table()
2820 ret = -EINVAL; in si_init_smc_spll_table()
2822 ret = -EINVAL; in si_init_smc_spll_table()
2829 spll_table->freq[i] = cpu_to_be32(tmp); in si_init_smc_spll_table()
2833 spll_table->ss[i] = cpu_to_be32(tmp); in si_init_smc_spll_table()
2840 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, in si_init_smc_spll_table()
2842 si_pi->sram_end); in si_init_smc_spll_table()
2845 ni_pi->enable_power_containment = false; in si_init_smc_spll_table()
2859 for (i = 0; i < si_pi->leakage_voltage.count; i++){ in si_get_lower_of_leakage_and_vce_voltage()
2860 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) in si_get_lower_of_leakage_and_vce_voltage()
2861 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; in si_get_lower_of_leakage_and_vce_voltage()
2864 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) in si_get_lower_of_leakage_and_vce_voltage()
2874 int ret = -EINVAL; in si_get_vce_clock_voltage()
2876 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
2879 (table && (table->count == 0))) { in si_get_vce_clock_voltage()
2884 for (i = 0; i < table->count; i++) { in si_get_vce_clock_voltage()
2885 if ((evclk <= table->entries[i].evclk) && in si_get_vce_clock_voltage()
2886 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
2887 *voltage = table->entries[i].v; in si_get_vce_clock_voltage()
2895 *voltage = table->entries[table->count - 1].v; in si_get_vce_clock_voltage()
2915 if (rdev->family == CHIP_HAINAN) { in si_apply_state_adjust_rules()
2916 if ((rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2917 (rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2918 (rdev->pdev->device == 0x6664) || in si_apply_state_adjust_rules()
2919 (rdev->pdev->device == 0x6665) || in si_apply_state_adjust_rules()
2920 (rdev->pdev->device == 0x6667)) { in si_apply_state_adjust_rules()
2923 if ((rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2924 (rdev->pdev->device == 0x6665)) { in si_apply_state_adjust_rules()
2928 } else if (rdev->family == CHIP_OLAND) { in si_apply_state_adjust_rules()
2929 if ((rdev->pdev->revision == 0xC7) || in si_apply_state_adjust_rules()
2930 (rdev->pdev->revision == 0x80) || in si_apply_state_adjust_rules()
2931 (rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2932 (rdev->pdev->revision == 0x83) || in si_apply_state_adjust_rules()
2933 (rdev->pdev->revision == 0x87) || in si_apply_state_adjust_rules()
2934 (rdev->pdev->device == 0x6604) || in si_apply_state_adjust_rules()
2935 (rdev->pdev->device == 0x6605)) { in si_apply_state_adjust_rules()
2939 if (rdev->pm.dpm.high_pixelclock_count > 1) in si_apply_state_adjust_rules()
2943 if (rps->vce_active) { in si_apply_state_adjust_rules()
2944 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
2945 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
2946 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
2949 rps->evclk = 0; in si_apply_state_adjust_rules()
2950 rps->ecclk = 0; in si_apply_state_adjust_rules()
2953 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
2957 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
2962 if (rdev->pm.dpm.ac_power) in si_apply_state_adjust_rules()
2963 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
2965 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
2967 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()
2968 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
2969 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
2971 if (rdev->pm.dpm.ac_power == false) { in si_apply_state_adjust_rules()
2972 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
2973 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
2974 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
2975 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
2976 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
2977 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
2978 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
2979 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
2980 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
2985 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
2987 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
2989 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
2992 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
2994 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
2995 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
2998 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
2999 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3002 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3003 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3006 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3007 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3010 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3011 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3018 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3019 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3021 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3022 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3026 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3027 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3029 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3030 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3033 if (rps->vce_active) { in si_apply_state_adjust_rules()
3034 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3035 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3036 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3037 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3040 /* adjusted low state */ in si_apply_state_adjust_rules()
3041 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3042 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3043 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3044 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3047 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3048 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3049 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3050 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3052 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3053 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3054 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3057 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3058 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3059 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3060 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3061 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3066 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3067 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3068 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3069 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3071 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3072 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3073 ps->performance_levels[i].vddci = vddci; in si_apply_state_adjust_rules()
3076 for (i = 1; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3077 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3078 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3079 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()
3080 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()
3084 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3086 &ps->performance_levels[i]); in si_apply_state_adjust_rules()
3088 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3089 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3090 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3091 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3092 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
3093 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3094 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3095 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3096 max_limits->vddci, &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3097 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3098 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3099 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3100 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3101 rdev->clock.current_dispclk, in si_apply_state_adjust_rules()
3102 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3105 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3107 max_limits->vddc, max_limits->vddci, in si_apply_state_adjust_rules()
3108 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3109 &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3112 ps->dc_compatible = true; in si_apply_state_adjust_rules()
3113 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3114 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3115 ps->dc_compatible = false; in si_apply_state_adjust_rules()
3126 si_pi->soft_regs_start + reg_offset, value,
3127 si_pi->sram_end);
3137 si_pi->soft_regs_start + reg_offset, in si_write_smc_soft_register()
3138 value, si_pi->sram_end); in si_write_smc_soft_register()
3160 density = (1 << (row + column - 20 + bank)) * width; in si_is_special_1gb_platform()
3162 if ((rdev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3179 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
3180 si_pi->leakage_voltage.entries[count].leakage_index = in si_get_leakage_vddc()
3185 si_pi->leakage_voltage.count = count; in si_get_leakage_vddc()
3195 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3198 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3201 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3204 return -EINVAL; in si_get_leakage_voltage_from_leakage_index()
3206 for (i = 0; i < si_pi->leakage_voltage.count; i++) { in si_get_leakage_voltage_from_leakage_index()
3207 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { in si_get_leakage_voltage_from_leakage_index()
3208 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; in si_get_leakage_voltage_from_leakage_index()
3212 return -EAGAIN; in si_get_leakage_voltage_from_leakage_index()
3243 if (pi->thermal_protection) in si_set_dpm_event_sources()
3257 if (!(pi->active_auto_throttle_sources & (1 << source))) { in si_enable_auto_throttle_source()
3258 pi->active_auto_throttle_sources |= 1 << source; in si_enable_auto_throttle_source()
3259 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3262 if (pi->active_auto_throttle_sources & (1 << source)) { in si_enable_auto_throttle_source()
3263 pi->active_auto_throttle_sources &= ~(1 << source); in si_enable_auto_throttle_source()
3264 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in si_enable_auto_throttle_source()
3299 return -EINVAL;
3315 0 : -EINVAL;
3331 return -EINVAL; in si_restrict_performance_levels_before_switch()
3334 0 : -EINVAL; in si_restrict_performance_levels_before_switch()
3340 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3342 u32 levels = ps->performance_level_count; in si_dpm_force_performance_level()
3346 return -EINVAL; in si_dpm_force_performance_level()
3349 return -EINVAL; in si_dpm_force_performance_level()
3352 return -EINVAL; in si_dpm_force_performance_level()
3355 return -EINVAL; in si_dpm_force_performance_level()
3358 return -EINVAL; in si_dpm_force_performance_level()
3361 return -EINVAL; in si_dpm_force_performance_level()
3364 rdev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
3373 0 : -EINVAL;
3380 0 : -EINVAL; in si_set_sw_state()
3386 return -EINVAL; in si_halt_smc()
3389 0 : -EINVAL; in si_halt_smc()
3395 return -EINVAL; in si_resume_smc()
3398 0 : -EINVAL; in si_resume_smc()
3423 &tmp, si_pi->sram_end); in si_process_firmware_header()
3427 si_pi->state_table_start = tmp; in si_process_firmware_header()
3432 &tmp, si_pi->sram_end); in si_process_firmware_header()
3436 si_pi->soft_regs_start = tmp; in si_process_firmware_header()
3441 &tmp, si_pi->sram_end); in si_process_firmware_header()
3445 si_pi->mc_reg_table_start = tmp; in si_process_firmware_header()
3450 &tmp, si_pi->sram_end); in si_process_firmware_header()
3454 si_pi->fan_table_start = tmp; in si_process_firmware_header()
3459 &tmp, si_pi->sram_end); in si_process_firmware_header()
3463 si_pi->arb_table_start = tmp; in si_process_firmware_header()
3468 &tmp, si_pi->sram_end); in si_process_firmware_header()
3472 si_pi->cac_table_start = tmp; in si_process_firmware_header()
3477 &tmp, si_pi->sram_end); in si_process_firmware_header()
3481 si_pi->dte_table_start = tmp; in si_process_firmware_header()
3486 &tmp, si_pi->sram_end); in si_process_firmware_header()
3490 si_pi->spll_table_start = tmp; in si_process_firmware_header()
3495 &tmp, si_pi->sram_end); in si_process_firmware_header()
3499 si_pi->papm_cfg_table_start = tmp; in si_process_firmware_header()
3508 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
3509 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
3510 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
3511 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); in si_read_clock_registers()
3512 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); in si_read_clock_registers()
3513 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in si_read_clock_registers()
3514 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in si_read_clock_registers()
3515 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in si_read_clock_registers()
3516 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in si_read_clock_registers()
3517 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
3518 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in si_read_clock_registers()
3519 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
3520 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in si_read_clock_registers()
3521 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()
3522 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in si_read_clock_registers()
3557 for (i = 0; i < rdev->usec_timeout; i++) {
3574 0 : -EINVAL; in si_notify_smc_display_change()
3585 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in si_program_response_times()
3610 if (eg_pi->sclk_deep_sleep) { in si_program_ds_registers()
3623 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3628 if (rdev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
3638 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3639 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
3641 for (i = 0; i < rdev->num_crtc; i++) { in si_program_display_gap()
3642 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
3645 if (i == rdev->num_crtc) in si_program_display_gap()
3655 /* Setting this to false forces the performance state to low if the crtcs are disabled. in si_program_display_gap()
3659 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3667 if (pi->sclk_ss) in si_enable_spread_spectrum()
3680 r600_calculate_u_and_p(pi->asi, in si_setup_bsp()
3683 &pi->bsp, in si_setup_bsp()
3684 &pi->bsu); in si_setup_bsp()
3686 r600_calculate_u_and_p(pi->pasi, in si_setup_bsp()
3689 &pi->pbsp, in si_setup_bsp()
3690 &pi->pbsu); in si_setup_bsp()
3693 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in si_setup_bsp()
3694 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in si_setup_bsp()
3696 WREG32(CG_BSP, pi->dsp); in si_setup_bsp()
3752 WREG32(CG_FTV, pi->vrc); in si_program_vc()
3769 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio()
3783 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio()
3790 mc_para_index = (u8)((memory_clock - 60000) / 5000); in si_get_mclk_frequency_ratio()
3801 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
3804 if (pi->mem_gddr5) in si_get_strobe_mode_settings()
3823 ret = si_load_smc_ucode(rdev, si_pi->sram_end); in si_upload_firmware()
3837 data = table->mask_low; in si_validate_phase_shedding_tables()
3846 if (table->count != num_levels) in si_validate_phase_shedding_tables()
3849 if (limits->count != (num_levels - 1)) in si_validate_phase_shedding_tables()
3861 if (voltage_table->count <= max_voltage_steps) in si_trim_voltage_table_to_fit_state_table()
3864 diff = voltage_table->count - max_voltage_steps; in si_trim_voltage_table_to_fit_state_table()
3867 voltage_table->entries[i] = voltage_table->entries[i + diff]; in si_trim_voltage_table_to_fit_state_table()
3869 voltage_table->count = max_voltage_steps; in si_trim_voltage_table_to_fit_state_table()
3879 return -EINVAL; in si_get_svi2_voltage_table()
3881 voltage_table->mask_low = 0; in si_get_svi2_voltage_table()
3882 voltage_table->phase_delay = 0; in si_get_svi2_voltage_table()
3884 voltage_table->count = voltage_dependency_table->count; in si_get_svi2_voltage_table()
3885 for (i = 0; i < voltage_table->count; i++) { in si_get_svi2_voltage_table()
3886 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; in si_get_svi2_voltage_table()
3887 voltage_table->entries[i].smio_low = 0; in si_get_svi2_voltage_table()
3900 if (pi->voltage_control) { in si_construct_voltage_tables()
3902 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
3906 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
3909 &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
3910 } else if (si_pi->voltage_control_svi2) { in si_construct_voltage_tables()
3912 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
3913 &eg_pi->vddc_voltage_table); in si_construct_voltage_tables()
3917 return -EINVAL; in si_construct_voltage_tables()
3920 if (eg_pi->vddci_control) { in si_construct_voltage_tables()
3922 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
3926 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
3929 &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
3931 if (si_pi->vddci_control_svi2) { in si_construct_voltage_tables()
3933 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
3934 &eg_pi->vddci_voltage_table); in si_construct_voltage_tables()
3939 if (pi->mvdd_control) { in si_construct_voltage_tables()
3941 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
3944 pi->mvdd_control = false; in si_construct_voltage_tables()
3948 if (si_pi->mvdd_voltage_table.count == 0) { in si_construct_voltage_tables()
3949 pi->mvdd_control = false; in si_construct_voltage_tables()
3950 return -EINVAL; in si_construct_voltage_tables()
3953 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
3956 &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
3959 if (si_pi->vddc_phase_shed_control) { in si_construct_voltage_tables()
3961 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); in si_construct_voltage_tables()
3963 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
3965 if ((si_pi->vddc_phase_shed_table.count == 0) || in si_construct_voltage_tables()
3966 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) in si_construct_voltage_tables()
3967 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
3979 for (i = 0; i < voltage_table->count; i++) in si_populate_smc_voltage_table()
3980 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); in si_populate_smc_voltage_table()
3991 if (si_pi->voltage_control_svi2) { in si_populate_smc_voltage_tables()
3993 si_pi->svc_gpio_id); in si_populate_smc_voltage_tables()
3995 si_pi->svd_gpio_id); in si_populate_smc_voltage_tables()
3999 if (eg_pi->vddc_voltage_table.count) { in si_populate_smc_voltage_tables()
4000 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); in si_populate_smc_voltage_tables()
4001 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = in si_populate_smc_voltage_tables()
4002 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4004 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { in si_populate_smc_voltage_tables()
4005 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { in si_populate_smc_voltage_tables()
4006 table->maxVDDCIndexInPPTable = i; in si_populate_smc_voltage_tables()
4012 if (eg_pi->vddci_voltage_table.count) { in si_populate_smc_voltage_tables()
4013 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); in si_populate_smc_voltage_tables()
4015 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = in si_populate_smc_voltage_tables()
4016 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4020 if (si_pi->mvdd_voltage_table.count) { in si_populate_smc_voltage_tables()
4021 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4023 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = in si_populate_smc_voltage_tables()
4024 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4027 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_voltage_tables()
4028 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4029 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4030 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4032 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = in si_populate_smc_voltage_tables()
4033 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); in si_populate_smc_voltage_tables()
4036 (u32)si_pi->vddc_phase_shed_table.phase_delay); in si_populate_smc_voltage_tables()
4038 si_pi->vddc_phase_shed_control = false; in si_populate_smc_voltage_tables()
4052 for (i = 0; i < table->count; i++) { in si_populate_voltage_value()
4053 if (value <= table->entries[i].value) { in si_populate_voltage_value()
4054 voltage->index = (u8)i; in si_populate_voltage_value()
4055 voltage->value = cpu_to_be16(table->entries[i].value); in si_populate_voltage_value()
4060 if (i >= table->count) in si_populate_voltage_value()
4061 return -EINVAL; in si_populate_voltage_value()
4072 if (pi->mvdd_control) { in si_populate_mvdd_value()
4073 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4074 voltage->index = 0; in si_populate_mvdd_value()
4076 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; in si_populate_mvdd_value()
4078 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); in si_populate_mvdd_value()
4089 *std_voltage = be16_to_cpu(voltage->value); in si_get_std_voltage_value()
4091 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4092 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4093 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4094 return -EINVAL; in si_get_std_voltage_value()
4096 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4097 if (be16_to_cpu(voltage->value) == in si_get_std_voltage_value()
4098 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4100 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4102 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4105 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4111 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4112 if (be16_to_cpu(voltage->value) <= in si_get_std_voltage_value()
4113 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4115 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4117 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4120 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4126 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4127 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4138 voltage->index = index; in si_populate_std_voltage_value()
4139 voltage->value = cpu_to_be16(value); in si_populate_std_voltage_value()
4151 for (i = 0; i < limits->count; i++) { in si_populate_phase_shedding_value()
4152 if ((voltage <= limits->entries[i].voltage) && in si_populate_phase_shedding_value()
4153 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
4154 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4158 smc_voltage->phase_settings = (u8)i; in si_populate_phase_shedding_value()
4169 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); in si_init_arb_table_index()
4176 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); in si_init_arb_table_index()
4187 0 : -EINVAL; in si_reset_to_default()
4196 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4197 &tmp, si_pi->sram_end); in si_force_switch_to_arb_f0()
4223 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4236 arb_regs->mc_arb_rfsh_rate = in si_populate_memory_timing_parameters()
4237 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); in si_populate_memory_timing_parameters()
4240 pl->sclk, in si_populate_memory_timing_parameters()
4241 pl->mclk); in si_populate_memory_timing_parameters()
4247 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); in si_populate_memory_timing_parameters()
4248 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); in si_populate_memory_timing_parameters()
4249 arb_regs->mc_arb_burst_time = (u8)burst_time; in si_populate_memory_timing_parameters()
4263 for (i = 0; i < state->performance_level_count; i++) { in si_do_program_memory_timing_parameters()
4264 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4268 si_pi->arb_table_start + in si_do_program_memory_timing_parameters()
4273 si_pi->sram_end); in si_do_program_memory_timing_parameters()
4294 if (pi->mvdd_control) in si_populate_initial_mvdd_value()
4295 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4296 si_pi->mvdd_bootup_value, voltage); in si_populate_initial_mvdd_value()
4312 table->initialState.level.mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4313 cpu_to_be32(si_pi->clock_registers.dll_cntl); in si_populate_smc_initial_state()
4314 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4315 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); in si_populate_smc_initial_state()
4316 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4317 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); in si_populate_smc_initial_state()
4318 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4319 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); in si_populate_smc_initial_state()
4320 table->initialState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4321 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); in si_populate_smc_initial_state()
4322 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4323 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); in si_populate_smc_initial_state()
4324 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4325 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); in si_populate_smc_initial_state()
4326 table->initialState.level.mclk.vMPLL_SS = in si_populate_smc_initial_state()
4327 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_initial_state()
4328 table->initialState.level.mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4329 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_initial_state()
4331 table->initialState.level.mclk.mclk_value = in si_populate_smc_initial_state()
4332 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4334 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4335 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); in si_populate_smc_initial_state()
4336 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4337 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); in si_populate_smc_initial_state()
4338 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_initial_state()
4339 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); in si_populate_smc_initial_state()
4340 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_initial_state()
4341 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); in si_populate_smc_initial_state()
4342 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = in si_populate_smc_initial_state()
4343 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); in si_populate_smc_initial_state()
4344 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in si_populate_smc_initial_state()
4345 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); in si_populate_smc_initial_state()
4347 table->initialState.level.sclk.sclk_value = in si_populate_smc_initial_state()
4348 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4350 table->initialState.level.arbRefreshState = in si_populate_smc_initial_state()
4353 table->initialState.level.ACIndex = 0; in si_populate_smc_initial_state()
4355 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_initial_state()
4356 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4357 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4363 &table->initialState.level.vddc, in si_populate_smc_initial_state()
4367 table->initialState.level.vddc.index, in si_populate_smc_initial_state()
4368 &table->initialState.level.std_vddc); in si_populate_smc_initial_state()
4371 if (eg_pi->vddci_control) in si_populate_smc_initial_state()
4373 &eg_pi->vddci_voltage_table, in si_populate_smc_initial_state()
4374 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4375 &table->initialState.level.vddci); in si_populate_smc_initial_state()
4377 if (si_pi->vddc_phase_shed_control) in si_populate_smc_initial_state()
4379 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4380 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4381 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4382 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4383 &table->initialState.level.vddc); in si_populate_smc_initial_state()
4385 si_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd); in si_populate_smc_initial_state()
4388 table->initialState.level.aT = cpu_to_be32(reg); in si_populate_smc_initial_state()
4390 table->initialState.level.bSP = cpu_to_be32(pi->dsp); in si_populate_smc_initial_state()
4392 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; in si_populate_smc_initial_state()
4394 if (pi->mem_gddr5) { in si_populate_smc_initial_state()
4395 table->initialState.level.strobeMode = in si_populate_smc_initial_state()
4397 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4399 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4400 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; in si_populate_smc_initial_state()
4402 table->initialState.level.mcFlags = 0; in si_populate_smc_initial_state()
4405 table->initialState.levelCount = 1; in si_populate_smc_initial_state()
4407 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; in si_populate_smc_initial_state()
4409 table->initialState.level.dpm2.MaxPS = 0; in si_populate_smc_initial_state()
4410 table->initialState.level.dpm2.NearTDPDec = 0; in si_populate_smc_initial_state()
4411 table->initialState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_initial_state()
4412 table->initialState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_initial_state()
4413 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_initial_state()
4416 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); in si_populate_smc_initial_state()
4419 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); in si_populate_smc_initial_state()
4430 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_populate_smc_acpi_state()
4431 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_populate_smc_acpi_state()
4432 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_populate_smc_acpi_state()
4433 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_populate_smc_acpi_state()
4434 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_smc_acpi_state()
4435 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_smc_acpi_state()
4436 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_smc_acpi_state()
4437 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_smc_acpi_state()
4438 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_smc_acpi_state()
4439 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_smc_acpi_state()
4440 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_smc_acpi_state()
4444 table->ACPIState = table->initialState; in si_populate_smc_acpi_state()
4446 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; in si_populate_smc_acpi_state()
4448 if (pi->acpi_vddc) { in si_populate_smc_acpi_state()
4449 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4450 pi->acpi_vddc, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4455 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4458 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4459 &table->ACPIState.level.std_vddc); in si_populate_smc_acpi_state()
4461 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; in si_populate_smc_acpi_state()
4463 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_acpi_state()
4465 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4466 pi->acpi_vddc, in si_populate_smc_acpi_state()
4469 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4472 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, in si_populate_smc_acpi_state()
4473 pi->min_vddc_in_table, &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4478 &table->ACPIState.level.vddc, &std_vddc); in si_populate_smc_acpi_state()
4482 table->ACPIState.level.vddc.index, in si_populate_smc_acpi_state()
4483 &table->ACPIState.level.std_vddc); in si_populate_smc_acpi_state()
4485 table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, in si_populate_smc_acpi_state()
4486 si_pi->sys_pcie_mask, in si_populate_smc_acpi_state()
4487 si_pi->boot_pcie_gen, in si_populate_smc_acpi_state()
4490 if (si_pi->vddc_phase_shed_control) in si_populate_smc_acpi_state()
4492 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
4493 pi->min_vddc_in_table, in si_populate_smc_acpi_state()
4496 &table->ACPIState.level.vddc); in si_populate_smc_acpi_state()
4499 if (pi->acpi_vddc) { in si_populate_smc_acpi_state()
4500 if (eg_pi->acpi_vddci) in si_populate_smc_acpi_state()
4501 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_populate_smc_acpi_state()
4502 eg_pi->acpi_vddci, in si_populate_smc_acpi_state()
4503 &table->ACPIState.level.vddci); in si_populate_smc_acpi_state()
4514 table->ACPIState.level.mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
4516 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
4518 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
4520 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
4522 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4524 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
4526 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4528 table->ACPIState.level.mclk.vMPLL_SS = in si_populate_smc_acpi_state()
4529 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_acpi_state()
4530 table->ACPIState.level.mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
4531 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_acpi_state()
4533 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4535 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4537 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = in si_populate_smc_acpi_state()
4539 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = in si_populate_smc_acpi_state()
4542 table->ACPIState.level.mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4543 table->ACPIState.level.sclk.sclk_value = 0; in si_populate_smc_acpi_state()
4545 si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd); in si_populate_smc_acpi_state()
4547 if (eg_pi->dynamic_ac_timing) in si_populate_smc_acpi_state()
4548 table->ACPIState.level.ACIndex = 0; in si_populate_smc_acpi_state()
4550 table->ACPIState.level.dpm2.MaxPS = 0; in si_populate_smc_acpi_state()
4551 table->ACPIState.level.dpm2.NearTDPDec = 0; in si_populate_smc_acpi_state()
4552 table->ACPIState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_acpi_state()
4553 table->ACPIState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_acpi_state()
4554 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_acpi_state()
4557 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); in si_populate_smc_acpi_state()
4560 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); in si_populate_smc_acpi_state()
4570 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_ulv_state()
4574 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, in si_populate_ulv_state()
4575 &state->level); in si_populate_ulv_state()
4577 if (eg_pi->sclk_deep_sleep) { in si_populate_ulv_state()
4579 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; in si_populate_ulv_state()
4581 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; in si_populate_ulv_state()
4583 if (ulv->one_pcie_lane_in_ulv) in si_populate_ulv_state()
4584 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; in si_populate_ulv_state()
4585 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); in si_populate_ulv_state()
4586 state->level.ACIndex = 1; in si_populate_ulv_state()
4587 state->level.std_vddc = state->level.vddc; in si_populate_ulv_state()
4588 state->levelCount = 1; in si_populate_ulv_state()
4590 state->flags |= PPSMC_SWSTATE_FLAG_DC; in si_populate_ulv_state()
4599 struct si_ulv_param *ulv = &si_pi->ulv; in si_program_ulv_memory_timing_parameters()
4603 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
4609 ulv->volt_change_delay); in si_program_ulv_memory_timing_parameters()
4612 si_pi->arb_table_start + in si_program_ulv_memory_timing_parameters()
4617 si_pi->sram_end); in si_program_ulv_memory_timing_parameters()
4626 pi->mvdd_split_frequency = 30000; in si_get_mvdd_configuration()
4633 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in si_init_smc_table()
4634 const struct si_ulv_param *ulv = &si_pi->ulv; in si_init_smc_table()
4635 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; in si_init_smc_table()
4642 switch (rdev->pm.int_thermal_type) { in si_init_smc_table()
4645 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; in si_init_smc_table()
4648 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; in si_init_smc_table()
4651 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; in si_init_smc_table()
4655 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
4656 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in si_init_smc_table()
4658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
4659 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) in si_init_smc_table()
4660 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; in si_init_smc_table()
4663 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
4664 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in si_init_smc_table()
4666 if (pi->mem_gddr5) in si_init_smc_table()
4667 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in si_init_smc_table()
4669 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
4670 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; in si_init_smc_table()
4672 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
4673 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; in si_init_smc_table()
4674 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; in si_init_smc_table()
4687 table->driverState.flags = table->initialState.flags; in si_init_smc_table()
4688 table->driverState.levelCount = table->initialState.levelCount; in si_init_smc_table()
4689 table->driverState.levels[0] = table->initialState.level; in si_init_smc_table()
4696 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
4697 ret = si_populate_ulv_state(rdev, &table->ULVState); in si_init_smc_table()
4705 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); in si_init_smc_table()
4706 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in si_init_smc_table()
4711 table->ULVState = table->initialState; in si_init_smc_table()
4714 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, in si_init_smc_table()
4716 si_pi->sram_end); in si_init_smc_table()
4726 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_calculate_sclk_params()
4727 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_calculate_sclk_params()
4728 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_calculate_sclk_params()
4729 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_calculate_sclk_params()
4730 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; in si_calculate_sclk_params()
4731 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
4733 u32 reference_clock = rdev->clock.spll.reference_freq; in si_calculate_sclk_params()
4760 if (pi->sclk_ss) { in si_calculate_sclk_params()
4778 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
4779 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; in si_calculate_sclk_params()
4780 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; in si_calculate_sclk_params()
4781 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; in si_calculate_sclk_params()
4782 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; in si_calculate_sclk_params()
4783 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; in si_calculate_sclk_params()
4784 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
4798 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); in si_populate_sclk_value()
4799 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); in si_populate_sclk_value()
4800 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); in si_populate_sclk_value()
4801 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); in si_populate_sclk_value()
4802 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); in si_populate_sclk_value()
4803 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); in si_populate_sclk_value()
4804 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); in si_populate_sclk_value()
4819 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_mclk_value()
4820 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_mclk_value()
4821 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_mclk_value()
4822 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_mclk_value()
4823 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_mclk_value()
4824 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_mclk_value()
4825 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_mclk_value()
4826 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; in si_populate_mclk_value()
4827 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; in si_populate_mclk_value()
4845 if (pi->mem_gddr5) { in si_populate_mclk_value()
4851 if (pi->mclk_ss) { in si_populate_mclk_value()
4855 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
4857 if (pi->mem_gddr5) in si_populate_mclk_value()
4885 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
4886 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
4887 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
4888 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
4889 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
4890 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
4891 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
4892 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
4893 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
4894 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
4907 for (i = 0; i < ps->performance_level_count - 1; i++) in si_populate_smc_sp()
4908 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in si_populate_smc_sp()
4910 smc_state->levels[ps->performance_level_count - 1].bSP = in si_populate_smc_sp()
4911 cpu_to_be32(pi->psp); in si_populate_smc_sp()
4926 if (eg_pi->pcie_performance_request && in si_convert_power_level_to_smc()
4927 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) in si_convert_power_level_to_smc()
4928 level->gen2PCIE = (u8)si_pi->force_pcie_gen; in si_convert_power_level_to_smc()
4930 level->gen2PCIE = (u8)pl->pcie_gen; in si_convert_power_level_to_smc()
4932 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); in si_convert_power_level_to_smc()
4936 level->mcFlags = 0; in si_convert_power_level_to_smc()
4938 if (pi->mclk_stutter_mode_threshold && in si_convert_power_level_to_smc()
4939 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
4940 !eg_pi->uvd_enabled && in si_convert_power_level_to_smc()
4942 (rdev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
4943 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; in si_convert_power_level_to_smc()
4946 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; in si_convert_power_level_to_smc()
4949 if (pi->mem_gddr5) { in si_convert_power_level_to_smc()
4950 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
4951 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; in si_convert_power_level_to_smc()
4953 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
4954 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; in si_convert_power_level_to_smc()
4956 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
4958 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { in si_convert_power_level_to_smc()
4959 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
4968 level->strobeMode = si_get_strobe_mode_settings(rdev, in si_convert_power_level_to_smc()
4969 pl->mclk); in si_convert_power_level_to_smc()
4975 pl->sclk, in si_convert_power_level_to_smc()
4976 pl->mclk, in si_convert_power_level_to_smc()
4977 &level->mclk, in si_convert_power_level_to_smc()
4978 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); in si_convert_power_level_to_smc()
4983 &eg_pi->vddc_voltage_table, in si_convert_power_level_to_smc()
4984 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
4989 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); in si_convert_power_level_to_smc()
4994 level->vddc.index, &level->std_vddc); in si_convert_power_level_to_smc()
4998 if (eg_pi->vddci_control) { in si_convert_power_level_to_smc()
4999 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, in si_convert_power_level_to_smc()
5000 pl->vddci, &level->vddci); in si_convert_power_level_to_smc()
5005 if (si_pi->vddc_phase_shed_control) { in si_convert_power_level_to_smc()
5007 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5008 pl->vddc, in si_convert_power_level_to_smc()
5009 pl->sclk, in si_convert_power_level_to_smc()
5010 pl->mclk, in si_convert_power_level_to_smc()
5011 &level->vddc); in si_convert_power_level_to_smc()
5016 level->MaxPoweredUpCU = si_pi->max_cu; in si_convert_power_level_to_smc()
5018 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5034 if (state->performance_level_count >= 9) in si_populate_smc_t()
5035 return -EINVAL; in si_populate_smc_t()
5037 if (state->performance_level_count < 2) { in si_populate_smc_t()
5039 smc_state->levels[0].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5043 smc_state->levels[0].aT = cpu_to_be32(0); in si_populate_smc_t()
5045 for (i = 0; i <= state->performance_level_count - 2; i++) { in si_populate_smc_t()
5049 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5050 state->performance_levels[i].sclk, in si_populate_smc_t()
5055 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; in si_populate_smc_t()
5059 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; in si_populate_smc_t()
5060 a_t |= CG_R(t_l * pi->bsp / 20000); in si_populate_smc_t()
5061 smc_state->levels[i].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5063 high_bsp = (i == state->performance_level_count - 2) ? in si_populate_smc_t()
5064 pi->pbsp : pi->bsp; in si_populate_smc_t()
5066 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5075 struct si_ulv_param *ulv = &si_pi->ulv; in si_disable_ulv()
5077 if (ulv->supported) in si_disable_ulv()
5079 0 : -EINVAL; in si_disable_ulv()
5088 const struct si_ulv_param *ulv = &si_pi->ulv; in si_is_state_ulv_compatible()
5092 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5097 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5098 if (rdev->clock.current_dispclk <= in si_is_state_ulv_compatible()
5099 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5100 if (ulv->pl.vddc < in si_is_state_ulv_compatible()
5101 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5106 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) in si_is_state_ulv_compatible()
5116 const struct si_ulv_param *ulv = &si_pi->ulv; in si_set_power_state_conditionally_enable_ulv()
5118 if (ulv->supported) { in si_set_power_state_conditionally_enable_ulv()
5121 0 : -EINVAL; in si_set_power_state_conditionally_enable_ulv()
5138 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) in si_convert_power_state_to_smc()
5139 return -EINVAL; in si_convert_power_state_to_smc()
5141 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5143 if (radeon_state->vclk && radeon_state->dclk) { in si_convert_power_state_to_smc()
5144 eg_pi->uvd_enabled = true; in si_convert_power_state_to_smc()
5145 if (eg_pi->smu_uvd_hs) in si_convert_power_state_to_smc()
5146 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; in si_convert_power_state_to_smc()
5148 eg_pi->uvd_enabled = false; in si_convert_power_state_to_smc()
5151 if (state->dc_compatible) in si_convert_power_state_to_smc()
5152 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in si_convert_power_state_to_smc()
5154 smc_state->levelCount = 0; in si_convert_power_state_to_smc()
5155 for (i = 0; i < state->performance_level_count; i++) { in si_convert_power_state_to_smc()
5156 if (eg_pi->sclk_deep_sleep) { in si_convert_power_state_to_smc()
5157 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { in si_convert_power_state_to_smc()
5159 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; in si_convert_power_state_to_smc()
5161 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; in si_convert_power_state_to_smc()
5165 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5166 &smc_state->levels[i]); in si_convert_power_state_to_smc()
5167 smc_state->levels[i].arbRefreshState = in si_convert_power_state_to_smc()
5173 if (ni_pi->enable_power_containment) in si_convert_power_state_to_smc()
5174 smc_state->levels[i].displayWatermark = in si_convert_power_state_to_smc()
5175 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
5178 smc_state->levels[i].displayWatermark = (i < 2) ? in si_convert_power_state_to_smc()
5181 if (eg_pi->dynamic_ac_timing) in si_convert_power_state_to_smc()
5182 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; in si_convert_power_state_to_smc()
5184 smc_state->levels[i].ACIndex = 0; in si_convert_power_state_to_smc()
5186 smc_state->levelCount++; in si_convert_power_state_to_smc()
5197 ni_pi->enable_power_containment = false; in si_convert_power_state_to_smc()
5201 ni_pi->enable_sq_ramping = false; in si_convert_power_state_to_smc()
5212 u32 address = si_pi->state_table_start + in si_upload_sw_state()
5214 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; in si_upload_sw_state()
5216 new_state->performance_level_count); in si_upload_sw_state()
5225 state_size, si_pi->sram_end); in si_upload_sw_state()
5233 struct si_ulv_param *ulv = &si_pi->ulv; in si_upload_ulv_state()
5236 if (ulv->supported && ulv->pl.vddc) { in si_upload_ulv_state()
5237 u32 address = si_pi->state_table_start + in si_upload_ulv_state()
5239 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; in si_upload_ulv_state()
5247 state_size, si_pi->sram_end); in si_upload_ulv_state()
5258 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5261 for (i = 0; i < rdev->num_crtc; i++) { in si_upload_smc_data()
5262 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
5263 radeon_crtc = rdev->mode_info.crtcs[i]; in si_upload_smc_data()
5271 if (radeon_crtc->line_time <= 0) in si_upload_smc_data()
5276 radeon_crtc->crtc_id) != PPSMC_Result_OK) in si_upload_smc_data()
5281 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) in si_upload_smc_data()
5286 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) in si_upload_smc_data()
5299 for (i = 0, j = table->last; i < table->last; i++) { in si_set_mc_special_registers()
5301 return -EINVAL; in si_set_mc_special_registers()
5302 switch (table->mc_reg_address[i].s1 << 2) { in si_set_mc_special_registers()
5305 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in si_set_mc_special_registers()
5306 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in si_set_mc_special_registers()
5307 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5308 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5310 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in si_set_mc_special_registers()
5313 return -EINVAL; in si_set_mc_special_registers()
5316 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in si_set_mc_special_registers()
5317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in si_set_mc_special_registers()
5318 for (k = 0; k < table->num_entries; k++) { in si_set_mc_special_registers()
5319 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5321 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5322 if (!pi->mem_gddr5) in si_set_mc_special_registers()
5323 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in si_set_mc_special_registers()
5327 return -EINVAL; in si_set_mc_special_registers()
5329 if (!pi->mem_gddr5) { in si_set_mc_special_registers()
5330 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers()
5331 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers()
5332 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5333 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5334 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in si_set_mc_special_registers()
5337 return -EINVAL; in si_set_mc_special_registers()
5342 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in si_set_mc_special_registers()
5343 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in si_set_mc_special_registers()
5344 for(k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5345 table->mc_reg_table_entry[k].mc_data[j] = in si_set_mc_special_registers()
5347 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5350 return -EINVAL; in si_set_mc_special_registers()
5357 table->last = j; in si_set_mc_special_registers()
5421 for (i = 0; i < table->last; i++) { in si_set_valid_flag()
5422 for (j = 1; j < table->num_entries; j++) { in si_set_valid_flag()
5423 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { in si_set_valid_flag()
5424 table->valid_flag |= 1 << i; in si_set_valid_flag()
5436 for (i = 0; i < table->last; i++) in si_set_s0_mc_reg_index()
5437 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in si_set_s0_mc_reg_index()
5438 address : table->mc_reg_address[i].s1; in si_set_s0_mc_reg_index()
5447 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) in si_copy_vbios_mc_reg_table()
5448 return -EINVAL; in si_copy_vbios_mc_reg_table()
5449 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in si_copy_vbios_mc_reg_table()
5450 return -EINVAL; in si_copy_vbios_mc_reg_table()
5452 for (i = 0; i < table->last; i++) in si_copy_vbios_mc_reg_table()
5453 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in si_copy_vbios_mc_reg_table()
5454 si_table->last = table->last; in si_copy_vbios_mc_reg_table()
5456 for (i = 0; i < table->num_entries; i++) { in si_copy_vbios_mc_reg_table()
5457 si_table->mc_reg_table_entry[i].mclk_max = in si_copy_vbios_mc_reg_table()
5458 table->mc_reg_table_entry[i].mclk_max; in si_copy_vbios_mc_reg_table()
5459 for (j = 0; j < table->last; j++) { in si_copy_vbios_mc_reg_table()
5460 si_table->mc_reg_table_entry[i].mc_data[j] = in si_copy_vbios_mc_reg_table()
5461 table->mc_reg_table_entry[i].mc_data[j]; in si_copy_vbios_mc_reg_table()
5464 si_table->num_entries = table->num_entries; in si_copy_vbios_mc_reg_table()
5473 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; in si_initialize_mc_reg_table()
5479 return -ENOMEM; in si_initialize_mc_reg_table()
5525 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { in si_populate_mc_reg_addresses()
5526 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { in si_populate_mc_reg_addresses()
5529 mc_reg_table->address[i].s0 = in si_populate_mc_reg_addresses()
5530 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); in si_populate_mc_reg_addresses()
5531 mc_reg_table->address[i].s1 = in si_populate_mc_reg_addresses()
5532 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); in si_populate_mc_reg_addresses()
5536 mc_reg_table->last = (u8)i; in si_populate_mc_reg_addresses()
5547 data->value[i] = cpu_to_be32(entry->mc_data[j]); in si_convert_mc_registers()
5560 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { in si_convert_mc_reg_table_entry_to_smc()
5561 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
5565 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) in si_convert_mc_reg_table_entry_to_smc()
5566 --i; in si_convert_mc_reg_table_entry_to_smc()
5568 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], in si_convert_mc_reg_table_entry_to_smc()
5569 mc_reg_table_data, si_pi->mc_reg_table.last, in si_convert_mc_reg_table_entry_to_smc()
5570 si_pi->mc_reg_table.valid_flag); in si_convert_mc_reg_table_entry_to_smc()
5580 for (i = 0; i < state->performance_level_count; i++) { in si_convert_mc_reg_table_to_smc()
5582 &state->performance_levels[i], in si_convert_mc_reg_table_to_smc()
5583 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); in si_convert_mc_reg_table_to_smc()
5592 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_mc_reg_table()
5593 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_populate_mc_reg_table()
5601 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
5602 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); in si_populate_mc_reg_table()
5604 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
5605 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], in si_populate_mc_reg_table()
5606 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
5607 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
5609 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
5610 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, in si_populate_mc_reg_table()
5611 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); in si_populate_mc_reg_table()
5613 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
5614 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], in si_populate_mc_reg_table()
5615 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
5616 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
5620 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
5622 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); in si_populate_mc_reg_table()
5630 u32 address = si_pi->mc_reg_table_start + in si_upload_mc_reg_table()
5633 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_upload_mc_reg_table()
5641 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], in si_upload_mc_reg_table()
5642 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, in si_upload_mc_reg_table()
5643 si_pi->sram_end); in si_upload_mc_reg_table()
5662 for (i = 0; i < state->performance_level_count; i++) { in si_get_maximum_link_speed()
5663 pcie_speed = state->performance_levels[i].pcie_gen; in si_get_maximum_link_speed()
5688 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in si_request_link_speed_change_before_state_change()
5691 current_link_speed = si_pi->force_pcie_gen; in si_request_link_speed_change_before_state_change()
5693 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in si_request_link_speed_change_before_state_change()
5694 si_pi->pspp_notify_required = false; in si_request_link_speed_change_before_state_change()
5701 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; in si_request_link_speed_change_before_state_change()
5711 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); in si_request_link_speed_change_before_state_change()
5716 si_pi->pspp_notify_required = true; in si_request_link_speed_change_before_state_change()
5728 if (si_pi->pspp_notify_required) { in si_notify_link_speed_change_after_state_change()
5752 if (eg_pi->sclk_deep_sleep) {
5756 0 : -EINVAL;
5759 PPSMC_Result_OK) ? 0 : -EINVAL;
5769 if (rdev->family == CHIP_VERDE) { in si_set_max_cu_value()
5770 switch (rdev->pdev->device) { in si_set_max_cu_value()
5776 si_pi->max_cu = 10; in si_set_max_cu_value()
5782 si_pi->max_cu = 8; in si_set_max_cu_value()
5790 si_pi->max_cu = 10; in si_set_max_cu_value()
5795 si_pi->max_cu = 8; in si_set_max_cu_value()
5798 si_pi->max_cu = 0; in si_set_max_cu_value()
5802 si_pi->max_cu = 0; in si_set_max_cu_value()
5814 for (i = 0; i < table->count; i++) { in si_patch_single_dependency_table_based_on_leakage()
5816 table->entries[i].v, in si_patch_single_dependency_table_based_on_leakage()
5819 table->entries[i].v = leakage_voltage; in si_patch_single_dependency_table_based_on_leakage()
5821 case -EAGAIN: in si_patch_single_dependency_table_based_on_leakage()
5822 return -EINVAL; in si_patch_single_dependency_table_based_on_leakage()
5823 case -EINVAL: in si_patch_single_dependency_table_based_on_leakage()
5829 for (j = (table->count - 2); j >= 0; j--) { in si_patch_single_dependency_table_based_on_leakage()
5830 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? in si_patch_single_dependency_table_based_on_leakage()
5831 table->entries[j].v : table->entries[j + 1].v; in si_patch_single_dependency_table_based_on_leakage()
5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
5844 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5846 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
5856 …((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) +… in si_set_pcie_lane_width_in_smc()
5858 …((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIF… in si_set_pcie_lane_width_in_smc()
5871 if ((old_rps->evclk != new_rps->evclk) || in si_set_vce_clock()
5872 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
5874 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5878 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
5904 rdev->irq.dpm_thermal = false; in si_thermal_enable_alert()
5908 return -EINVAL; in si_thermal_enable_alert()
5913 rdev->irq.dpm_thermal = true; in si_thermal_enable_alert()
5930 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in si_thermal_set_temperature_range()
5931 return -EINVAL; in si_thermal_set_temperature_range()
5938 rdev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
5939 rdev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
5949 if (si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_static_mode()
5951 si_pi->fan_ctrl_default_mode = tmp; in si_fan_ctrl_set_static_mode()
5953 si_pi->t_min = tmp; in si_fan_ctrl_set_static_mode()
5954 si_pi->fan_ctrl_is_in_default_mode = false; in si_fan_ctrl_set_static_mode()
5977 if (!si_pi->fan_table_start) { in si_thermal_setup_fan_table()
5978 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5985 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
5989 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
5993 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
5994 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
5996 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
5997 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6002 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6003 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6004 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6011 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6021 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6030 si_pi->fan_table_start, in si_thermal_setup_fan_table()
6033 si_pi->sram_end); in si_thermal_setup_fan_table()
6037 rdev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6050 si_pi->fan_is_controlled_by_smc = true; in si_fan_ctrl_start_smc_fan_control()
6053 return -EINVAL; in si_fan_ctrl_start_smc_fan_control()
6065 si_pi->fan_is_controlled_by_smc = false; in si_fan_ctrl_stop_smc_fan_control()
6068 return -EINVAL; in si_fan_ctrl_stop_smc_fan_control()
6078 if (rdev->pm.no_fan) in si_fan_ctrl_get_fan_speed_percent()
6079 return -ENOENT; in si_fan_ctrl_get_fan_speed_percent()
6085 return -EINVAL; in si_fan_ctrl_get_fan_speed_percent()
6105 if (rdev->pm.no_fan) in si_fan_ctrl_set_fan_speed_percent()
6106 return -ENOENT; in si_fan_ctrl_set_fan_speed_percent()
6108 if (si_pi->fan_is_controlled_by_smc) in si_fan_ctrl_set_fan_speed_percent()
6109 return -EINVAL; in si_fan_ctrl_set_fan_speed_percent()
6112 return -EINVAL; in si_fan_ctrl_set_fan_speed_percent()
6117 return -EINVAL; in si_fan_ctrl_set_fan_speed_percent()
6133 /* stop auto-manage */ in si_fan_ctrl_set_mode()
6134 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6138 /* restart auto-manage */ in si_fan_ctrl_set_mode()
6139 if (rdev->pm.dpm.fan.ucode_fan_control) in si_fan_ctrl_set_mode()
6151 if (si_pi->fan_is_controlled_by_smc) in si_fan_ctrl_get_mode()
6165 if (rdev->pm.no_fan)
6166 return -ENOENT;
6168 if (rdev->pm.fan_pulses_per_revolution == 0)
6169 return -ENOENT;
6173 return -ENOENT;
6186 if (rdev->pm.no_fan)
6187 return -ENOENT;
6189 if (rdev->pm.fan_pulses_per_revolution == 0)
6190 return -ENOENT;
6192 if ((speed < rdev->pm.fan_min_rpm) ||
6193 (speed > rdev->pm.fan_max_rpm))
6194 return -EINVAL;
6196 if (rdev->pm.dpm.fan.ucode_fan_control)
6215 if (!si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_default_mode()
6217 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); in si_fan_ctrl_set_default_mode()
6221 tmp |= TMIN(si_pi->t_min); in si_fan_ctrl_set_default_mode()
6223 si_pi->fan_ctrl_is_in_default_mode = true; in si_fan_ctrl_set_default_mode()
6229 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6239 if (rdev->pm.fan_pulses_per_revolution) { in si_thermal_initialize()
6241 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); in si_thermal_initialize()
6261 if (rdev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6279 if (!rdev->pm.no_fan) { in si_thermal_stop_thermal_controller()
6290 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_enable()
6294 return -EINVAL; in si_dpm_enable()
6295 if (pi->voltage_control || si_pi->voltage_control_svi2) in si_dpm_enable()
6297 if (pi->mvdd_control) in si_dpm_enable()
6299 if (pi->voltage_control || si_pi->voltage_control_svi2) { in si_dpm_enable()
6306 if (eg_pi->dynamic_ac_timing) { in si_dpm_enable()
6309 eg_pi->dynamic_ac_timing = false; in si_dpm_enable()
6311 if (pi->dynamic_ss) in si_dpm_enable()
6313 if (pi->thermal_protection) in si_dpm_enable()
6352 if (eg_pi->dynamic_ac_timing) { in si_dpm_enable()
6435 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in si_dpm_disable()
6442 if (pi->thermal_protection) in si_dpm_disable()
6459 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6464 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); in si_dpm_pre_set_power_state()
6471 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level()
6498 struct radeon_ps *new_ps = &eg_pi->requested_rps; in si_dpm_set_power_state()
6499 struct radeon_ps *old_ps = &eg_pi->current_rps; in si_dpm_set_power_state()
6512 if (eg_pi->pcie_performance_request) in si_dpm_set_power_state()
6545 if (eg_pi->dynamic_ac_timing) { in si_dpm_set_power_state()
6571 if (eg_pi->pcie_performance_request) in si_dpm_set_power_state()
6601 struct radeon_ps *new_ps = &eg_pi->requested_rps; in si_dpm_post_set_power_state()
6647 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in si_parse_pplib_non_clock_info()
6648 rps->class = le16_to_cpu(non_clock_info->usClassification); in si_parse_pplib_non_clock_info()
6649 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in si_parse_pplib_non_clock_info()
6652 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in si_parse_pplib_non_clock_info()
6653 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in si_parse_pplib_non_clock_info()
6654 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info()
6655 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in si_parse_pplib_non_clock_info()
6656 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in si_parse_pplib_non_clock_info()
6658 rps->vclk = 0; in si_parse_pplib_non_clock_info()
6659 rps->dclk = 0; in si_parse_pplib_non_clock_info()
6662 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) in si_parse_pplib_non_clock_info()
6663 rdev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
6664 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in si_parse_pplib_non_clock_info()
6665 rdev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
6677 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info()
6680 ps->performance_level_count = index + 1; in si_parse_pplib_clock_info()
6682 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_pplib_clock_info()
6683 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_pplib_clock_info()
6684 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
6685 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
6687 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); in si_parse_pplib_clock_info()
6688 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); in si_parse_pplib_clock_info()
6689 pl->flags = le32_to_cpu(clock_info->si.ulFlags); in si_parse_pplib_clock_info()
6690 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in si_parse_pplib_clock_info()
6691 si_pi->sys_pcie_mask, in si_parse_pplib_clock_info()
6692 si_pi->boot_pcie_gen, in si_parse_pplib_clock_info()
6693 clock_info->si.ucPCIEGen); in si_parse_pplib_clock_info()
6696 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, in si_parse_pplib_clock_info()
6699 pl->vddc = leakage_voltage; in si_parse_pplib_clock_info()
6701 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { in si_parse_pplib_clock_info()
6702 pi->acpi_vddc = pl->vddc; in si_parse_pplib_clock_info()
6703 eg_pi->acpi_vddci = pl->vddci; in si_parse_pplib_clock_info()
6704 si_pi->acpi_pcie_gen = pl->pcie_gen; in si_parse_pplib_clock_info()
6707 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && in si_parse_pplib_clock_info()
6710 si_pi->ulv.supported = false; in si_parse_pplib_clock_info()
6711 si_pi->ulv.pl = *pl; in si_parse_pplib_clock_info()
6712 si_pi->ulv.one_pcie_lane_in_ulv = false; in si_parse_pplib_clock_info()
6713 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; in si_parse_pplib_clock_info()
6714 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; in si_parse_pplib_clock_info()
6715 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; in si_parse_pplib_clock_info()
6718 if (pi->min_vddc_in_table > pl->vddc) in si_parse_pplib_clock_info()
6719 pi->min_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6721 if (pi->max_vddc_in_table < pl->vddc) in si_parse_pplib_clock_info()
6722 pi->max_vddc_in_table = pl->vddc; in si_parse_pplib_clock_info()
6725 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in si_parse_pplib_clock_info()
6728 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6729 pl->sclk = rdev->clock.default_sclk; in si_parse_pplib_clock_info()
6730 pl->vddc = vddc; in si_parse_pplib_clock_info()
6731 pl->vddci = vddci; in si_parse_pplib_clock_info()
6732 si_pi->mvdd_bootup_value = mvdd; in si_parse_pplib_clock_info()
6735 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == in si_parse_pplib_clock_info()
6737 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
6738 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6739 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
6740 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
6746 struct radeon_mode_info *mode_info = &rdev->mode_info; in si_parse_power_table()
6761 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in si_parse_power_table()
6763 return -EINVAL; in si_parse_power_table()
6764 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in si_parse_power_table()
6767 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
6768 le16_to_cpu(power_info->pplib.usStateArrayOffset)); in si_parse_power_table()
6770 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
6771 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); in si_parse_power_table()
6773 (mode_info->atom_context->bios + data_offset + in si_parse_power_table()
6774 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); in si_parse_power_table()
6776 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
6779 if (!rdev->pm.dpm.ps) in si_parse_power_table()
6780 return -ENOMEM; in si_parse_power_table()
6781 power_state_offset = (u8 *)state_array->states; in si_parse_power_table()
6782 for (i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
6785 non_clock_array_index = power_state->v2.nonClockInfoIndex; in si_parse_power_table()
6787 &non_clock_info_array->nonClockInfo[non_clock_array_index]; in si_parse_power_table()
6788 if (!rdev->pm.power_state[i].clock_info) in si_parse_power_table()
6789 return -EINVAL; in si_parse_power_table()
6792 kfree(rdev->pm.dpm.ps); in si_parse_power_table()
6793 return -ENOMEM; in si_parse_power_table()
6795 rdev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
6796 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in si_parse_power_table()
6798 non_clock_info_array->ucEntrySize); in si_parse_power_table()
6800 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in si_parse_power_table()
6801 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()
6803 if (clock_array_index >= clock_info_array->ucNumEntries) in si_parse_power_table()
6808 ((u8 *)&clock_info_array->clockInfo[0] + in si_parse_power_table()
6809 (clock_array_index * clock_info_array->ucEntrySize)); in si_parse_power_table()
6811 &rdev->pm.dpm.ps[i], k, in si_parse_power_table()
6815 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()
6817 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
6822 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
6824 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; in si_parse_power_table()
6825 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); in si_parse_power_table()
6826 sclk |= clock_info->si.ucEngineClockHigh << 16; in si_parse_power_table()
6827 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_power_table()
6828 mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_power_table()
6829 rdev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
6830 rdev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
6844 struct pci_dev *root = rdev->pdev->bus->self; in si_dpm_init()
6849 return -ENOMEM; in si_dpm_init()
6850 rdev->pm.dpm.priv = si_pi; in si_dpm_init()
6851 ni_pi = &si_pi->ni; in si_dpm_init()
6852 eg_pi = &ni_pi->eg; in si_dpm_init()
6853 pi = &eg_pi->rv7xx; in si_dpm_init()
6855 if (!pci_is_root_bus(rdev->pdev->bus)) in si_dpm_init()
6858 si_pi->sys_pcie_mask = 0; in si_dpm_init()
6861 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in si_dpm_init()
6865 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in si_dpm_init()
6868 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in si_dpm_init()
6870 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in si_dpm_init()
6871 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); in si_dpm_init()
6879 pi->acpi_vddc = 0; in si_dpm_init()
6880 eg_pi->acpi_vddci = 0; in si_dpm_init()
6881 pi->min_vddc_in_table = 0; in si_dpm_init()
6882 pi->max_vddc_in_table = 0; in si_dpm_init()
6896 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
6900 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
6902 return -ENOMEM; in si_dpm_init()
6904 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
6905 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6906 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6907 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
6908 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
6909 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
6910 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
6911 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
6912 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
6914 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6915 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
6916 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6917 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
6922 pi->ref_div = dividers.ref_div + 1; in si_dpm_init()
6924 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in si_dpm_init()
6926 eg_pi->smu_uvd_hs = false; in si_dpm_init()
6928 pi->mclk_strobe_mode_threshold = 40000; in si_dpm_init()
6930 pi->mclk_stutter_mode_threshold = 0; in si_dpm_init()
6932 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; in si_dpm_init()
6933 pi->mclk_edc_enable_threshold = 40000; in si_dpm_init()
6934 eg_pi->mclk_edc_wr_enable_threshold = 40000; in si_dpm_init()
6936 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; in si_dpm_init()
6938 pi->voltage_control = in si_dpm_init()
6941 if (!pi->voltage_control) { in si_dpm_init()
6942 si_pi->voltage_control_svi2 = in si_dpm_init()
6945 if (si_pi->voltage_control_svi2) in si_dpm_init()
6947 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); in si_dpm_init()
6950 pi->mvdd_control = in si_dpm_init()
6954 eg_pi->vddci_control = in si_dpm_init()
6957 if (!eg_pi->vddci_control) in si_dpm_init()
6958 si_pi->vddci_control_svi2 = in si_dpm_init()
6962 si_pi->vddc_phase_shed_control = in si_dpm_init()
6968 pi->asi = RV770_ASI_DFLT; in si_dpm_init()
6969 pi->pasi = CYPRESS_HASI_DFLT; in si_dpm_init()
6970 pi->vrc = SISLANDS_VRC_DFLT; in si_dpm_init()
6972 pi->gfx_clock_gating = true; in si_dpm_init()
6974 eg_pi->sclk_deep_sleep = true; in si_dpm_init()
6975 si_pi->sclk_deep_sleep_above_low = false; in si_dpm_init()
6977 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in si_dpm_init()
6978 pi->thermal_protection = true; in si_dpm_init()
6980 pi->thermal_protection = false; in si_dpm_init()
6982 eg_pi->dynamic_ac_timing = true; in si_dpm_init()
6984 eg_pi->light_sleep = true; in si_dpm_init()
6986 eg_pi->pcie_performance_request = in si_dpm_init()
6989 eg_pi->pcie_performance_request = false; in si_dpm_init()
6992 si_pi->sram_end = SMC_RAM_END; in si_dpm_init()
6994 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
6995 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
6996 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
6997 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
6998 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
6999 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7000 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7005 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7006 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7007 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7008 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7010 si_pi->fan_ctrl_is_in_default_mode = true; in si_dpm_init()
7019 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7020 kfree(rdev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7022 kfree(rdev->pm.dpm.ps); in si_dpm_fini()
7023 kfree(rdev->pm.dpm.priv); in si_dpm_fini()
7024 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7032 struct radeon_ps *rps = &eg_pi->current_rps; in si_dpm_debugfs_print_current_performance_level()
7039 if (current_index >= ps->performance_level_count) { in si_dpm_debugfs_print_current_performance_level()
7042 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7043 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
7045 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7052 struct radeon_ps *rps = &eg_pi->current_rps; in si_dpm_get_current_sclk()
7059 if (current_index >= ps->performance_level_count) { in si_dpm_get_current_sclk()
7062 pl = &ps->performance_levels[current_index]; in si_dpm_get_current_sclk()
7063 return pl->sclk; in si_dpm_get_current_sclk()
7070 struct radeon_ps *rps = &eg_pi->current_rps; in si_dpm_get_current_mclk()
7077 if (current_index >= ps->performance_level_count) { in si_dpm_get_current_mclk()
7080 pl = &ps->performance_levels[current_index]; in si_dpm_get_current_mclk()
7081 return pl->mclk; in si_dpm_get_current_mclk()