Lines Matching +full:0 +full:x0000ffff
40 #define MC_CG_ARB_FREQ_F0 0x0a
41 #define MC_CG_ARB_FREQ_F1 0x0b
42 #define MC_CG_ARB_FREQ_F2 0x0c
43 #define MC_CG_ARB_FREQ_F3 0x0d
45 #define SMC_RAM_END 0x20000
50 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
51 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
53 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
54 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
55 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
56 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
57 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
58 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
59 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
60 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
61 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
62 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
63 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
64 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
65 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
66 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
68 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
70 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
71 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
72 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
73 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
74 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
76 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
78 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
80 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
81 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
82 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
83 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
84 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
85 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
87 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
88 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
89 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
90 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
93 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
94 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
95 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
96 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
97 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
98 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
99 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
100 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
101 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
102 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
103 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
104 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
105 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
106 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
107 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
108 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
109 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
110 { 0xFFFFFFFF }
114 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
117 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
119 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
121 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
133 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
135 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
137 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
157 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
159 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
161 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
169 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
171 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
173 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
181 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
183 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
185 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
187 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
195 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
196 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
197 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
198 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
199 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
200 { 0xFFFFFFFF }
205 { 0xFFFFFFFF }
211 0,
215 0UL,
216 0UL,
226 0,
227 0,
228 0,
229 0,
230 0,
231 0,
232 0,
233 0
239 { 1159409, 0, 0, 0, 0 },
240 { 777, 0, 0, 0, 0 },
248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
249 …0299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
256 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
257 { 0x0, 0x0, 0x0, 0x0, 0x0 },
261 0xA,
263 0,
264 0x10,
265 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
266 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
267 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
274 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
275 0x5,
276 0xAFC8,
277 0x69,
278 0x32,
280 0,
281 0x10,
282 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
283 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
284 …{ 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x68…
290 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
291 { 0x0, 0x0, 0x0, 0x0, 0x0 },
295 0xA,
297 0,
298 0x10,
299 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
300 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
301 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
307 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
308 { 0x0, 0x0, 0x0, 0x0, 0x0 },
312 0xA,
314 0,
315 0x10,
316 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
317 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
318 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
324 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
325 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
326 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
327 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
328 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
329 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
330 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
331 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
332 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
333 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
334 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
335 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
336 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
337 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
338 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
339 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
340 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
341 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
342 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
343 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
344 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
345 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
346 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
347 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
348 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
349 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
350 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
351 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
352 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
353 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
354 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
355 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
356 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
357 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
358 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
359 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
360 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
361 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
362 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
363 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
364 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
365 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
366 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
367 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
368 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
369 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
370 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
371 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
372 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
373 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
375 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
377 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
378 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
379 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
380 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
381 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
382 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
383 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
384 { 0xFFFFFFFF }
388 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
389 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
390 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
391 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
392 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
393 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
394 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
395 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
396 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
397 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
398 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
399 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
400 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
401 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
402 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
403 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
404 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
405 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
406 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
407 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
408 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
409 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
410 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
411 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
412 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
413 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
414 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
415 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
416 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
417 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
418 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
419 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
420 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
421 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
422 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
423 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
424 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
425 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
426 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
427 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
428 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
429 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
430 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
431 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
432 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
433 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
434 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
435 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
436 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
437 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
438 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
439 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
440 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
441 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
442 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
443 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
444 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
445 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
446 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
447 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
448 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
449 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
450 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
451 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
452 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
453 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
454 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
455 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
456 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
457 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
458 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
459 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
460 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
461 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
462 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
463 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
464 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
465 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
466 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
467 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
468 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
469 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
470 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
471 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
472 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
473 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
474 { 0xFFFFFFFF }
478 { 0xFFFFFFFF }
484 0,
499 0,
500 0,
501 0,
502 0,
503 0,
504 0,
505 0,
506 0
512 { 0, 0, 0, 0, 0 },
513 { 0, 0, 0, 0, 0 },
514 0,
515 0,
516 0,
517 0,
518 0,
519 0,
520 0,
521 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
522 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
523 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
524 0,
529 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
530 { 0x0, 0x0, 0x0, 0x0, 0x0 },
534 0xA,
536 0,
537 0x10,
538 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
539 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
540 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
546 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
547 { 0x0, 0x0, 0x0, 0x0, 0x0 },
551 0xA,
553 0,
554 0x10,
555 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
556 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
557 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
563 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
564 { 0x0, 0x0, 0x0, 0x0, 0x0 },
568 0xA,
570 0,
571 0x10,
572 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
573 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
574 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
580 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
581 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
582 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
583 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
584 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
585 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
586 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
587 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
588 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
589 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
590 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
591 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
592 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
593 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
594 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
595 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
596 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
597 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
598 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
599 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
600 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
601 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
602 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
603 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
604 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
605 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
606 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
607 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
608 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
609 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
610 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
611 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
612 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
613 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
614 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
615 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
616 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
617 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
618 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
619 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
620 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
621 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
622 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
623 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
624 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
625 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
626 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
627 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
628 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
629 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
630 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
631 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
632 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
633 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
634 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
635 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
636 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
637 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
638 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
639 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
640 { 0xFFFFFFFF }
644 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
645 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
646 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
647 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
648 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
649 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
650 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
651 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
652 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
653 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
654 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
655 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
656 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
657 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
658 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
659 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
660 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
661 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
662 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
663 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
664 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
665 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
666 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
667 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
668 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
669 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
670 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
671 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
672 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
673 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
674 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
675 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
676 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
677 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
678 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
679 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
680 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
681 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
682 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
683 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
684 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
685 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
686 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
687 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
688 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
689 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
690 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
691 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
692 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
693 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
694 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
695 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
696 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
697 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
698 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
699 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
700 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
701 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
702 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
703 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
704 { 0xFFFFFFFF }
708 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
709 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
710 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
711 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
712 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
713 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
714 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
715 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
716 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
717 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
718 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
719 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
720 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
721 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
722 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
723 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
724 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
725 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
726 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
727 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
728 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
729 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
730 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
731 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
732 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
733 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
734 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
735 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
736 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
737 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
738 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
739 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
740 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
741 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
742 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
743 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
744 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
746 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
748 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
749 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
750 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
751 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
752 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
753 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
761 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
762 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
763 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
764 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
765 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
766 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
767 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
768 { 0xFFFFFFFF }
772 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
773 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
774 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
775 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
776 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
778 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
779 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
780 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
781 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
782 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
783 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
784 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
785 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
786 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
787 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
788 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
789 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
790 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
791 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
792 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
793 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
794 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
795 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
796 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
797 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
798 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
799 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
800 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
801 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
802 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
803 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
804 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
805 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
806 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
807 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
808 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
810 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
812 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
813 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
814 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
815 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
816 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
817 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
826 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
827 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
828 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
829 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
830 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
831 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
832 { 0xFFFFFFFF }
836 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
837 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
839 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
840 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
841 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
842 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
843 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
844 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
845 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
846 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
847 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
848 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
849 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
850 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
851 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
852 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
853 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
854 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
855 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
856 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
857 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
858 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
859 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
860 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
861 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
863 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
864 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
865 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
866 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
867 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
868 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
869 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
870 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
871 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
872 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
874 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
876 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
877 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
878 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
879 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
880 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
881 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
891 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
892 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
893 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
894 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
895 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
896 { 0xFFFFFFFF }
900 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
901 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
902 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
903 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
904 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
905 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
906 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
907 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
908 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
909 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
910 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
911 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
912 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
913 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
914 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
915 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
916 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
917 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
918 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
919 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
920 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
921 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
922 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
923 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
924 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
925 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
927 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
928 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
929 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
930 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
931 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
932 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
933 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
934 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
935 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
936 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
937 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
938 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
939 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
940 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
941 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
942 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
943 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
944 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
945 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
946 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
947 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
948 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
949 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
950 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
951 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
952 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
953 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
954 { 0xFFFFFFFF }
958 { 0xFFFFFFFF }
962 ((1 << 16) | 0x6993),
964 0,
968 0UL,
969 0UL,
979 0,
980 0,
981 0,
982 0,
983 0,
984 0,
985 0,
986 0
992 { 0, 0, 0, 0, 0 },
993 { 0, 0, 0, 0, 0 },
994 0,
995 0,
996 0,
997 0,
998 0,
999 0,
1000 0,
1001 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1002 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1003 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1004 0,
1009 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1010 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1013 0x69,
1014 0xA,
1016 0,
1017 0x3,
1018 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1019 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1020 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1026 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1027 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1030 0x69,
1031 0xA,
1033 0,
1034 0x3,
1035 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1036 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1037 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1043 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1044 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1047 0x69,
1048 0xA,
1050 0,
1051 0x3,
1052 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1053 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1054 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1061 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1062 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1063 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1064 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1065 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1066 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1067 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1068 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1069 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1070 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1071 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1072 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1073 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1074 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1075 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1076 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1077 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1078 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1079 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1080 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1081 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1082 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1083 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1084 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1085 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1086 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1087 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1088 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1089 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1090 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1091 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1092 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1093 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1094 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1095 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1096 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1097 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1098 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1099 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1100 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1101 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1102 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1103 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1104 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1105 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1106 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1107 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1108 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1109 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1110 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1111 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1112 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1113 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1114 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1115 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1116 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1117 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1118 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1119 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1120 { 0xFFFFFFFF }
1124 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1125 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1126 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1127 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1128 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1129 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1130 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1131 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1132 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1133 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1134 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1135 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1136 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1137 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1138 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1139 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1140 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1141 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1142 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1143 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1144 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1145 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1146 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1147 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1148 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1149 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1150 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1151 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1152 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1153 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1154 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1155 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1156 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1157 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1158 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1159 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1160 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1161 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1162 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1163 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1164 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1165 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1166 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1167 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1168 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1169 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1170 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1171 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1172 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1173 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1174 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1175 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1176 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1177 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1178 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1179 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1180 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1181 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1182 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1183 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1184 { 0xFFFFFFFF }
1188 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1189 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1190 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1191 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1192 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1193 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1194 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1195 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1196 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1197 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1198 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1199 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1200 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1201 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1202 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1203 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1204 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1205 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1206 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1207 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1208 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1209 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1210 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1211 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1212 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1213 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1214 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1215 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1216 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1217 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1218 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1219 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1220 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1221 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1222 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1223 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1224 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1225 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1226 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1227 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1228 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1229 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1231 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1233 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1236 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1248 { 0xFFFFFFFF }
1252 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1253 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1254 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1255 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1256 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1257 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1259 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1260 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1261 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1262 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1263 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1264 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1265 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1266 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1267 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1268 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1269 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1270 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1271 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1272 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1273 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1274 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1275 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1276 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1277 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1278 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1279 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1280 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1281 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1282 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1283 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1284 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1285 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1286 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1287 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1288 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1290 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1291 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1292 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1293 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1294 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1296 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1303 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1310 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1312 { 0xFFFFFFFF }
1316 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1317 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1318 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1319 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1320 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1321 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1322 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1323 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1324 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1325 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1326 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1327 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1328 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1329 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1330 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1331 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1332 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1333 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1334 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1335 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1336 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1337 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1338 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1339 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1340 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1341 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1342 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1343 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1344 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1345 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1346 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1347 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1348 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1349 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1350 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1351 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1352 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1353 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1354 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1355 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1356 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1357 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1358 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1359 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1361 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1367 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1368 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1374 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1375 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1376 { 0xFFFFFFFF }
1380 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1381 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1382 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1383 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1384 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1385 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1386 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1387 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1388 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1389 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1391 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1392 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1393 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1394 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1395 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1396 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1397 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1398 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1399 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1400 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1401 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1402 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1403 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1404 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1405 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1406 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1407 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1408 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1409 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1410 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1411 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1412 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1413 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1414 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1415 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1416 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1418 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1419 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1420 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1421 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1422 { 0xFFFFFFFF }
1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468 { 0xFFFFFFFF }
1472 { 0xFFFFFFFF }
1476 ((1 << 16) | 0x6993),
1478 0,
1482 0UL,
1483 0UL,
1493 0,
1494 0,
1495 0,
1496 0,
1497 0,
1498 0,
1499 0,
1500 0
1506 ((1 << 16) | 0x6993),
1508 0,
1512 0UL,
1513 0UL,
1523 0,
1524 0,
1525 0,
1526 0,
1527 0,
1528 0,
1529 0,
1530 0
1536 { 0, 0, 0, 0, 0 },
1537 { 0, 0, 0, 0, 0 },
1538 0,
1539 0,
1540 0,
1541 0,
1542 0,
1543 0,
1544 0,
1545 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1548 0,
1553 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1554 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1558 0xA,
1560 0,
1561 0x10,
1562 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1563 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
1564 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1570 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1571 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1575 0xA,
1577 0,
1578 0x10,
1579 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1580 … 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x98968…
1581 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1588 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1589 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1590 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1591 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1592 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1593 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1594 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1595 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1596 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1597 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1598 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1599 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1600 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1601 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1602 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1603 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1604 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1605 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1606 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1607 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1608 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1609 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1610 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1611 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1612 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1613 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1614 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1615 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1616 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1617 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1618 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1619 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1620 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1621 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1622 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1623 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1624 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1625 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1626 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1627 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1628 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1629 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1630 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1631 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1632 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1633 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1634 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1635 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1636 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1637 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1638 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1639 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1640 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1641 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1642 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1643 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1644 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1645 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1646 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1647 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1648 { 0xFFFFFFFF }
1652 ((1 << 16) | 0x6993),
1654 0,
1658 0UL,
1659 0UL,
1669 0,
1670 0,
1671 0,
1672 0,
1673 0,
1674 0,
1675 0,
1676 0
1783 if (p_limit2 != 0 && p_limit2 <= p_limit1) { in si_update_dte_from_pl2()
1786 for (i = 0; i < k; i++) { in si_update_dte_from_pl2()
1816 case 0x6798: in si_initialize_powertune_defaults()
1819 case 0x6799: in si_initialize_powertune_defaults()
1822 case 0x6790: in si_initialize_powertune_defaults()
1823 case 0x6791: in si_initialize_powertune_defaults()
1824 case 0x6792: in si_initialize_powertune_defaults()
1825 case 0x679E: in si_initialize_powertune_defaults()
1829 case 0x679B: in si_initialize_powertune_defaults()
1833 case 0x679A: in si_initialize_powertune_defaults()
1844 case 0x6810: in si_initialize_powertune_defaults()
1845 case 0x6818: in si_initialize_powertune_defaults()
1853 case 0x6819: in si_initialize_powertune_defaults()
1854 case 0x6811: in si_initialize_powertune_defaults()
1862 case 0x6800: in si_initialize_powertune_defaults()
1863 case 0x6806: in si_initialize_powertune_defaults()
1885 case 0x683B: in si_initialize_powertune_defaults()
1886 case 0x683F: in si_initialize_powertune_defaults()
1887 case 0x6829: in si_initialize_powertune_defaults()
1888 case 0x6835: in si_initialize_powertune_defaults()
1892 case 0x682C: in si_initialize_powertune_defaults()
1897 case 0x6825: in si_initialize_powertune_defaults()
1898 case 0x6827: in si_initialize_powertune_defaults()
1902 case 0x6824: in si_initialize_powertune_defaults()
1903 case 0x682D: in si_initialize_powertune_defaults()
1907 case 0x682F: in si_initialize_powertune_defaults()
1911 case 0x6820: in si_initialize_powertune_defaults()
1915 case 0x6821: in si_initialize_powertune_defaults()
1919 case 0x6823: in si_initialize_powertune_defaults()
1920 case 0x682B: in si_initialize_powertune_defaults()
1921 case 0x6822: in si_initialize_powertune_defaults()
1922 case 0x682A: in si_initialize_powertune_defaults()
1933 case 0x6601: in si_initialize_powertune_defaults()
1934 case 0x6621: in si_initialize_powertune_defaults()
1935 case 0x6603: in si_initialize_powertune_defaults()
1936 case 0x6605: in si_initialize_powertune_defaults()
1944 case 0x6600: in si_initialize_powertune_defaults()
1945 case 0x6606: in si_initialize_powertune_defaults()
1946 case 0x6620: in si_initialize_powertune_defaults()
1947 case 0x6604: in si_initialize_powertune_defaults()
1955 case 0x6611: in si_initialize_powertune_defaults()
1956 case 0x6613: in si_initialize_powertune_defaults()
1957 case 0x6608: in si_initialize_powertune_defaults()
1965 case 0x6610: in si_initialize_powertune_defaults()
2021 si_pi->dyn_powertune_data.l2_lta_window_size = 0; in si_initialize_powertune_defaults()
2022 si_pi->dyn_powertune_data.lts_truncate = 0; in si_initialize_powertune_defaults()
2042 if (xclk == 0) in si_calculate_cac_wintime()
2043 return 0; in si_calculate_cac_wintime()
2046 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); in si_calculate_cac_wintime()
2080 *near_tdp_limit = 0; in si_calculate_adjusted_tdp_limits()
2083 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) in si_calculate_adjusted_tdp_limits()
2085 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) in si_calculate_adjusted_tdp_limits()
2088 return 0; in si_calculate_adjusted_tdp_limits()
2106 if (scaling_factor == 0) in si_populate_smc_tdp_limits()
2109 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); in si_populate_smc_tdp_limits()
2137 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); in si_populate_smc_tdp_limits()
2142 papm_parm->PlatformPowerLimit = 0xffffffff; in si_populate_smc_tdp_limits()
2143 papm_parm->NearTDPLimitPAPM = 0xffffffff; in si_populate_smc_tdp_limits()
2153 return 0; in si_populate_smc_tdp_limits()
2167 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); in si_populate_smc_tdp_limits_2()
2185 return 0; in si_populate_smc_tdp_limits_2()
2197 if ((prev_vddc == 0) || (curr_vddc == 0)) in si_calculate_power_efficiency_ratio()
2198 return 0; in si_calculate_power_efficiency_ratio()
2204 if (pwr_efficiency_ratio > (u64)0xFFFF) in si_calculate_power_efficiency_ratio()
2205 return 0; in si_calculate_power_efficiency_ratio()
2242 return 0; in si_populate_power_containment_values()
2244 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2252 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2253 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2254 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2255 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2256 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2269 if ((max_ps_percent == 0) || in si_populate_power_containment_values()
2279 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2280 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2282 if (min_sclk == 0) in si_populate_power_containment_values()
2313 return 0; in si_populate_power_containment_values()
2326 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2332 if (rdev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2350 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
2351 sq_power_throttle = 0; in si_populate_sq_ramping_values()
2352 sq_power_throttle2 = 0; in si_populate_sq_ramping_values()
2370 return 0; in si_populate_sq_ramping_values()
2379 int ret = 0; in si_enable_power_containment()
2406 int ret = 0; in si_initialize_smc_dte_tables()
2417 return 0; in si_initialize_smc_dte_tables()
2419 if (dte_data->k <= 0) in si_initialize_smc_dte_tables()
2445 if (tdep_count > 0) in si_initialize_smc_dte_tables()
2448 for (i = 0; i < table_size; i++) { in si_initialize_smc_dte_tables()
2455 for (i = 0; i < (u32)tdep_count; i++) { in si_initialize_smc_dte_tables()
2481 *max = 0; in si_get_cac_std_voltage_max_min()
2482 *min = 0xFFFF; in si_get_cac_std_voltage_max_min()
2484 for (i = 0; i < table->count; i++) { in si_get_cac_std_voltage_max_min()
2496 if (v0_loadline > 0xFFFFUL) in si_get_cac_std_voltage_max_min()
2501 if ((*min > *max) || (*max == 0) || (*min == 0)) in si_get_cac_std_voltage_max_min()
2504 return 0; in si_get_cac_std_voltage_max_min()
2528 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { in si_init_dte_leakage_table()
2531 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { in si_init_dte_leakage_table()
2543 if (smc_leakage > 0xFFFF) in si_init_dte_leakage_table()
2544 smc_leakage = 0xFFFF; in si_init_dte_leakage_table()
2550 return 0; in si_init_dte_leakage_table()
2566 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { in si_init_simplified_leakage_table()
2578 if (smc_leakage > 0xFFFF) in si_init_simplified_leakage_table()
2579 smc_leakage = 0xFFFF; in si_init_simplified_leakage_table()
2581 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) in si_init_simplified_leakage_table()
2585 return 0; in si_init_simplified_leakage_table()
2596 int ret = 0; in si_initialize_smc_cac_tables()
2600 return 0; in si_initialize_smc_cac_tables()
2647 cac_tables->dc_cac = cpu_to_be32(0); in si_initialize_smc_cac_tables()
2669 return 0; in si_initialize_smc_cac_tables()
2676 u32 data = 0, offset; in si_program_cac_config_registers()
2681 while (config_regs->offset != 0xFFFFFFFF) { in si_program_cac_config_registers()
2708 return 0; in si_program_cac_config_registers()
2719 return 0; in si_initialize_hardware_cac_manager()
2731 return 0; in si_initialize_hardware_cac_manager()
2741 int ret = 0; in si_enable_smc_cac()
2789 u32 sclk = 0; in si_init_smc_spll_table()
2790 int ret = 0; in si_init_smc_spll_table()
2794 if (si_pi->spll_table_start == 0) in si_init_smc_spll_table()
2801 for (i = 0; i < 256; i++) { in si_init_smc_spll_table()
2811 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2855 u16 highest_leakage = 0; in si_get_lower_of_leakage_and_vce_voltage()
2859 for (i = 0; i < si_pi->leakage_voltage.count; i++){ in si_get_lower_of_leakage_and_vce_voltage()
2878 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2879 (table && (table->count == 0))) { in si_get_vce_clock_voltage()
2880 *voltage = 0; in si_get_vce_clock_voltage()
2881 return 0; in si_get_vce_clock_voltage()
2884 for (i = 0; i < table->count; i++) { in si_get_vce_clock_voltage()
2888 ret = 0; in si_get_vce_clock_voltage()
2910 u16 vddc, vddci, min_vce_voltage = 0; in si_apply_state_adjust_rules()
2912 u32 max_sclk = 0, max_mclk = 0; in si_apply_state_adjust_rules()
2916 if ((rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2917 (rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2918 (rdev->pdev->device == 0x6664) || in si_apply_state_adjust_rules()
2919 (rdev->pdev->device == 0x6665) || in si_apply_state_adjust_rules()
2920 (rdev->pdev->device == 0x6667)) { in si_apply_state_adjust_rules()
2923 if ((rdev->pdev->revision == 0xC3) || in si_apply_state_adjust_rules()
2924 (rdev->pdev->device == 0x6665)) { in si_apply_state_adjust_rules()
2929 if ((rdev->pdev->revision == 0xC7) || in si_apply_state_adjust_rules()
2930 (rdev->pdev->revision == 0x80) || in si_apply_state_adjust_rules()
2931 (rdev->pdev->revision == 0x81) || in si_apply_state_adjust_rules()
2932 (rdev->pdev->revision == 0x83) || in si_apply_state_adjust_rules()
2933 (rdev->pdev->revision == 0x87) || in si_apply_state_adjust_rules()
2934 (rdev->pdev->device == 0x6604) || in si_apply_state_adjust_rules()
2935 (rdev->pdev->device == 0x6605)) { in si_apply_state_adjust_rules()
2949 rps->evclk = 0; in si_apply_state_adjust_rules()
2950 rps->ecclk = 0; in si_apply_state_adjust_rules()
2967 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()
2972 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
2992 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3021 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3022 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3029 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3030 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3041 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3042 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3043 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3044 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3047 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3052 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3066 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3071 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3084 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3088 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3105 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3113 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3119 #if 0
3152 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); in si_is_special_1gb_platform()
3162 if ((rdev->pdev->device == 0x6819) && in si_is_special_1gb_platform()
3163 is_memory_gddr5 && is_special && (density == 0x400)) in si_is_special_1gb_platform()
3172 u16 vddc, count = 0; in si_get_leakage_vddc()
3175 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { in si_get_leakage_vddc()
3178 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { in si_get_leakage_vddc()
3197 if ((index & 0xff00) != 0xff00) in si_get_leakage_voltage_from_leakage_index()
3200 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) in si_get_leakage_voltage_from_leakage_index()
3206 for (i = 0; i < si_pi->leakage_voltage.count; i++) { in si_get_leakage_voltage_from_leakage_index()
3209 return 0; in si_get_leakage_voltage_from_leakage_index()
3222 case 0: in si_set_dpm_event_sources()
3244 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_set_dpm_event_sources()
3276 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in si_stop_dpm()
3282 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3288 #if 0
3294 if (thermal_level == 0) {
3297 return 0;
3301 return 0;
3310 #if 0
3315 0 : -EINVAL;
3317 return 0;
3334 0 : -EINVAL; in si_restrict_performance_levels_before_switch()
3351 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3357 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) in si_dpm_force_performance_level()
3366 return 0; in si_dpm_force_performance_level()
3369 #if 0
3373 0 : -EINVAL;
3380 0 : -EINVAL; in si_set_sw_state()
3389 0 : -EINVAL; in si_halt_smc()
3398 0 : -EINVAL; in si_resume_smc()
3529 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_enable_thermal_protection()
3539 #if 0
3546 return 0;
3557 for (i = 0; i < rdev->usec_timeout; i++) {
3563 return 0;
3574 0 : -EINVAL; in si_notify_smc_display_change()
3587 if (voltage_response_time == 0) in si_program_response_times()
3602 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); in si_program_response_times()
3608 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ in si_program_ds_registers()
3623 if (rdev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
3638 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
3641 for (i = 0; i < rdev->num_crtc; i++) { in si_program_display_gap()
3646 pipe = 0; in si_program_display_gap()
3659 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
3670 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in si_enable_spread_spectrum()
3671 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); in si_enable_spread_spectrum()
3709 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) in si_program_tp()
3713 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in si_program_tp()
3718 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in si_program_tp()
3757 WREG32(CG_FTV, 0); in si_clear_vc()
3765 mc_para_index = 0; in si_get_ddr3_mclk_frequency_ratio()
3767 mc_para_index = 0x0f; in si_get_ddr3_mclk_frequency_ratio()
3779 mc_para_index = 0x00; in si_get_mclk_frequency_ratio()
3781 mc_para_index = 0x0f; in si_get_mclk_frequency_ratio()
3786 mc_para_index = 0x00; in si_get_mclk_frequency_ratio()
3788 mc_para_index = 0x0f; in si_get_mclk_frequency_ratio()
3799 u8 result = 0; in si_get_strobe_mode_settings()
3841 if (num_bits == 0) in si_validate_phase_shedding_tables()
3866 for (i= 0; i < max_voltage_steps; i++) in si_trim_voltage_table_to_fit_state_table()
3881 voltage_table->mask_low = 0; in si_get_svi2_voltage_table()
3882 voltage_table->phase_delay = 0; in si_get_svi2_voltage_table()
3885 for (i = 0; i < voltage_table->count; i++) { in si_get_svi2_voltage_table()
3887 voltage_table->entries[i].smio_low = 0; in si_get_svi2_voltage_table()
3890 return 0; in si_get_svi2_voltage_table()
3948 if (si_pi->mvdd_voltage_table.count == 0) { in si_construct_voltage_tables()
3965 if ((si_pi->vddc_phase_shed_table.count == 0) || in si_construct_voltage_tables()
3970 return 0; in si_construct_voltage_tables()
3979 for (i = 0; i < voltage_table->count; i++) in si_populate_smc_voltage_table()
4004 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { in si_populate_smc_voltage_tables()
4043 return 0; in si_populate_smc_voltage_tables()
4052 for (i = 0; i < table->count; i++) { in si_populate_voltage_value()
4063 return 0; in si_populate_voltage_value()
4074 voltage->index = 0; in si_populate_mvdd_value()
4080 return 0; in si_populate_mvdd_value()
4096 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4111 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4131 return 0; in si_get_std_voltage_value()
4141 return 0; in si_populate_std_voltage_value()
4151 for (i = 0; i < limits->count; i++) { in si_populate_phase_shedding_value()
4160 return 0; in si_populate_phase_shedding_value()
4173 tmp &= 0x00FFFFFF; in si_init_arb_table_index()
4187 0 : -EINVAL; in si_reset_to_default()
4201 tmp = (tmp >> 24) & 0xff; in si_force_switch_to_arb_f0()
4204 return 0; in si_force_switch_to_arb_f0()
4222 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); in si_calculate_memory_refresh_rate()
4251 return 0; in si_populate_memory_timing_parameters()
4260 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; in si_do_program_memory_timing_parameters()
4261 int i, ret = 0; in si_do_program_memory_timing_parameters()
4263 for (i = 0; i < state->performance_level_count; i++) { in si_do_program_memory_timing_parameters()
4298 return 0; in si_populate_initial_mvdd_value()
4332 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4348 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4353 table->initialState.level.ACIndex = 0; in si_populate_smc_initial_state()
4356 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4374 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4380 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4381 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4382 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4387 reg = CG_R(0xffff) | CG_L(0); in si_populate_smc_initial_state()
4397 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4399 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4402 table->initialState.level.mcFlags = 0; in si_populate_smc_initial_state()
4409 table->initialState.level.dpm2.MaxPS = 0; in si_populate_smc_initial_state()
4410 table->initialState.level.dpm2.NearTDPDec = 0; in si_populate_smc_initial_state()
4411 table->initialState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_initial_state()
4412 table->initialState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_initial_state()
4413 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_initial_state()
4421 return 0; in si_populate_smc_initial_state()
4467 0, in si_populate_smc_acpi_state()
4468 0, in si_populate_smc_acpi_state()
4494 0, in si_populate_smc_acpi_state()
4495 0, in si_populate_smc_acpi_state()
4542 table->ACPIState.level.mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4543 table->ACPIState.level.sclk.sclk_value = 0; in si_populate_smc_acpi_state()
4545 si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd); in si_populate_smc_acpi_state()
4548 table->ACPIState.level.ACIndex = 0; in si_populate_smc_acpi_state()
4550 table->ACPIState.level.dpm2.MaxPS = 0; in si_populate_smc_acpi_state()
4551 table->ACPIState.level.dpm2.NearTDPDec = 0; in si_populate_smc_acpi_state()
4552 table->ACPIState.level.dpm2.AboveSafeInc = 0; in si_populate_smc_acpi_state()
4553 table->ACPIState.level.dpm2.BelowSafeInc = 0; in si_populate_smc_acpi_state()
4554 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; in si_populate_smc_acpi_state()
4562 return 0; in si_populate_smc_acpi_state()
4600 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; in si_program_ulv_memory_timing_parameters()
4659 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) in si_init_smc_table()
4689 table->driverState.levels[0] = table->initialState.level; in si_init_smc_table()
4786 return 0; in si_calculate_sclk_params()
4896 return 0; in si_populate_mclk_value()
4907 for (i = 0; i < ps->performance_level_count - 1; i++) in si_populate_smc_sp()
4936 level->mcFlags = 0; in si_convert_power_level_to_smc()
4960 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) in si_convert_power_level_to_smc()
4961 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in si_convert_power_level_to_smc()
4963 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; in si_convert_power_level_to_smc()
4971 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; in si_convert_power_level_to_smc()
4978 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); in si_convert_power_level_to_smc()
5038 a_t = CG_R(0xffff) | CG_L(0); in si_populate_smc_t()
5039 smc_state->levels[0].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5040 return 0; in si_populate_smc_t()
5043 smc_state->levels[0].aT = cpu_to_be32(0); in si_populate_smc_t()
5045 for (i = 0; i <= state->performance_level_count - 2; i++) { in si_populate_smc_t()
5065 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); in si_populate_smc_t()
5069 return 0; in si_populate_smc_t()
5079 0 : -EINVAL; in si_disable_ulv()
5081 return 0; in si_disable_ulv()
5092 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5097 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5106 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) in si_is_state_ulv_compatible()
5121 0 : -EINVAL; in si_set_power_state_conditionally_enable_ulv()
5123 return 0; in si_set_power_state_conditionally_enable_ulv()
5154 smc_state->levelCount = 0; in si_convert_power_state_to_smc()
5155 for (i = 0; i < state->performance_level_count; i++) { in si_convert_power_state_to_smc()
5157 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { in si_convert_power_state_to_smc()
5184 smc_state->levels[i].ACIndex = 0; in si_convert_power_state_to_smc()
5218 memset(smc_state, 0, state_size); in si_upload_sw_state()
5234 int ret = 0; in si_upload_ulv_state()
5242 memset(smc_state, 0, state_size); in si_upload_ulv_state()
5258 if (rdev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5259 return 0; in si_upload_smc_data()
5261 for (i = 0; i < rdev->num_crtc; i++) { in si_upload_smc_data()
5269 return 0; in si_upload_smc_data()
5271 if (radeon_crtc->line_time <= 0) in si_upload_smc_data()
5272 return 0; in si_upload_smc_data()
5277 return 0; in si_upload_smc_data()
5282 return 0; in si_upload_smc_data()
5287 return 0; in si_upload_smc_data()
5289 return 0; in si_upload_smc_data()
5299 for (i = 0, j = table->last; i < table->last; i++) { in si_set_mc_special_registers()
5307 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5309 ((temp_reg & 0xffff0000)) | in si_set_mc_special_registers()
5310 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in si_set_mc_special_registers()
5318 for (k = 0; k < table->num_entries; k++) { in si_set_mc_special_registers()
5320 (temp_reg & 0xffff0000) | in si_set_mc_special_registers()
5321 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5323 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in si_set_mc_special_registers()
5332 for (k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5334 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in si_set_mc_special_registers()
5344 for(k = 0; k < table->num_entries; k++) in si_set_mc_special_registers()
5346 (temp_reg & 0xffff0000) | in si_set_mc_special_registers()
5347 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in si_set_mc_special_registers()
5359 return 0; in si_set_mc_special_registers()
5421 for (i = 0; i < table->last; i++) { in si_set_valid_flag()
5436 for (i = 0; i < table->last; i++) in si_set_s0_mc_reg_index()
5452 for (i = 0; i < table->last; i++) in si_copy_vbios_mc_reg_table()
5456 for (i = 0; i < table->num_entries; i++) { in si_copy_vbios_mc_reg_table()
5459 for (j = 0; j < table->last; j++) { in si_copy_vbios_mc_reg_table()
5466 return 0; in si_copy_vbios_mc_reg_table()
5525 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { in si_populate_mc_reg_addresses()
5545 for(i = 0, j = 0; j < num_entries; j++) { in si_convert_mc_registers()
5558 u32 i = 0; in si_convert_mc_reg_table_entry_to_smc()
5560 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { in si_convert_mc_reg_table_entry_to_smc()
5565 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) in si_convert_mc_reg_table_entry_to_smc()
5580 for (i = 0; i < state->performance_level_count; i++) { in si_convert_mc_reg_table_to_smc()
5595 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); in si_populate_mc_reg_table()
5601 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
5604 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
5609 if (ulv->supported && ulv->pl.vddc != 0) in si_populate_mc_reg_table()
5613 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
5635 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); in si_upload_mc_reg_table()
5652 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); in si_enable_voltage_control()
5660 u16 pcie_speed, max_speed = 0; in si_get_maximum_link_speed()
5662 for (i = 0; i < state->performance_level_count; i++) { in si_get_maximum_link_speed()
5699 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in si_request_link_speed_change_before_state_change()
5706 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in si_request_link_speed_change_before_state_change()
5737 (si_get_current_pcie_speed(rdev) > 0)) in si_notify_link_speed_change_after_state_change()
5746 #if 0
5756 0 : -EINVAL;
5759 PPSMC_Result_OK) ? 0 : -EINVAL;
5761 return 0;
5771 case 0x6820: in si_set_max_cu_value()
5772 case 0x6825: in si_set_max_cu_value()
5773 case 0x6821: in si_set_max_cu_value()
5774 case 0x6823: in si_set_max_cu_value()
5775 case 0x6827: in si_set_max_cu_value()
5778 case 0x682D: in si_set_max_cu_value()
5779 case 0x6824: in si_set_max_cu_value()
5780 case 0x682F: in si_set_max_cu_value()
5781 case 0x6826: in si_set_max_cu_value()
5784 case 0x6828: in si_set_max_cu_value()
5785 case 0x6830: in si_set_max_cu_value()
5786 case 0x6831: in si_set_max_cu_value()
5787 case 0x6838: in si_set_max_cu_value()
5788 case 0x6839: in si_set_max_cu_value()
5789 case 0x683D: in si_set_max_cu_value()
5792 case 0x683B: in si_set_max_cu_value()
5793 case 0x683F: in si_set_max_cu_value()
5794 case 0x6829: in si_set_max_cu_value()
5798 si_pi->max_cu = 0; in si_set_max_cu_value()
5802 si_pi->max_cu = 0; in si_set_max_cu_value()
5814 for (i = 0; i < table->count; i++) { in si_patch_single_dependency_table_based_on_leakage()
5818 case 0: in si_patch_single_dependency_table_based_on_leakage()
5829 for (j = (table->count - 2); j >= 0; j--) { in si_patch_single_dependency_table_based_on_leakage()
5834 return 0; in si_patch_single_dependency_table_based_on_leakage()
5916 return 0; in si_thermal_enable_alert()
5922 int low_temp = 0 * 1000; in si_thermal_set_temperature_range()
5941 return 0; in si_thermal_set_temperature_range()
5958 tmp |= TMIN(0); in si_fan_ctrl_set_static_mode()
5979 return 0; in si_thermal_setup_fan_table()
5984 if (duty100 == 0) { in si_thermal_setup_fan_table()
5986 return 0; in si_thermal_setup_fan_table()
6040 return 0; in si_thermal_setup_fan_table()
6051 return 0; in si_fan_ctrl_start_smc_fan_control()
6066 return 0; in si_fan_ctrl_stop_smc_fan_control()
6084 if (duty100 == 0) in si_fan_ctrl_get_fan_speed_percent()
6094 return 0; in si_fan_ctrl_get_fan_speed_percent()
6116 if (duty100 == 0) in si_fan_ctrl_set_fan_speed_percent()
6127 return 0; in si_fan_ctrl_set_fan_speed_percent()
6152 return 0; in si_fan_ctrl_get_mode()
6158 #if 0
6168 if (rdev->pm.fan_pulses_per_revolution == 0)
6172 if (tach_period == 0)
6177 return 0;
6189 if (rdev->pm.fan_pulses_per_revolution == 0)
6206 return 0;
6246 tmp |= TACH_PWM_RESP_RATE(0x28); in si_thermal_initialize()
6274 return 0; in si_thermal_start_thermal_controller()
6401 return 0; in si_dpm_enable()
6466 return 0; in si_dpm_pre_set_power_state()
6492 return 0; in si_power_control_set_level()
6595 return 0; in si_dpm_set_power_state()
6606 #if 0
6658 rps->vclk = 0; in si_parse_pplib_non_clock_info()
6659 rps->dclk = 0; in si_parse_pplib_non_clock_info()
6698 if (ret == 0) in si_parse_pplib_clock_info()
6708 index == 0) { in si_parse_pplib_clock_info()
6782 for (i = 0; i < state_array->ucNumEntries; i++) { in si_parse_power_table()
6799 k = 0; in si_parse_power_table()
6800 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; in si_parse_power_table()
6801 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()
6808 ((u8 *)&clock_info_array->clockInfo[0] + in si_parse_power_table()
6820 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { in si_parse_power_table()
6833 return 0; in si_parse_power_table()
6858 si_pi->sys_pcie_mask = 0; in si_dpm_init()
6879 pi->acpi_vddc = 0; in si_dpm_init()
6880 eg_pi->acpi_vddci = 0; in si_dpm_init()
6881 pi->min_vddc_in_table = 0; in si_dpm_init()
6882 pi->max_vddc_in_table = 0; in si_dpm_init()
6905 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
6906 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
6914 if (rdev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
6916 if (rdev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
6920 0, false, ÷rs); in si_dpm_init()
6930 pi->mclk_stutter_mode_threshold = 0; in si_dpm_init()
6997 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
6999 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7005 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7006 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7012 return 0; in si_dpm_init()
7019 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in si_dpm_fini()
7060 return 0; in si_dpm_get_current_sclk()
7078 return 0; in si_dpm_get_current_mclk()