Lines Matching refs:gb_addr_config
3071 u32 gb_addr_config = 0; in si_gpu_init() local
3094 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3111 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3129 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3146 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3163 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in si_gpu_init()
3199 gb_addr_config &= ~ROW_SIZE_MASK; in si_gpu_init()
3203 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3206 gb_addr_config |= ROW_SIZE(1); in si_gpu_init()
3209 gb_addr_config |= ROW_SIZE(2); in si_gpu_init()
3250 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in si_gpu_init()
3252 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; in si_gpu_init()
3254 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3255 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3256 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
3257 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3258 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3259 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3261 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3262 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3263 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in si_gpu_init()