2501 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2510 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2519 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2528 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2537 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2546 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2555 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2564 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2573 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2582 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2591 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2600 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2609 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2618 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2627 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2636 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2645 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2654 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2663 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2672 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2681 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2690 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2699 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2716 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2725 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2734 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2743 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2752 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2761 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2770 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2779 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2788 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2797 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2806 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2815 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2824 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2833 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2842 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2851 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2860 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2869 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2878 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |  in si_tiling_mode_table_init()
2887 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2896 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2905 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2914 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()