Lines Matching +full:clkf +full:- +full:- +full:-
51 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
82 if (!pi->boot_in_gen2) { in rv770_enable_bif_dynamic_pcie_gen2()
152 if (rdev->family == CHIP_RV770) in rv770_mg_clock_gating_enable()
160 if (pi->mgcgtssm) in rv770_mg_clock_gating_enable()
231 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ? in rv770_get_seq_value()
242 pi->soft_regs_start + reg_offset,
243 value, pi->sram_end);
253 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
254 value, pi->sram_end); in rv770_write_smc_soft_register()
273 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
276 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
278 l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d); in rv770_populate_smc_t()
279 r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d); in rv770_populate_smc_t()
281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
282 (R600_AH_DFLT - pi->rmp); in rv770_populate_smc_t()
283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
284 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
286 l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d); in rv770_populate_smc_t()
287 r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d); in rv770_populate_smc_t()
289 for (i = 0; i < (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1); i++) { in rv770_populate_smc_t()
290 a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200); in rv770_populate_smc_t()
291 smc_state->levels[i].aT = cpu_to_be32(a_t); in rv770_populate_smc_t()
294 a_t = CG_R(r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200) | in rv770_populate_smc_t()
295 CG_L(l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200); in rv770_populate_smc_t()
297 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = in rv770_populate_smc_t()
310 for (i = 0; i < (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1); i++) in rv770_populate_smc_sp()
311 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_sp()
313 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = in rv770_populate_smc_sp()
314 cpu_to_be32(pi->psp); in rv770_populate_smc_sp()
323 u32 *clkf, in rv770_calculate_fractional_mpll_feedback_divider() argument
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
340 *clkf = feedback_divider8 / 8; in rv770_calculate_fractional_mpll_feedback_divider()
365 ret = -EINVAL; in rv770_encode_yclk_post_div()
372 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) in rv770_map_clkf_to_ibias() argument
374 if (clkf <= 0x10) in rv770_map_clkf_to_ibias()
376 if (clkf <= 0x19) in rv770_map_clkf_to_ibias()
378 if (clkf <= 0x21) in rv770_map_clkf_to_ibias()
380 if (clkf <= 0x27) in rv770_map_clkf_to_ibias()
382 if (clkf <= 0x31) in rv770_map_clkf_to_ibias()
394 pi->clk_regs.rv770.mpll_ad_func_cntl; in rv770_populate_mclk_value()
396 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv770_populate_mclk_value()
398 pi->clk_regs.rv770.mpll_dq_func_cntl; in rv770_populate_mclk_value()
400 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv770_populate_mclk_value()
402 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in rv770_populate_mclk_value()
403 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; in rv770_populate_mclk_value()
405 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv770_populate_mclk_value()
406 u32 clkf, clkfrac; in rv770_populate_mclk_value() local
417 return -EINVAL; in rv770_populate_mclk_value()
420 pi->mem_gddr5, in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
427 ibias = rv770_map_clkf_to_ibias(rdev, clkf); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
436 mpll_ad_func_cntl |= CLKF(clkf); in rv770_populate_mclk_value()
445 if (pi->mem_gddr5) { in rv770_populate_mclk_value()
448 pi->mem_gddr5, in rv770_populate_mclk_value()
449 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
451 ibias = rv770_map_clkf_to_ibias(rdev, clkf); in rv770_populate_mclk_value()
462 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
464 mpll_dq_func_cntl |= CLKF(clkf); in rv770_populate_mclk_value()
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
475 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_mclk_value()
476 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_mclk_value()
477 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_mclk_value()
478 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_mclk_value()
479 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_mclk_value()
480 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_mclk_value()
492 pi->clk_regs.rv770.cg_spll_func_cntl; in rv770_populate_sclk_value()
494 pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv770_populate_sclk_value()
496 pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv770_populate_sclk_value()
498 pi->clk_regs.rv770.cg_spll_spread_spectrum; in rv770_populate_sclk_value()
500 pi->clk_regs.rv770.cg_spll_spread_spectrum_2; in rv770_populate_sclk_value()
502 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
539 if (pi->sclk_ss) { in rv770_populate_sclk_value()
557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
558 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
559 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv770_populate_sclk_value()
560 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv770_populate_sclk_value()
561 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv770_populate_sclk_value()
562 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv770_populate_sclk_value()
573 if (!pi->voltage_control) { in rv770_populate_vddc_value()
574 voltage->index = 0; in rv770_populate_vddc_value()
575 voltage->value = 0; in rv770_populate_vddc_value()
579 for (i = 0; i < pi->valid_vddc_entries; i++) { in rv770_populate_vddc_value()
580 if (vddc <= pi->vddc_table[i].vddc) { in rv770_populate_vddc_value()
581 voltage->index = pi->vddc_table[i].vddc_index; in rv770_populate_vddc_value()
582 voltage->value = cpu_to_be16(vddc); in rv770_populate_vddc_value()
587 if (i == pi->valid_vddc_entries) in rv770_populate_vddc_value()
588 return -EINVAL; in rv770_populate_vddc_value()
598 if (!pi->mvdd_control) { in rv770_populate_mvdd_value()
599 voltage->index = MVDD_HIGH_INDEX; in rv770_populate_mvdd_value()
600 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in rv770_populate_mvdd_value()
604 if (mclk <= pi->mvdd_split_frequency) { in rv770_populate_mvdd_value()
605 voltage->index = MVDD_LOW_INDEX; in rv770_populate_mvdd_value()
606 voltage->value = cpu_to_be16(MVDD_LOW_VALUE); in rv770_populate_mvdd_value()
608 voltage->index = MVDD_HIGH_INDEX; in rv770_populate_mvdd_value()
609 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in rv770_populate_mvdd_value()
623 level->gen2PCIE = pi->pcie_gen2 ? in rv770_convert_power_level_to_smc()
624 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0; in rv770_convert_power_level_to_smc()
625 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0; in rv770_convert_power_level_to_smc()
626 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0; in rv770_convert_power_level_to_smc()
627 level->displayWatermark = watermark_level; in rv770_convert_power_level_to_smc()
629 if (rdev->family == CHIP_RV740) in rv770_convert_power_level_to_smc()
630 ret = rv740_populate_sclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
631 &level->sclk); in rv770_convert_power_level_to_smc()
632 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_convert_power_level_to_smc()
633 ret = rv730_populate_sclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
634 &level->sclk); in rv770_convert_power_level_to_smc()
636 ret = rv770_populate_sclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
637 &level->sclk); in rv770_convert_power_level_to_smc()
641 if (rdev->family == CHIP_RV740) { in rv770_convert_power_level_to_smc()
642 if (pi->mem_gddr5) { in rv770_convert_power_level_to_smc()
643 if (pl->mclk <= pi->mclk_strobe_mode_threshold) in rv770_convert_power_level_to_smc()
644 level->strobeMode = in rv770_convert_power_level_to_smc()
645 rv740_get_mclk_frequency_ratio(pl->mclk) | 0x10; in rv770_convert_power_level_to_smc()
647 level->strobeMode = 0; in rv770_convert_power_level_to_smc()
649 if (pl->mclk > pi->mclk_edc_enable_threshold) in rv770_convert_power_level_to_smc()
650 level->mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG; in rv770_convert_power_level_to_smc()
652 level->mcFlags = 0; in rv770_convert_power_level_to_smc()
654 ret = rv740_populate_mclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
655 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
656 } else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_convert_power_level_to_smc()
657 ret = rv730_populate_mclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
658 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
660 ret = rv770_populate_mclk_value(rdev, pl->sclk, in rv770_convert_power_level_to_smc()
661 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
665 ret = rv770_populate_vddc_value(rdev, pl->vddc, in rv770_convert_power_level_to_smc()
666 &level->vddc); in rv770_convert_power_level_to_smc()
670 ret = rv770_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in rv770_convert_power_level_to_smc()
682 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC)) in rv770_convert_power_state_to_smc()
683 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in rv770_convert_power_state_to_smc()
686 &state->low, in rv770_convert_power_state_to_smc()
687 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
693 &state->medium, in rv770_convert_power_state_to_smc()
694 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
700 &state->high, in rv770_convert_power_state_to_smc()
701 &smc_state->levels[2], in rv770_convert_power_state_to_smc()
706 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in rv770_convert_power_state_to_smc()
707 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in rv770_convert_power_state_to_smc()
708 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in rv770_convert_power_state_to_smc()
710 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev, in rv770_convert_power_state_to_smc()
711 &state->low); in rv770_convert_power_state_to_smc()
712 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev, in rv770_convert_power_state_to_smc()
713 &state->medium); in rv770_convert_power_state_to_smc()
714 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev, in rv770_convert_power_state_to_smc()
715 &state->high); in rv770_convert_power_state_to_smc()
735 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
749 if (state->high.sclk < (state->low.sclk * 0xFF / 0x40)) in rv770_program_memory_timing_parameters()
750 high_clock = state->high.sclk; in rv770_program_memory_timing_parameters()
752 high_clock = (state->low.sclk * 0xFF / 0x40); in rv770_program_memory_timing_parameters()
755 state->high.mclk); in rv770_program_memory_timing_parameters()
758 STATE0(64 * high_clock / pi->boot_sclk) | in rv770_program_memory_timing_parameters()
759 STATE1(64 * high_clock / state->low.sclk) | in rv770_program_memory_timing_parameters()
760 STATE2(64 * high_clock / state->medium.sclk) | in rv770_program_memory_timing_parameters()
761 STATE3(64 * high_clock / state->high.sclk); in rv770_program_memory_timing_parameters()
765 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) | in rv770_program_memory_timing_parameters()
766 POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | in rv770_program_memory_timing_parameters()
767 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | in rv770_program_memory_timing_parameters()
768 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)); in rv770_program_memory_timing_parameters()
787 if (pi->sclk_ss) in rv770_enable_spread_spectrum()
790 if (pi->mclk_ss) { in rv770_enable_spread_spectrum()
791 if (rdev->family == CHIP_RV740) in rv770_enable_spread_spectrum()
801 if (rdev->family == CHIP_RV740) in rv770_enable_spread_spectrum()
810 if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) { in rv770_program_mpll_timing_parameters()
812 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) | in rv770_program_mpll_timing_parameters()
822 r600_calculate_u_and_p(pi->asi, in rv770_setup_bsp()
825 &pi->bsp, in rv770_setup_bsp()
826 &pi->bsu); in rv770_setup_bsp()
828 r600_calculate_u_and_p(pi->pasi, in rv770_setup_bsp()
831 &pi->pbsp, in rv770_setup_bsp()
832 &pi->pbsu); in rv770_setup_bsp()
834 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in rv770_setup_bsp()
835 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in rv770_setup_bsp()
837 WREG32(CG_BSP, pi->dsp); in rv770_setup_bsp()
893 WREG32(CG_FTV, pi->vrc); in rv770_program_vc()
909 ret = rv770_load_smc_ucode(rdev, pi->sram_end); in rv770_upload_firmware()
922 pi->clk_regs.rv770.mpll_ad_func_cntl; in rv770_populate_smc_acpi_state()
924 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in rv770_populate_smc_acpi_state()
926 pi->clk_regs.rv770.mpll_dq_func_cntl; in rv770_populate_smc_acpi_state()
928 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in rv770_populate_smc_acpi_state()
930 pi->clk_regs.rv770.cg_spll_func_cntl; in rv770_populate_smc_acpi_state()
932 pi->clk_regs.rv770.cg_spll_func_cntl_2; in rv770_populate_smc_acpi_state()
934 pi->clk_regs.rv770.cg_spll_func_cntl_3; in rv770_populate_smc_acpi_state()
938 table->ACPIState = table->initialState; in rv770_populate_smc_acpi_state()
940 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; in rv770_populate_smc_acpi_state()
942 if (pi->acpi_vddc) { in rv770_populate_smc_acpi_state()
943 rv770_populate_vddc_value(rdev, pi->acpi_vddc, in rv770_populate_smc_acpi_state()
944 &table->ACPIState.levels[0].vddc); in rv770_populate_smc_acpi_state()
945 if (pi->pcie_gen2) { in rv770_populate_smc_acpi_state()
946 if (pi->acpi_pcie_gen2) in rv770_populate_smc_acpi_state()
947 table->ACPIState.levels[0].gen2PCIE = 1; in rv770_populate_smc_acpi_state()
949 table->ACPIState.levels[0].gen2PCIE = 0; in rv770_populate_smc_acpi_state()
951 table->ACPIState.levels[0].gen2PCIE = 0; in rv770_populate_smc_acpi_state()
952 if (pi->acpi_pcie_gen2) in rv770_populate_smc_acpi_state()
953 table->ACPIState.levels[0].gen2XSP = 1; in rv770_populate_smc_acpi_state()
955 table->ACPIState.levels[0].gen2XSP = 0; in rv770_populate_smc_acpi_state()
957 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, in rv770_populate_smc_acpi_state()
958 &table->ACPIState.levels[0].vddc); in rv770_populate_smc_acpi_state()
959 table->ACPIState.levels[0].gen2PCIE = 0; in rv770_populate_smc_acpi_state()
983 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv770_populate_smc_acpi_state()
984 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv770_populate_smc_acpi_state()
985 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv770_populate_smc_acpi_state()
986 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv770_populate_smc_acpi_state()
988 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv770_populate_smc_acpi_state()
989 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv770_populate_smc_acpi_state()
991 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; in rv770_populate_smc_acpi_state()
993 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_smc_acpi_state()
994 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv770_populate_smc_acpi_state()
995 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv770_populate_smc_acpi_state()
997 table->ACPIState.levels[0].sclk.sclk_value = 0; in rv770_populate_smc_acpi_state()
999 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); in rv770_populate_smc_acpi_state()
1001 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in rv770_populate_smc_acpi_state()
1002 table->ACPIState.levels[2] = table->ACPIState.levels[0]; in rv770_populate_smc_acpi_state()
1012 if ((pi->s0_vid_lower_smio_cntl & pi->mvdd_mask_low) == in rv770_populate_initial_mvdd_value()
1013 (pi->mvdd_low_smio[MVDD_LOW_INDEX] & pi->mvdd_mask_low)) { in rv770_populate_initial_mvdd_value()
1014 voltage->index = MVDD_LOW_INDEX; in rv770_populate_initial_mvdd_value()
1015 voltage->value = cpu_to_be16(MVDD_LOW_VALUE); in rv770_populate_initial_mvdd_value()
1017 voltage->index = MVDD_HIGH_INDEX; in rv770_populate_initial_mvdd_value()
1018 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in rv770_populate_initial_mvdd_value()
1032 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = in rv770_populate_smc_initial_state()
1033 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); in rv770_populate_smc_initial_state()
1034 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = in rv770_populate_smc_initial_state()
1035 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); in rv770_populate_smc_initial_state()
1036 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = in rv770_populate_smc_initial_state()
1037 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl); in rv770_populate_smc_initial_state()
1038 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = in rv770_populate_smc_initial_state()
1039 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2); in rv770_populate_smc_initial_state()
1040 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = in rv770_populate_smc_initial_state()
1041 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl); in rv770_populate_smc_initial_state()
1042 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL = in rv770_populate_smc_initial_state()
1043 cpu_to_be32(pi->clk_regs.rv770.dll_cntl); in rv770_populate_smc_initial_state()
1045 table->initialState.levels[0].mclk.mclk770.vMPLL_SS = in rv770_populate_smc_initial_state()
1046 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1); in rv770_populate_smc_initial_state()
1047 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 = in rv770_populate_smc_initial_state()
1048 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2); in rv770_populate_smc_initial_state()
1050 table->initialState.levels[0].mclk.mclk770.mclk_value = in rv770_populate_smc_initial_state()
1051 cpu_to_be32(initial_state->low.mclk); in rv770_populate_smc_initial_state()
1053 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in rv770_populate_smc_initial_state()
1054 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl); in rv770_populate_smc_initial_state()
1055 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in rv770_populate_smc_initial_state()
1056 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2); in rv770_populate_smc_initial_state()
1057 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in rv770_populate_smc_initial_state()
1058 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3); in rv770_populate_smc_initial_state()
1059 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = in rv770_populate_smc_initial_state()
1060 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum); in rv770_populate_smc_initial_state()
1061 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in rv770_populate_smc_initial_state()
1062 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2); in rv770_populate_smc_initial_state()
1064 table->initialState.levels[0].sclk.sclk_value = in rv770_populate_smc_initial_state()
1065 cpu_to_be32(initial_state->low.sclk); in rv770_populate_smc_initial_state()
1067 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; in rv770_populate_smc_initial_state()
1069 table->initialState.levels[0].seqValue = in rv770_populate_smc_initial_state()
1070 rv770_get_seq_value(rdev, &initial_state->low); in rv770_populate_smc_initial_state()
1073 initial_state->low.vddc, in rv770_populate_smc_initial_state()
1074 &table->initialState.levels[0].vddc); in rv770_populate_smc_initial_state()
1076 &table->initialState.levels[0].mvdd); in rv770_populate_smc_initial_state()
1079 table->initialState.levels[0].aT = cpu_to_be32(a_t); in rv770_populate_smc_initial_state()
1081 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_initial_state()
1083 if (pi->boot_in_gen2) in rv770_populate_smc_initial_state()
1084 table->initialState.levels[0].gen2PCIE = 1; in rv770_populate_smc_initial_state()
1086 table->initialState.levels[0].gen2PCIE = 0; in rv770_populate_smc_initial_state()
1087 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv770_populate_smc_initial_state()
1088 table->initialState.levels[0].gen2XSP = 1; in rv770_populate_smc_initial_state()
1090 table->initialState.levels[0].gen2XSP = 0; in rv770_populate_smc_initial_state()
1092 if (rdev->family == CHIP_RV740) { in rv770_populate_smc_initial_state()
1093 if (pi->mem_gddr5) { in rv770_populate_smc_initial_state()
1094 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) in rv770_populate_smc_initial_state()
1095 table->initialState.levels[0].strobeMode = in rv770_populate_smc_initial_state()
1096 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; in rv770_populate_smc_initial_state()
1098 table->initialState.levels[0].strobeMode = 0; in rv770_populate_smc_initial_state()
1100 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) in rv770_populate_smc_initial_state()
1101 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG; in rv770_populate_smc_initial_state()
1103 table->initialState.levels[0].mcFlags = 0; in rv770_populate_smc_initial_state()
1107 table->initialState.levels[1] = table->initialState.levels[0]; in rv770_populate_smc_initial_state()
1108 table->initialState.levels[2] = table->initialState.levels[0]; in rv770_populate_smc_initial_state()
1110 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; in rv770_populate_smc_initial_state()
1121 for (i = 0; i < pi->valid_vddc_entries; i++) { in rv770_populate_smc_vddc_table()
1122 table->highSMIO[pi->vddc_table[i].vddc_index] = in rv770_populate_smc_vddc_table()
1123 pi->vddc_table[i].high_smio; in rv770_populate_smc_vddc_table()
1124 table->lowSMIO[pi->vddc_table[i].vddc_index] = in rv770_populate_smc_vddc_table()
1125 cpu_to_be32(pi->vddc_table[i].low_smio); in rv770_populate_smc_vddc_table()
1128 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0; in rv770_populate_smc_vddc_table()
1129 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] = in rv770_populate_smc_vddc_table()
1130 cpu_to_be32(pi->vddc_mask_low); in rv770_populate_smc_vddc_table()
1133 ((i < pi->valid_vddc_entries) && in rv770_populate_smc_vddc_table()
1134 (pi->max_vddc_in_table > in rv770_populate_smc_vddc_table()
1135 pi->vddc_table[i].vddc)); in rv770_populate_smc_vddc_table()
1138 table->maxVDDCIndexInPPTable = in rv770_populate_smc_vddc_table()
1139 pi->vddc_table[i].vddc_index; in rv770_populate_smc_vddc_table()
1149 if (pi->mvdd_control) { in rv770_populate_smc_mvdd_table()
1150 table->lowSMIO[MVDD_HIGH_INDEX] |= in rv770_populate_smc_mvdd_table()
1151 cpu_to_be32(pi->mvdd_low_smio[MVDD_HIGH_INDEX]); in rv770_populate_smc_mvdd_table()
1152 table->lowSMIO[MVDD_LOW_INDEX] |= in rv770_populate_smc_mvdd_table()
1153 cpu_to_be32(pi->mvdd_low_smio[MVDD_LOW_INDEX]); in rv770_populate_smc_mvdd_table()
1155 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_MVDD] = 0; in rv770_populate_smc_mvdd_table()
1156 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_MVDD] = in rv770_populate_smc_mvdd_table()
1157 cpu_to_be32(pi->mvdd_mask_low); in rv770_populate_smc_mvdd_table()
1168 RV770_SMC_STATETABLE *table = &pi->smc_statetable; in rv770_init_smc_table()
1173 pi->boot_sclk = boot_state->low.sclk; in rv770_init_smc_table()
1178 switch (rdev->pm.int_thermal_type) { in rv770_init_smc_table()
1181 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; in rv770_init_smc_table()
1184 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; in rv770_init_smc_table()
1188 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; in rv770_init_smc_table()
1192 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) { in rv770_init_smc_table()
1193 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in rv770_init_smc_table()
1195 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT) in rv770_init_smc_table()
1196 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK; in rv770_init_smc_table()
1198 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT) in rv770_init_smc_table()
1199 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE; in rv770_init_smc_table()
1202 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv770_init_smc_table()
1203 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in rv770_init_smc_table()
1205 if (pi->mem_gddr5) in rv770_init_smc_table()
1206 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in rv770_init_smc_table()
1208 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_init_smc_table()
1215 if (rdev->family == CHIP_RV740) in rv770_init_smc_table()
1217 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_init_smc_table()
1224 table->driverState = table->initialState; in rv770_init_smc_table()
1227 pi->state_table_start, in rv770_init_smc_table()
1230 pi->sram_end); in rv770_init_smc_table()
1245 steps = (max - min) / step + 1; in rv770_construct_vddc_table()
1248 return -EINVAL; in rv770_construct_vddc_table()
1253 pi->vddc_table[i].vddc = (u16)(min + i * step); in rv770_construct_vddc_table()
1255 pi->vddc_table[i].vddc, in rv770_construct_vddc_table()
1258 pi->vddc_table[i].low_smio = gpio_pins & gpio_mask; in rv770_construct_vddc_table()
1259 pi->vddc_table[i].high_smio = 0; in rv770_construct_vddc_table()
1260 pi->vddc_mask_low = gpio_mask; in rv770_construct_vddc_table()
1262 if ((pi->vddc_table[i].low_smio != in rv770_construct_vddc_table()
1263 pi->vddc_table[i - 1].low_smio) || in rv770_construct_vddc_table()
1264 (pi->vddc_table[i].high_smio != in rv770_construct_vddc_table()
1265 pi->vddc_table[i - 1].high_smio)) in rv770_construct_vddc_table()
1268 pi->vddc_table[i].vddc_index = vddc_index; in rv770_construct_vddc_table()
1271 pi->valid_vddc_entries = (u8)steps; in rv770_construct_vddc_table()
1278 if (memory_info->mem_type == MEM_TYPE_GDDR3) in rv770_get_mclk_split_point()
1292 pi->mvdd_mask_low = gpio_mask; in rv770_get_mvdd_pin_configuration()
1293 pi->mvdd_low_smio[MVDD_HIGH_INDEX] = in rv770_get_mvdd_pin_configuration()
1299 pi->mvdd_low_smio[MVDD_LOW_INDEX] = in rv770_get_mvdd_pin_configuration()
1319 pi->mvdd_control = false; in rv770_get_mvdd_configuration()
1323 pi->mvdd_split_frequency = in rv770_get_mvdd_configuration()
1326 if (pi->mvdd_split_frequency == 0) { in rv770_get_mvdd_configuration()
1327 pi->mvdd_control = false; in rv770_get_mvdd_configuration()
1348 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv770_program_display_gap()
1351 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv770_program_display_gap()
1375 if ((rdev->family == CHIP_RV730) || in r7xx_program_memory_timing_parameters()
1376 (rdev->family == CHIP_RV710) || in r7xx_program_memory_timing_parameters()
1377 (rdev->family == CHIP_RV740)) in r7xx_program_memory_timing_parameters()
1387 u16 address = pi->state_table_start + in rv770_upload_sw_state()
1398 pi->sram_end); in rv770_upload_sw_state()
1404 return -EINVAL; in rv770_halt_smc()
1407 return -EINVAL; in rv770_halt_smc()
1415 return -EINVAL; in rv770_resume_smc()
1429 return -EINVAL; in rv770_set_boot_state()
1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1441 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1444 if (new_state->high.sclk >= current_state->high.sclk) in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1458 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1461 if (new_state->high.sclk < current_state->high.sclk) in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
1470 return -EINVAL; in rv770_restrict_performance_levels_before_switch()
1473 return -EINVAL; in rv770_restrict_performance_levels_before_switch()
1485 return -EINVAL; in rv770_dpm_force_performance_level()
1489 return -EINVAL; in rv770_dpm_force_performance_level()
1493 return -EINVAL; in rv770_dpm_force_performance_level()
1498 return -EINVAL; in rv770_dpm_force_performance_level()
1500 rdev->pm.dpm.forced_level = level; in rv770_dpm_force_performance_level()
1522 pi->clk_regs.rv770.cg_spll_func_cntl = in rv770_read_clock_registers()
1524 pi->clk_regs.rv770.cg_spll_func_cntl_2 = in rv770_read_clock_registers()
1526 pi->clk_regs.rv770.cg_spll_func_cntl_3 = in rv770_read_clock_registers()
1528 pi->clk_regs.rv770.cg_spll_spread_spectrum = in rv770_read_clock_registers()
1530 pi->clk_regs.rv770.cg_spll_spread_spectrum_2 = in rv770_read_clock_registers()
1532 pi->clk_regs.rv770.mpll_ad_func_cntl = in rv770_read_clock_registers()
1534 pi->clk_regs.rv770.mpll_ad_func_cntl_2 = in rv770_read_clock_registers()
1536 pi->clk_regs.rv770.mpll_dq_func_cntl = in rv770_read_clock_registers()
1538 pi->clk_regs.rv770.mpll_dq_func_cntl_2 = in rv770_read_clock_registers()
1540 pi->clk_regs.rv770.mclk_pwrmgt_cntl = in rv770_read_clock_registers()
1542 pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL); in rv770_read_clock_registers()
1547 if (rdev->family == CHIP_RV740) in r7xx_read_clock_registers()
1549 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in r7xx_read_clock_registers()
1559 pi->s0_vid_lower_smio_cntl = in rv770_read_voltage_smio_registers()
1583 vid_smio_cntl = pi->s0_vid_lower_smio_cntl; in rv770_reset_smio_status()
1600 pi->mem_gddr5 = true; in rv770_get_memory_type()
1602 pi->mem_gddr5 = false; in rv770_get_memory_type()
1615 pi->pcie_gen2 = true; in rv770_get_pcie_gen2_status()
1617 pi->pcie_gen2 = false; in rv770_get_pcie_gen2_status()
1619 if (pi->pcie_gen2) { in rv770_get_pcie_gen2_status()
1621 pi->boot_in_gen2 = true; in rv770_get_pcie_gen2_status()
1623 pi->boot_in_gen2 = false; in rv770_get_pcie_gen2_status()
1625 pi->boot_in_gen2 = false; in rv770_get_pcie_gen2_status()
1633 if (pi->gfx_clock_gating) {
1658 for (i = 0; i < rdev->usec_timeout; i++) {
1664 if (pi->gfx_clock_gating)
1677 pi->mclk_odt_threshold = 0; in rv770_get_mclk_odt_threshold()
1679 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) { in rv770_get_mclk_odt_threshold()
1687 pi->mclk_odt_threshold = 30000; in rv770_get_mclk_odt_threshold()
1697 pi->max_vddc = 0; in rv770_get_max_vddc()
1699 pi->max_vddc = vddc; in rv770_get_max_vddc()
1709 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in rv770_program_response_times()
1710 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; in rv770_program_response_times()
1755 if (pi->mclk_odt_threshold == 0) in rv770_program_dcodt_before_state_switch()
1758 if (current_state->high.mclk <= pi->mclk_odt_threshold) in rv770_program_dcodt_before_state_switch()
1761 if (new_state->high.mclk <= pi->mclk_odt_threshold) in rv770_program_dcodt_before_state_switch()
1770 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_program_dcodt_before_state_switch()
1784 if (pi->mclk_odt_threshold == 0) in rv770_program_dcodt_after_state_switch()
1787 if (current_state->high.mclk <= pi->mclk_odt_threshold) in rv770_program_dcodt_after_state_switch()
1790 if (new_state->high.mclk <= pi->mclk_odt_threshold) in rv770_program_dcodt_after_state_switch()
1799 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_program_dcodt_after_state_switch()
1807 if (pi->mclk_odt_threshold == 0) in rv770_retrieve_odt_values()
1810 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_retrieve_odt_values()
1844 if (pi->thermal_protection) in rv770_set_dpm_event_sources()
1858 if (!(pi->active_auto_throttle_sources & (1 << source))) { in rv770_enable_auto_throttle_source()
1859 pi->active_auto_throttle_sources |= 1 << source; in rv770_enable_auto_throttle_source()
1860 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv770_enable_auto_throttle_source()
1863 if (pi->active_auto_throttle_sources & (1 << source)) { in rv770_enable_auto_throttle_source()
1864 pi->active_auto_throttle_sources &= ~(1 << source); in rv770_enable_auto_throttle_source()
1865 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv770_enable_auto_throttle_source()
1881 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in rv770_set_thermal_temperature_range()
1882 return -EINVAL; in rv770_set_thermal_temperature_range()
1889 rdev->pm.dpm.thermal.min_temp = low_temp; in rv770_set_thermal_temperature_range()
1890 rdev->pm.dpm.thermal.max_temp = high_temp; in rv770_set_thermal_temperature_range()
1898 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv770_dpm_enable()
1901 if (pi->gfx_clock_gating) in rv770_dpm_enable()
1905 return -EINVAL; in rv770_dpm_enable()
1907 if (pi->voltage_control) { in rv770_dpm_enable()
1916 if (pi->dcodt) in rv770_dpm_enable()
1919 if (pi->mvdd_control) { in rv770_dpm_enable()
1927 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv770_dpm_enable()
1932 if (pi->thermal_protection) in rv770_dpm_enable()
1945 if (pi->dynamic_pcie_gen2) in rv770_dpm_enable()
1962 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_dpm_enable()
1967 if (pi->gfx_clock_gating) in rv770_dpm_enable()
1970 if (pi->mg_clock_gating) in rv770_dpm_enable()
1982 if (rdev->irq.installed && in rv770_dpm_late_enable()
1983 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in rv770_dpm_late_enable()
1989 rdev->irq.dpm_thermal = true; in rv770_dpm_late_enable()
2009 if (pi->thermal_protection) in rv770_dpm_disable()
2014 if (pi->dynamic_pcie_gen2) in rv770_dpm_disable()
2017 if (rdev->irq.installed && in rv770_dpm_disable()
2018 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in rv770_dpm_disable()
2019 rdev->irq.dpm_thermal = false; in rv770_dpm_disable()
2023 if (pi->gfx_clock_gating) in rv770_dpm_disable()
2026 if (pi->mg_clock_gating) in rv770_dpm_disable()
2029 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) in rv770_dpm_disable()
2041 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rv770_dpm_set_power_state()
2042 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rv770_dpm_set_power_state()
2062 if (pi->dcodt) in rv770_dpm_set_power_state()
2074 if (pi->dcodt) in rv770_dpm_set_power_state()
2085 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2088 if (pi->dcodt)
2091 if (pi->dcodt)
2103 if (pi->dcodt) in rv770_dpm_setup_asic()
2110 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) in rv770_dpm_setup_asic()
2112 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) in rv770_dpm_setup_asic()
2114 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) in rv770_dpm_setup_asic()
2150 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in rv7xx_parse_pplib_non_clock_info()
2151 rps->class = le16_to_cpu(non_clock_info->usClassification); in rv7xx_parse_pplib_non_clock_info()
2152 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rv7xx_parse_pplib_non_clock_info()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2159 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2165 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2169 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) in rv7xx_parse_pplib_non_clock_info()
2170 rdev->pm.dpm.boot_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2171 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) in rv7xx_parse_pplib_non_clock_info()
2172 rdev->pm.dpm.uvd_ps = rps; in rv7xx_parse_pplib_non_clock_info()
2187 pl = &ps->low; in rv7xx_parse_pplib_clock_info()
2190 pl = &ps->medium; in rv7xx_parse_pplib_clock_info()
2194 pl = &ps->high; in rv7xx_parse_pplib_clock_info()
2198 if (rdev->family >= CHIP_CEDAR) { in rv7xx_parse_pplib_clock_info()
2199 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); in rv7xx_parse_pplib_clock_info()
2200 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; in rv7xx_parse_pplib_clock_info()
2201 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); in rv7xx_parse_pplib_clock_info()
2202 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; in rv7xx_parse_pplib_clock_info()
2204 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC); in rv7xx_parse_pplib_clock_info()
2205 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI); in rv7xx_parse_pplib_clock_info()
2206 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags); in rv7xx_parse_pplib_clock_info()
2208 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); in rv7xx_parse_pplib_clock_info()
2209 sclk |= clock_info->r600.ucEngineClockHigh << 16; in rv7xx_parse_pplib_clock_info()
2210 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); in rv7xx_parse_pplib_clock_info()
2211 mclk |= clock_info->r600.ucMemoryClockHigh << 16; in rv7xx_parse_pplib_clock_info()
2213 pl->vddc = le16_to_cpu(clock_info->r600.usVDDC); in rv7xx_parse_pplib_clock_info()
2214 pl->flags = le32_to_cpu(clock_info->r600.ulFlags); in rv7xx_parse_pplib_clock_info()
2217 pl->mclk = mclk; in rv7xx_parse_pplib_clock_info()
2218 pl->sclk = sclk; in rv7xx_parse_pplib_clock_info()
2221 if (pl->vddc == 0xff01) { in rv7xx_parse_pplib_clock_info()
2222 if (pi->max_vddc) in rv7xx_parse_pplib_clock_info()
2223 pl->vddc = pi->max_vddc; in rv7xx_parse_pplib_clock_info()
2226 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { in rv7xx_parse_pplib_clock_info()
2227 pi->acpi_vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2228 if (rdev->family >= CHIP_CEDAR) in rv7xx_parse_pplib_clock_info()
2229 eg_pi->acpi_vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
2230 if (ps->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv7xx_parse_pplib_clock_info()
2231 pi->acpi_pcie_gen2 = true; in rv7xx_parse_pplib_clock_info()
2233 pi->acpi_pcie_gen2 = false; in rv7xx_parse_pplib_clock_info()
2236 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in rv7xx_parse_pplib_clock_info()
2237 if (rdev->family >= CHIP_BARTS) { in rv7xx_parse_pplib_clock_info()
2238 eg_pi->ulv.supported = true; in rv7xx_parse_pplib_clock_info()
2239 eg_pi->ulv.pl = pl; in rv7xx_parse_pplib_clock_info()
2243 if (pi->min_vddc_in_table > pl->vddc) in rv7xx_parse_pplib_clock_info()
2244 pi->min_vddc_in_table = pl->vddc; in rv7xx_parse_pplib_clock_info()
2246 if (pi->max_vddc_in_table < pl->vddc) in rv7xx_parse_pplib_clock_info()
2247 pi->max_vddc_in_table = pl->vddc; in rv7xx_parse_pplib_clock_info()
2250 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { in rv7xx_parse_pplib_clock_info()
2253 pl->mclk = rdev->clock.default_mclk; in rv7xx_parse_pplib_clock_info()
2254 pl->sclk = rdev->clock.default_sclk; in rv7xx_parse_pplib_clock_info()
2255 pl->vddc = vddc; in rv7xx_parse_pplib_clock_info()
2256 pl->vddci = vddci; in rv7xx_parse_pplib_clock_info()
2259 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == in rv7xx_parse_pplib_clock_info()
2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
2270 struct radeon_mode_info *mode_info = &rdev->mode_info; in rv7xx_parse_power_table()
2281 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in rv7xx_parse_power_table()
2283 return -EINVAL; in rv7xx_parse_power_table()
2284 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in rv7xx_parse_power_table()
2286 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, in rv7xx_parse_power_table()
2289 if (!rdev->pm.dpm.ps) in rv7xx_parse_power_table()
2290 return -ENOMEM; in rv7xx_parse_power_table()
2292 for (i = 0; i < power_info->pplib.ucNumStates; i++) { in rv7xx_parse_power_table()
2294 (mode_info->atom_context->bios + data_offset + in rv7xx_parse_power_table()
2295 le16_to_cpu(power_info->pplib.usStateArrayOffset) + in rv7xx_parse_power_table()
2296 i * power_info->pplib.ucStateEntrySize); in rv7xx_parse_power_table()
2298 (mode_info->atom_context->bios + data_offset + in rv7xx_parse_power_table()
2299 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + in rv7xx_parse_power_table()
2300 (power_state->v1.ucNonClockStateIndex * in rv7xx_parse_power_table()
2301 power_info->pplib.ucNonClockSize)); in rv7xx_parse_power_table()
2302 if (power_info->pplib.ucStateEntrySize - 1) { in rv7xx_parse_power_table()
2306 kfree(rdev->pm.dpm.ps); in rv7xx_parse_power_table()
2307 return -ENOMEM; in rv7xx_parse_power_table()
2309 rdev->pm.dpm.ps[i].ps_priv = ps; in rv7xx_parse_power_table()
2310 rv7xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in rv7xx_parse_power_table()
2312 power_info->pplib.ucNonClockSize); in rv7xx_parse_power_table()
2313 idx = (u8 *)&power_state->v1.ucClockStateIndices[0]; in rv7xx_parse_power_table()
2314 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { in rv7xx_parse_power_table()
2316 (mode_info->atom_context->bios + data_offset + in rv7xx_parse_power_table()
2317 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + in rv7xx_parse_power_table()
2318 (idx[j] * power_info->pplib.ucClockInfoSize)); in rv7xx_parse_power_table()
2320 &rdev->pm.dpm.ps[i], j, in rv7xx_parse_power_table()
2325 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; in rv7xx_parse_power_table()
2334 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv770_get_engine_memory_ss()
2336 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv770_get_engine_memory_ss()
2339 if (pi->sclk_ss || pi->mclk_ss) in rv770_get_engine_memory_ss()
2340 pi->dynamic_ss = true; in rv770_get_engine_memory_ss()
2342 pi->dynamic_ss = false; in rv770_get_engine_memory_ss()
2353 return -ENOMEM; in rv770_dpm_init()
2354 rdev->pm.dpm.priv = pi; in rv770_dpm_init()
2358 pi->acpi_vddc = 0; in rv770_dpm_init()
2359 pi->min_vddc_in_table = 0; in rv770_dpm_init()
2360 pi->max_vddc_in_table = 0; in rv770_dpm_init()
2370 if (rdev->pm.dpm.voltage_response_time == 0) in rv770_dpm_init()
2371 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in rv770_dpm_init()
2372 if (rdev->pm.dpm.backbias_response_time == 0) in rv770_dpm_init()
2373 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in rv770_dpm_init()
2378 pi->ref_div = dividers.ref_div + 1; in rv770_dpm_init()
2380 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in rv770_dpm_init()
2382 pi->mclk_strobe_mode_threshold = 30000; in rv770_dpm_init()
2383 pi->mclk_edc_enable_threshold = 30000; in rv770_dpm_init()
2385 pi->rlp = RV770_RLP_DFLT; in rv770_dpm_init()
2386 pi->rmp = RV770_RMP_DFLT; in rv770_dpm_init()
2387 pi->lhp = RV770_LHP_DFLT; in rv770_dpm_init()
2388 pi->lmp = RV770_LMP_DFLT; in rv770_dpm_init()
2390 pi->voltage_control = in rv770_dpm_init()
2393 pi->mvdd_control = in rv770_dpm_init()
2398 pi->asi = RV770_ASI_DFLT; in rv770_dpm_init()
2399 pi->pasi = RV770_HASI_DFLT; in rv770_dpm_init()
2400 pi->vrc = RV770_VRC_DFLT; in rv770_dpm_init()
2402 pi->power_gating = false; in rv770_dpm_init()
2404 pi->gfx_clock_gating = true; in rv770_dpm_init()
2406 pi->mg_clock_gating = true; in rv770_dpm_init()
2407 pi->mgcgtssm = true; in rv770_dpm_init()
2409 pi->dynamic_pcie_gen2 = true; in rv770_dpm_init()
2411 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in rv770_dpm_init()
2412 pi->thermal_protection = true; in rv770_dpm_init()
2414 pi->thermal_protection = false; in rv770_dpm_init()
2416 pi->display_gap = true; in rv770_dpm_init()
2418 if (rdev->flags & RADEON_IS_MOBILITY) in rv770_dpm_init()
2419 pi->dcodt = true; in rv770_dpm_init()
2421 pi->dcodt = false; in rv770_dpm_init()
2423 pi->ulps = true; in rv770_dpm_init()
2425 pi->mclk_stutter_mode_threshold = 0; in rv770_dpm_init()
2427 pi->sram_end = SMC_RAM_END; in rv770_dpm_init()
2428 pi->state_table_start = RV770_SMC_TABLE_ADDRESS; in rv770_dpm_init()
2429 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START; in rv770_dpm_init()
2440 r600_dpm_print_class_info(rps->class, rps->class2); in rv770_dpm_print_power_state()
2441 r600_dpm_print_cap_info(rps->caps); in rv770_dpm_print_power_state()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2443 if (rdev->family >= CHIP_CEDAR) { in rv770_dpm_print_power_state()
2444 pl = &ps->low; in rv770_dpm_print_power_state()
2446 pl->sclk, pl->mclk, pl->vddc, pl->vddci); in rv770_dpm_print_power_state()
2447 pl = &ps->medium; in rv770_dpm_print_power_state()
2449 pl->sclk, pl->mclk, pl->vddc, pl->vddci); in rv770_dpm_print_power_state()
2450 pl = &ps->high; in rv770_dpm_print_power_state()
2452 pl->sclk, pl->mclk, pl->vddc, pl->vddci); in rv770_dpm_print_power_state()
2454 pl = &ps->low; in rv770_dpm_print_power_state()
2456 pl->sclk, pl->mclk, pl->vddc); in rv770_dpm_print_power_state()
2457 pl = &ps->medium; in rv770_dpm_print_power_state()
2459 pl->sclk, pl->mclk, pl->vddc); in rv770_dpm_print_power_state()
2460 pl = &ps->high; in rv770_dpm_print_power_state()
2462 pl->sclk, pl->mclk, pl->vddc); in rv770_dpm_print_power_state()
2470 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv770_dpm_debugfs_print_current_performance_level()
2481 pl = &ps->low; in rv770_dpm_debugfs_print_current_performance_level()
2483 pl = &ps->medium; in rv770_dpm_debugfs_print_current_performance_level()
2485 pl = &ps->high; in rv770_dpm_debugfs_print_current_performance_level()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
2487 if (rdev->family >= CHIP_CEDAR) { in rv770_dpm_debugfs_print_current_performance_level()
2489 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); in rv770_dpm_debugfs_print_current_performance_level()
2492 current_index, pl->sclk, pl->mclk, pl->vddc); in rv770_dpm_debugfs_print_current_performance_level()
2499 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv770_dpm_get_current_sclk()
2510 pl = &ps->low; in rv770_dpm_get_current_sclk()
2512 pl = &ps->medium; in rv770_dpm_get_current_sclk()
2514 pl = &ps->high; in rv770_dpm_get_current_sclk()
2515 return pl->sclk; in rv770_dpm_get_current_sclk()
2521 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv770_dpm_get_current_mclk()
2532 pl = &ps->low; in rv770_dpm_get_current_mclk()
2534 pl = &ps->medium; in rv770_dpm_get_current_mclk()
2536 pl = &ps->high; in rv770_dpm_get_current_mclk()
2537 return pl->mclk; in rv770_dpm_get_current_mclk()
2545 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in rv770_dpm_fini()
2546 kfree(rdev->pm.dpm.ps[i].ps_priv); in rv770_dpm_fini()
2548 kfree(rdev->pm.dpm.ps); in rv770_dpm_fini()
2549 kfree(rdev->pm.dpm.priv); in rv770_dpm_fini()
2554 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps); in rv770_dpm_get_sclk()
2557 return requested_state->low.sclk; in rv770_dpm_get_sclk()
2559 return requested_state->high.sclk; in rv770_dpm_get_sclk()
2564 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps); in rv770_dpm_get_mclk()
2567 return requested_state->low.mclk; in rv770_dpm_get_mclk()
2569 return requested_state->high.mclk; in rv770_dpm_get_mclk()
2579 if ((rdev->family == CHIP_RV770) && in rv770_dpm_vblank_too_short()
2580 !(rdev->flags & RADEON_IS_MOBILITY)) in rv770_dpm_vblank_too_short()