Lines Matching +full:0 +full:x2800
26 #define CG_SPLL_FUNC_CNTL 0x600
27 #define SPLL_RESET (1 << 0)
32 #define SPLL_REF_DIV_MASK (0x3f << 4)
34 #define SPLL_HILEN_MASK (0xf << 12)
36 #define SPLL_LOLEN_MASK (0xf << 16)
37 #define CG_SPLL_FUNC_CNTL_2 0x604
38 #define SCLK_MUX_SEL(x) ((x) << 0)
39 #define SCLK_MUX_SEL_MASK (0x1ff << 0)
40 #define CG_SPLL_FUNC_CNTL_3 0x608
41 #define SPLL_FB_DIV(x) ((x) << 0)
42 #define SPLL_FB_DIV_MASK (0x3ffffff << 0)
45 #define CG_MPLL_FUNC_CNTL 0x624
46 #define MPLL_RESET (1 << 0)
51 #define MPLL_REF_DIV_MASK (0x3f << 4)
53 #define MPLL_HILEN_MASK (0xf << 12)
55 #define MPLL_LOLEN_MASK (0xf << 16)
56 #define CG_MPLL_FUNC_CNTL_2 0x628
57 #define MCLK_MUX_SEL(x) ((x) << 0)
58 #define MCLK_MUX_SEL_MASK (0x1ff << 0)
59 #define CG_MPLL_FUNC_CNTL_3 0x62c
60 #define MPLL_FB_DIV(x) ((x) << 0)
61 #define MPLL_FB_DIV_MASK (0x3ffffff << 0)
64 #define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634
65 #define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638
66 #define GENERAL_PWRMGT 0x63c
67 # define GLOBAL_PWRMGT_EN (1 << 0)
83 #define SCLK_PWRMGT_CNTL 0x644
84 # define SCLK_PWRMGT_OFF (1 << 0)
97 #define TCI_MCLK_PWRMGT_CNTL 0x648
121 #define TCI_DLL_CNTL 0x64c
123 #define CG_PG_CNTL 0x858
124 # define PWRGATE_ENABLE (1 << 0)
126 #define CG_AT 0x6d4
127 #define CG_R(x) ((x) << 0)
128 #define CG_R_MASK (0xffff << 0)
130 #define CG_L_MASK (0xffff << 16)
132 #define CG_SPLL_SPREAD_SPECTRUM 0x790
133 #define SSEN (1 << 0)
135 #define CLK_S_MASK (0xfff << 4)
136 #define CG_SPLL_SPREAD_SPECTRUM_2 0x794
137 #define CLK_V(x) ((x) << 0)
138 #define CLK_V_MASK (0x3ffffff << 0)
140 #define MC_ARB_DRAM_TIMING 0x2774
141 #define MC_ARB_DRAM_TIMING2 0x2778
143 #define MC_ARB_RFSH_RATE 0x27b0
144 #define POWERMODE0(x) ((x) << 0)
145 #define POWERMODE0_MASK (0xff << 0)
147 #define POWERMODE1_MASK (0xff << 8)
149 #define POWERMODE2_MASK (0xff << 16)
151 #define POWERMODE3_MASK (0xff << 24)
153 #define MC_ARB_DRAM_TIMING_1 0x27f0
154 #define MC_ARB_DRAM_TIMING_2 0x27f4
155 #define MC_ARB_DRAM_TIMING_3 0x27f8
156 #define MC_ARB_DRAM_TIMING2_1 0x27fc
157 #define MC_ARB_DRAM_TIMING2_2 0x2800
158 #define MC_ARB_DRAM_TIMING2_3 0x2804
160 #define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978
161 #define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c
162 #define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980
163 #define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984