Lines Matching +full:0 +full:x740
27 #define SPLL_CNTL_MODE 0x60c
30 #define GENERAL_PWRMGT 0x618
31 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define MCLK_PWRMGT_CNTL 0x624
48 # define MPLL_PWRMGT_OFF (1 << 0)
78 #define MPLL_FREQ_LEVEL_0 0x6e8
79 # define LEVEL0_MPLL_POST_DIV(x) ((x) << 0)
80 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0)
82 # define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8)
84 # define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20)
89 #define VID_RT 0x6f8
90 # define VID_CRT(x) ((x) << 0)
91 # define VID_CRT_MASK (0x1fff << 0)
97 # define VID_SWT_MASK (0x1f << 19)
99 # define BRT_MASK (0xff << 24)
101 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
102 # define TARGET_PROFILE_INDEX_MASK (3 << 0)
103 # define TARGET_PROFILE_INDEX_SHIFT 0
111 # define CURR_SCLK_INDEX_MASK (0x1f << 8)
116 #define VID_UPPER_GPIO_CNTL 0x740
117 # define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0)
118 # define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0)
130 #define CG_DISPLAY_GAP_CNTL 0x7dc
131 # define DISP1_GAP(x) ((x) << 0)
132 # define DISP1_GAP_MASK (3 << 0)
136 # define VBI_TIMER_COUNT_MASK (0x3fff << 4)
144 #define CG_THERMAL_CTRL 0x7f0
145 # define DPM_EVENT_SRC(x) ((x) << 0)
146 # define DPM_EVENT_SRC_MASK (7 << 0)
149 # define TOFFSET_MASK (0xff << 4)
151 # define DIG_THERM_DPM_MASK (0xff << 12)
157 #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820
158 # define SSEN (1 << 0)
160 # define CLKS_MASK (0xff << 3)
163 # define CLKV_MASK (0x7ff << 11)
165 #define CG_MPLL_SPREAD_SPECTRUM 0x830
167 #define CITF_CNTL 0x200c
168 # define BLACKOUT_RD (1 << 0)
171 #define RAMCFG 0x2408
172 #define NOOFBANK_SHIFT 0
173 #define NOOFBANK_MASK 0x00000001
175 #define NOOFRANK_MASK 0x00000002
177 #define NOOFROWS_MASK 0x0000001C
179 #define NOOFCOLS_MASK 0x00000060
181 #define CHANSIZE_MASK 0x00000080
183 #define BURSTLENGTH_MASK 0x00000100
186 #define SQM_RATIO 0x2424
187 # define STATE0(x) ((x) << 0)
188 # define STATE0_MASK (0xff << 0)
190 # define STATE1_MASK (0xff << 8)
192 # define STATE2_MASK (0xff << 16)
194 # define STATE3_MASK (0xff << 24)
196 #define ARB_RFSH_CNTL 0x2460
197 # define ENABLE (1 << 0)
198 #define ARB_RFSH_RATE 0x2464
199 # define POWERMODE0(x) ((x) << 0)
200 # define POWERMODE0_MASK (0xff << 0)
202 # define POWERMODE1_MASK (0xff << 8)
204 # define POWERMODE2_MASK (0xff << 16)
206 # define POWERMODE3_MASK (0xff << 24)
208 #define MC_SEQ_DRAM 0x2608
211 #define MC_SEQ_CMD 0x26c4
213 #define MC_SEQ_RESERVE_S 0x2890
214 #define MC_SEQ_RESERVE_M 0x2894
216 #define LVTMA_DATA_SYNCHRONIZATION 0x7adc
218 #define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98
221 #define PCIE_P_CNTL 0x40
227 #define PCIE_LC_CNTL 0xa0
229 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
232 # define LC_L1_INACTIVITY_MASK (0xf << 12)
236 #define PCIE_LC_SPEED_CNTL 0xa4
237 # define LC_GEN2_EN (1 << 0)