Lines Matching +full:idle +full:- +full:wait +full:- +full:delay
39 #include <linux/io-64-nonatomic-lo-hi.h>
59 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
84 * avivo_wait_for_vblank - vblank wait asic callback.
87 * @crtc: crtc to wait for vblank on
89 * Wait for vblank on the requested crtc (r5xx-r7xx).
95 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
102 * wait for another frame. in avivo_wait_for_vblank()
121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
122 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rs600_page_flip()
123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip()
135 fb->pitches[0] / fb->format->cpp[0]); in rs600_page_flip()
137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
142 /* Wait for update_pending to go high. */ in rs600_page_flip()
143 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_page_flip()
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
150 /* Unlock the lock, so double-buffering can take place inside vblank */ in rs600_page_flip()
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
157 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
160 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
166 struct drm_device *dev = encoder->dev; in avivo_program_fmt()
167 struct radeon_device *rdev = dev->dev_private; in avivo_program_fmt()
177 dither = radeon_connector->dither; in avivo_program_fmt()
181 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in avivo_program_fmt()
210 switch (radeon_encoder->encoder_id) { in avivo_program_fmt()
230 int requested_index = rdev->pm.requested_power_state_index; in rs600_pm_misc()
231 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in rs600_pm_misc()
232 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in rs600_pm_misc()
236 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in rs600_pm_misc()
237 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in rs600_pm_misc()
238 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
239 if (voltage->active_high) in rs600_pm_misc()
240 tmp |= voltage->gpio.mask; in rs600_pm_misc()
242 tmp &= ~(voltage->gpio.mask); in rs600_pm_misc()
243 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
244 if (voltage->delay) in rs600_pm_misc()
245 udelay(voltage->delay); in rs600_pm_misc()
247 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
248 if (voltage->active_high) in rs600_pm_misc()
249 tmp &= ~voltage->gpio.mask; in rs600_pm_misc()
251 tmp |= voltage->gpio.mask; in rs600_pm_misc()
252 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
253 if (voltage->delay) in rs600_pm_misc()
254 udelay(voltage->delay); in rs600_pm_misc()
256 } else if (voltage->type == VOLTAGE_VDDC) in rs600_pm_misc()
257 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); in rs600_pm_misc()
262 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in rs600_pm_misc()
263 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { in rs600_pm_misc()
266 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { in rs600_pm_misc()
277 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in rs600_pm_misc()
279 if (voltage->delay) { in rs600_pm_misc()
281 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); in rs600_pm_misc()
289 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in rs600_pm_misc()
297 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) in rs600_pm_misc()
304 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) in rs600_pm_misc()
311 if ((rdev->flags & RADEON_IS_PCIE) && in rs600_pm_misc()
312 !(rdev->flags & RADEON_IS_IGP) && in rs600_pm_misc()
313 rdev->asic->pm.set_pcie_lanes && in rs600_pm_misc()
314 (ps->pcie_lanes != in rs600_pm_misc()
315 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in rs600_pm_misc()
317 ps->pcie_lanes); in rs600_pm_misc()
318 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); in rs600_pm_misc()
330 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_prepare()
332 if (radeon_crtc->enabled) { in rs600_pm_prepare()
333 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
335 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare()
348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_finish()
350 if (radeon_crtc->enabled) { in rs600_pm_finish()
351 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish()
353 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_finish()
415 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_init()
417 switch (radeon_connector->hpd.hpd) { in rs600_hpd_init()
429 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_init()
430 enable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_init()
431 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in rs600_hpd_init()
442 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_fini()
444 switch (radeon_connector->hpd.hpd) { in rs600_hpd_fini()
456 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_fini()
457 disable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_fini()
475 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
483 pci_save_state(rdev->pdev); in rs600_asic_reset()
485 pci_clear_master(rdev->pdev); in rs600_asic_reset()
495 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
503 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
511 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
513 pci_restore_state(rdev->pdev); in rs600_asic_reset()
514 /* Check if GPU is idle */ in rs600_asic_reset()
516 dev_err(rdev->dev, "failed to reset GPU\n"); in rs600_asic_reset()
517 ret = -1; in rs600_asic_reset()
519 dev_info(rdev->dev, "GPU reset succeed\n"); in rs600_asic_reset()
549 if (rdev->gart.robj) { in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
569 return -EINVAL; in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
605 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
606 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
610 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
611 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
620 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
621 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
622 rdev->gart.ready = true; in rs600_gart_enable()
662 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
681 if (!rdev->irq.installed) { in rs600_irq_set()
684 return -EINVAL; in rs600_irq_set()
686 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
689 if (rdev->irq.crtc_vblank_int[0] || in rs600_irq_set()
690 atomic_read(&rdev->irq.pflip[0])) { in rs600_irq_set()
693 if (rdev->irq.crtc_vblank_int[1] || in rs600_irq_set()
694 atomic_read(&rdev->irq.pflip[1])) { in rs600_irq_set()
697 if (rdev->irq.hpd[0]) { in rs600_irq_set()
700 if (rdev->irq.hpd[1]) { in rs600_irq_set()
703 if (rdev->irq.afmt[0]) { in rs600_irq_set()
726 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
727 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
731 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
735 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
740 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
746 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
750 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & in rs600_irq_ack()
752 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_ack()
758 rdev->irq.stat_regs.r500.hdmi0_status = 0; in rs600_irq_ack()
773 /* Wait and acknowledge irq */ in rs600_irq_disable()
786 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
787 !rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
791 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
792 rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
798 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
799 if (rdev->irq.crtc_vblank_int[0]) { in rs600_irq_process()
801 rdev->pm.vblank_sync = true; in rs600_irq_process()
802 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
804 if (atomic_read(&rdev->irq.pflip[0])) in rs600_irq_process()
807 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
808 if (rdev->irq.crtc_vblank_int[1]) { in rs600_irq_process()
810 rdev->pm.vblank_sync = true; in rs600_irq_process()
811 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
813 if (atomic_read(&rdev->irq.pflip[1])) in rs600_irq_process()
816 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
820 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
824 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_process()
831 schedule_delayed_work(&rdev->hotplug_work, 0); in rs600_irq_process()
833 schedule_work(&rdev->audio_work); in rs600_irq_process()
834 if (rdev->msi_enabled) { in rs600_irq_process()
835 switch (rdev->family) { in rs600_irq_process()
863 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_mc_wait_for_idle()
868 return -1; in rs600_mc_wait_for_idle()
874 /* Wait for mc idle */ in rs600_gpu_init()
876 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
883 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
884 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
885 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
886 rdev->mc.vram_width = 128; in rs600_mc_init()
887 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
888 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
889 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
890 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
893 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
894 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
895 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
906 if (!rdev->mode_info.mode_config_initialized) in rs600_bandwidth_update()
911 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
912 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
913 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
914 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
918 if (rdev->disp_priority == 2) { in rs600_bandwidth_update()
935 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
939 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
947 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
951 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
956 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; in rs600_set_safe_registers()
957 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); in rs600_set_safe_registers()
967 /* Wait for mc idle */ in rs600_mc_program()
969 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
978 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
1007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs600_startup()
1012 if (!rdev->irq.installed) { in rs600_startup()
1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs600_startup()
1023 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs600_startup()
1029 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs600_startup()
1035 dev_err(rdev->dev, "failed initializing audio\n"); in rs600_startup()
1052 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1057 atom_asic_init(rdev->mode_info.atom_context); in rs600_resume()
1063 rdev->accel_working = true; in rs600_resume()
1066 rdev->accel_working = false; in rs600_resume()
1095 kfree(rdev->bios); in rs600_fini()
1096 rdev->bios = NULL; in rs600_fini()
1114 return -EINVAL; in rs600_init()
1116 if (rdev->is_atom_bios) { in rs600_init()
1121 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); in rs600_init()
1122 return -EINVAL; in rs600_init()
1126 dev_warn(rdev->dev, in rs600_init()
1133 return -EINVAL; in rs600_init()
1154 rdev->accel_working = true; in rs600_init()
1158 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs600_init()
1164 rdev->accel_working = false; in rs600_init()