41 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
43 void rs400_gart_adjust_size(struct radeon_device *rdev)  in rs400_gart_adjust_size()  argument
46 	switch (rdev->mc.gtt_size/(1024*1024)) {  in rs400_gart_adjust_size()
57 			  (unsigned)(rdev->mc.gtt_size >> 20));  in rs400_gart_adjust_size()
60 		rdev->mc.gtt_size = 32 * 1024 * 1024;  in rs400_gart_adjust_size()
65 void rs400_gart_tlb_flush(struct radeon_device *rdev)  in rs400_gart_tlb_flush()  argument
68 	unsigned int timeout = rdev->usec_timeout;  in rs400_gart_tlb_flush()
81 int rs400_gart_init(struct radeon_device *rdev)  in rs400_gart_init()  argument
85 	if (rdev->gart.ptr) {  in rs400_gart_init()
90 	switch (rdev->mc.gtt_size / (1024 * 1024)) {  in rs400_gart_init()
103 	r = radeon_gart_init(rdev);  in rs400_gart_init()
106 	rs400_debugfs_pcie_gart_info_init(rdev);  in rs400_gart_init()
107 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;  in rs400_gart_init()
108 	return radeon_gart_table_ram_alloc(rdev);  in rs400_gart_init()
111 int rs400_gart_enable(struct radeon_device *rdev)  in rs400_gart_enable()  argument
120 	switch (rdev->mc.gtt_size / (1024 * 1024)) {  in rs400_gart_enable()
146 	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {  in rs400_gart_enable()
153 	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);  in rs400_gart_enable()
154 	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);  in rs400_gart_enable()
155 	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {  in rs400_gart_enable()
165 	tmp = (u32)rdev->gart.table_addr & 0xfffff000;  in rs400_gart_enable()
166 	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;  in rs400_gart_enable()
179 	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {  in rs400_gart_enable()
190 	rs400_gart_tlb_flush(rdev);  in rs400_gart_enable()
192 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rs400_gart_enable()
193 		 (unsigned long long)rdev->gart.table_addr);  in rs400_gart_enable()
194 	rdev->gart.ready = true;  in rs400_gart_enable()
198 void rs400_gart_disable(struct radeon_device *rdev)  in rs400_gart_disable()  argument
208 void rs400_gart_fini(struct radeon_device *rdev)  in rs400_gart_fini()  argument
210 	radeon_gart_fini(rdev);  in rs400_gart_fini()
211 	rs400_gart_disable(rdev);  in rs400_gart_fini()
212 	radeon_gart_table_ram_free(rdev);  in rs400_gart_fini()
234 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,  in rs400_gart_set_page()  argument
237 	u32 *gtt = rdev->gart.ptr;  in rs400_gart_set_page()
241 int rs400_mc_wait_for_idle(struct radeon_device *rdev)  in rs400_mc_wait_for_idle()  argument
246 	for (i = 0; i < rdev->usec_timeout; i++) {  in rs400_mc_wait_for_idle()
257 static void rs400_gpu_init(struct radeon_device *rdev)  in rs400_gpu_init()  argument
260 	r420_pipes_init(rdev);  in rs400_gpu_init()
261 	if (rs400_mc_wait_for_idle(rdev)) {  in rs400_gpu_init()
267 static void rs400_mc_init(struct radeon_device *rdev)  in rs400_mc_init()  argument
271 	rs400_gart_adjust_size(rdev);  in rs400_mc_init()
272 	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);  in rs400_mc_init()
274 	rdev->mc.vram_is_ddr = true;  in rs400_mc_init()
275 	rdev->mc.vram_width = 128;  in rs400_mc_init()
276 	r100_vram_init_sizes(rdev);  in rs400_mc_init()
278 	radeon_vram_location(rdev, &rdev->mc, base);  in rs400_mc_init()
279 	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;  in rs400_mc_init()
280 	radeon_gtt_location(rdev, &rdev->mc);  in rs400_mc_init()
281 	radeon_update_bandwidth_info(rdev);  in rs400_mc_init()
284 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)  in rs400_mc_rreg()  argument
289 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rs400_mc_rreg()
293 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rs400_mc_rreg()
297 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)  in rs400_mc_wreg()  argument
301 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rs400_mc_wreg()
305 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rs400_mc_wreg()
311 	struct radeon_device *rdev = m->private;  in rs400_debugfs_gart_info_show()  local
320 	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {  in rs400_debugfs_gart_info_show()
379 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)  in rs400_debugfs_pcie_gart_info_init()  argument
382 	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;  in rs400_debugfs_pcie_gart_info_init()
384 	debugfs_create_file("rs400_gart_info", 0444, root, rdev,  in rs400_debugfs_pcie_gart_info_init()
389 static void rs400_mc_program(struct radeon_device *rdev)  in rs400_mc_program()  argument
394 	r100_mc_stop(rdev, &save);  in rs400_mc_program()
397 	if (rs400_mc_wait_for_idle(rdev))  in rs400_mc_program()
398 		dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");  in rs400_mc_program()
400 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |  in rs400_mc_program()
401 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));  in rs400_mc_program()
403 	r100_mc_resume(rdev, &save);  in rs400_mc_program()
406 static int rs400_startup(struct radeon_device *rdev)  in rs400_startup()  argument
410 	r100_set_common_regs(rdev);  in rs400_startup()
412 	rs400_mc_program(rdev);  in rs400_startup()
414 	r300_clock_startup(rdev);  in rs400_startup()
416 	rs400_gpu_init(rdev);  in rs400_startup()
417 	r100_enable_bm(rdev);  in rs400_startup()
420 	r = rs400_gart_enable(rdev);  in rs400_startup()
425 	r = radeon_wb_init(rdev);  in rs400_startup()
429 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);  in rs400_startup()
431 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in rs400_startup()
436 	if (!rdev->irq.installed) {  in rs400_startup()
437 		r = radeon_irq_kms_init(rdev);  in rs400_startup()
442 	r100_irq_set(rdev);  in rs400_startup()
443 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in rs400_startup()
445 	r = r100_cp_init(rdev, 1024 * 1024);  in rs400_startup()
447 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);  in rs400_startup()
451 	r = radeon_ib_pool_init(rdev);  in rs400_startup()
453 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in rs400_startup()
460 int rs400_resume(struct radeon_device *rdev)  in rs400_resume()  argument
465 	rs400_gart_disable(rdev);  in rs400_resume()
467 	r300_clock_startup(rdev);  in rs400_resume()
469 	rs400_mc_program(rdev);  in rs400_resume()
471 	if (radeon_asic_reset(rdev)) {  in rs400_resume()
472 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in rs400_resume()
477 	radeon_combios_asic_init(rdev_to_drm(rdev));  in rs400_resume()
479 	r300_clock_startup(rdev);  in rs400_resume()
481 	radeon_surface_init(rdev);  in rs400_resume()
483 	rdev->accel_working = true;  in rs400_resume()
484 	r = rs400_startup(rdev);  in rs400_resume()
486 		rdev->accel_working = false;  in rs400_resume()
491 int rs400_suspend(struct radeon_device *rdev)  in rs400_suspend()  argument
493 	radeon_pm_suspend(rdev);  in rs400_suspend()
494 	r100_cp_disable(rdev);  in rs400_suspend()
495 	radeon_wb_disable(rdev);  in rs400_suspend()
496 	r100_irq_disable(rdev);  in rs400_suspend()
497 	rs400_gart_disable(rdev);  in rs400_suspend()
501 void rs400_fini(struct radeon_device *rdev)  in rs400_fini()  argument
503 	radeon_pm_fini(rdev);  in rs400_fini()
504 	r100_cp_fini(rdev);  in rs400_fini()
505 	radeon_wb_fini(rdev);  in rs400_fini()
506 	radeon_ib_pool_fini(rdev);  in rs400_fini()
507 	radeon_gem_fini(rdev);  in rs400_fini()
508 	rs400_gart_fini(rdev);  in rs400_fini()
509 	radeon_irq_kms_fini(rdev);  in rs400_fini()
510 	radeon_fence_driver_fini(rdev);  in rs400_fini()
511 	radeon_bo_fini(rdev);  in rs400_fini()
512 	radeon_atombios_fini(rdev);  in rs400_fini()
513 	kfree(rdev->bios);  in rs400_fini()
514 	rdev->bios = NULL;  in rs400_fini()
517 int rs400_init(struct radeon_device *rdev)  in rs400_init()  argument
522 	r100_vga_render_disable(rdev);  in rs400_init()
524 	radeon_scratch_init(rdev);  in rs400_init()
526 	radeon_surface_init(rdev);  in rs400_init()
529 	r100_restore_sanity(rdev);  in rs400_init()
531 	if (!radeon_get_bios(rdev)) {  in rs400_init()
532 		if (ASIC_IS_AVIVO(rdev))  in rs400_init()
535 	if (rdev->is_atom_bios) {  in rs400_init()
536 		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");  in rs400_init()
539 		r = radeon_combios_init(rdev);  in rs400_init()
544 	if (radeon_asic_reset(rdev)) {  in rs400_init()
545 		dev_warn(rdev->dev,  in rs400_init()
551 	if (radeon_boot_test_post_card(rdev) == false)  in rs400_init()
555 	radeon_get_clock_info(rdev_to_drm(rdev));  in rs400_init()
557 	rs400_mc_init(rdev);  in rs400_init()
559 	radeon_fence_driver_init(rdev);  in rs400_init()
561 	r = radeon_bo_init(rdev);  in rs400_init()
564 	r = rs400_gart_init(rdev);  in rs400_init()
567 	r300_set_reg_safe(rdev);  in rs400_init()
570 	radeon_pm_init(rdev);  in rs400_init()
572 	rdev->accel_working = true;  in rs400_init()
573 	r = rs400_startup(rdev);  in rs400_init()
576 		dev_err(rdev->dev, "Disabling GPU acceleration\n");  in rs400_init()
577 		r100_cp_fini(rdev);  in rs400_init()
578 		radeon_wb_fini(rdev);  in rs400_init()
579 		radeon_ib_pool_fini(rdev);  in rs400_init()
580 		rs400_gart_fini(rdev);  in rs400_init()
581 		radeon_irq_kms_fini(rdev);  in rs400_init()
582 		rdev->accel_working = false;  in rs400_init()