Lines Matching +full:0 +full:x4124

62 #define RADEON_MC_AGP_LOCATION		0x014c
63 #define		RADEON_MC_AGP_START_MASK	0x0000FFFF
64 #define		RADEON_MC_AGP_START_SHIFT	0
65 #define		RADEON_MC_AGP_TOP_MASK		0xFFFF0000
67 #define RADEON_MC_FB_LOCATION		0x0148
68 #define		RADEON_MC_FB_START_MASK		0x0000FFFF
69 #define		RADEON_MC_FB_START_SHIFT	0
70 #define		RADEON_MC_FB_TOP_MASK		0xFFFF0000
72 #define RADEON_AGP_BASE_2		0x015c /* r200+ only */
73 #define RADEON_AGP_BASE			0x0170
75 #define ATI_DATATYPE_VQ				0
92 #define RADEON_ADAPTER_ID                   0x0f2c /* PCI */
93 #define RADEON_AGP_BASE                     0x0170
94 #define RADEON_AGP_CNTL                     0x0174
95 #       define RADEON_AGP_APER_SIZE_256MB   (0x00 << 0)
96 #       define RADEON_AGP_APER_SIZE_128MB   (0x20 << 0)
97 #       define RADEON_AGP_APER_SIZE_64MB    (0x30 << 0)
98 #       define RADEON_AGP_APER_SIZE_32MB    (0x38 << 0)
99 #       define RADEON_AGP_APER_SIZE_16MB    (0x3c << 0)
100 #       define RADEON_AGP_APER_SIZE_8MB     (0x3e << 0)
101 #       define RADEON_AGP_APER_SIZE_4MB     (0x3f << 0)
102 #       define RADEON_AGP_APER_SIZE_MASK    (0x3f << 0)
103 #define RADEON_STATUS_PCI_CONFIG            0x06
104 #       define RADEON_CAP_LIST              0x100000
105 #define RADEON_CAPABILITIES_PTR_PCI_CONFIG  0x34 /* offset in PCI config*/
106 #       define RADEON_CAP_PTR_MASK          0xfc /* mask off reserved bits of CAP_PTR */
107 #       define RADEON_CAP_ID_NULL           0x00 /* End of capability list */
108 #       define RADEON_CAP_ID_AGP            0x02 /* AGP capability ID */
109 #       define RADEON_CAP_ID_EXP            0x10 /* PCI Express */
110 #define RADEON_AGP_COMMAND                  0x0f60 /* PCI */
111 #define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/
113 #define RADEON_AGP_PLL_CNTL                 0x000b /* PLL */
114 #define RADEON_AGP_STATUS                   0x0f5c /* PCI */
115 #       define RADEON_AGP_1X_MODE           0x01
116 #       define RADEON_AGP_2X_MODE           0x02
117 #       define RADEON_AGP_4X_MODE           0x04
118 #       define RADEON_AGP_FW_MODE           0x10
119 #       define RADEON_AGP_MODE_MASK         0x17
120 #       define RADEON_AGPv3_MODE            0x08
121 #       define RADEON_AGPv3_4X_MODE         0x01
122 #       define RADEON_AGPv3_8X_MODE         0x02
123 #define RADEON_ATTRDR                       0x03c1 /* VGA */
124 #define RADEON_ATTRDW                       0x03c0 /* VGA */
125 #define RADEON_ATTRX                        0x03c0 /* VGA */
126 #define RADEON_AUX_SC_CNTL                  0x1660
127 #       define RADEON_AUX1_SC_EN            (1 << 0)
128 #       define RADEON_AUX1_SC_MODE_OR       (0 << 1)
131 #       define RADEON_AUX2_SC_MODE_OR       (0 << 3)
134 #       define RADEON_AUX3_SC_MODE_OR       (0 << 5)
136 #define RADEON_AUX1_SC_BOTTOM               0x1670
137 #define RADEON_AUX1_SC_LEFT                 0x1664
138 #define RADEON_AUX1_SC_RIGHT                0x1668
139 #define RADEON_AUX1_SC_TOP                  0x166c
140 #define RADEON_AUX2_SC_BOTTOM               0x1680
141 #define RADEON_AUX2_SC_LEFT                 0x1674
142 #define RADEON_AUX2_SC_RIGHT                0x1678
143 #define RADEON_AUX2_SC_TOP                  0x167c
144 #define RADEON_AUX3_SC_BOTTOM               0x1690
145 #define RADEON_AUX3_SC_LEFT                 0x1684
146 #define RADEON_AUX3_SC_RIGHT                0x1688
147 #define RADEON_AUX3_SC_TOP                  0x168c
148 #define RADEON_AUX_WINDOW_HORZ_CNTL         0x02d8
149 #define RADEON_AUX_WINDOW_VERT_CNTL         0x02dc
151 #define RADEON_BASE_CODE                    0x0f0b
152 #define RADEON_BIOS_0_SCRATCH               0x0010
158 #       define RADEON_DISPLAY_ROT_00        (0 << 28)
162 #define RADEON_BIOS_1_SCRATCH               0x0014
163 #define RADEON_BIOS_2_SCRATCH               0x0018
164 #define RADEON_BIOS_3_SCRATCH               0x001c
165 #define RADEON_BIOS_4_SCRATCH               0x0020
166 #       define RADEON_CRT1_ATTACHED_MASK    (3 << 0)
167 #       define RADEON_CRT1_ATTACHED_MONO    (1 << 0)
168 #       define RADEON_CRT1_ATTACHED_COLOR   (2 << 0)
178 #define RADEON_BIOS_5_SCRATCH               0x0024
179 #       define RADEON_LCD1_ON               (1 << 0)
207 #define RADEON_BIOS_6_SCRATCH               0x0028
215 #       define RADEON_DPMS_ON               (0 << 24)
222 #define RADEON_BIOS_7_SCRATCH               0x002c
225 #define RADEON_BIOS_ROM                     0x0f30 /* PCI */
226 #define RADEON_BIST                         0x0f0f /* PCI */
227 #define RADEON_BRUSH_DATA0                  0x1480
228 #define RADEON_BRUSH_DATA1                  0x1484
229 #define RADEON_BRUSH_DATA10                 0x14a8
230 #define RADEON_BRUSH_DATA11                 0x14ac
231 #define RADEON_BRUSH_DATA12                 0x14b0
232 #define RADEON_BRUSH_DATA13                 0x14b4
233 #define RADEON_BRUSH_DATA14                 0x14b8
234 #define RADEON_BRUSH_DATA15                 0x14bc
235 #define RADEON_BRUSH_DATA16                 0x14c0
236 #define RADEON_BRUSH_DATA17                 0x14c4
237 #define RADEON_BRUSH_DATA18                 0x14c8
238 #define RADEON_BRUSH_DATA19                 0x14cc
239 #define RADEON_BRUSH_DATA2                  0x1488
240 #define RADEON_BRUSH_DATA20                 0x14d0
241 #define RADEON_BRUSH_DATA21                 0x14d4
242 #define RADEON_BRUSH_DATA22                 0x14d8
243 #define RADEON_BRUSH_DATA23                 0x14dc
244 #define RADEON_BRUSH_DATA24                 0x14e0
245 #define RADEON_BRUSH_DATA25                 0x14e4
246 #define RADEON_BRUSH_DATA26                 0x14e8
247 #define RADEON_BRUSH_DATA27                 0x14ec
248 #define RADEON_BRUSH_DATA28                 0x14f0
249 #define RADEON_BRUSH_DATA29                 0x14f4
250 #define RADEON_BRUSH_DATA3                  0x148c
251 #define RADEON_BRUSH_DATA30                 0x14f8
252 #define RADEON_BRUSH_DATA31                 0x14fc
253 #define RADEON_BRUSH_DATA32                 0x1500
254 #define RADEON_BRUSH_DATA33                 0x1504
255 #define RADEON_BRUSH_DATA34                 0x1508
256 #define RADEON_BRUSH_DATA35                 0x150c
257 #define RADEON_BRUSH_DATA36                 0x1510
258 #define RADEON_BRUSH_DATA37                 0x1514
259 #define RADEON_BRUSH_DATA38                 0x1518
260 #define RADEON_BRUSH_DATA39                 0x151c
261 #define RADEON_BRUSH_DATA4                  0x1490
262 #define RADEON_BRUSH_DATA40                 0x1520
263 #define RADEON_BRUSH_DATA41                 0x1524
264 #define RADEON_BRUSH_DATA42                 0x1528
265 #define RADEON_BRUSH_DATA43                 0x152c
266 #define RADEON_BRUSH_DATA44                 0x1530
267 #define RADEON_BRUSH_DATA45                 0x1534
268 #define RADEON_BRUSH_DATA46                 0x1538
269 #define RADEON_BRUSH_DATA47                 0x153c
270 #define RADEON_BRUSH_DATA48                 0x1540
271 #define RADEON_BRUSH_DATA49                 0x1544
272 #define RADEON_BRUSH_DATA5                  0x1494
273 #define RADEON_BRUSH_DATA50                 0x1548
274 #define RADEON_BRUSH_DATA51                 0x154c
275 #define RADEON_BRUSH_DATA52                 0x1550
276 #define RADEON_BRUSH_DATA53                 0x1554
277 #define RADEON_BRUSH_DATA54                 0x1558
278 #define RADEON_BRUSH_DATA55                 0x155c
279 #define RADEON_BRUSH_DATA56                 0x1560
280 #define RADEON_BRUSH_DATA57                 0x1564
281 #define RADEON_BRUSH_DATA58                 0x1568
282 #define RADEON_BRUSH_DATA59                 0x156c
283 #define RADEON_BRUSH_DATA6                  0x1498
284 #define RADEON_BRUSH_DATA60                 0x1570
285 #define RADEON_BRUSH_DATA61                 0x1574
286 #define RADEON_BRUSH_DATA62                 0x1578
287 #define RADEON_BRUSH_DATA63                 0x157c
288 #define RADEON_BRUSH_DATA7                  0x149c
289 #define RADEON_BRUSH_DATA8                  0x14a0
290 #define RADEON_BRUSH_DATA9                  0x14a4
291 #define RADEON_BRUSH_SCALE                  0x1470
292 #define RADEON_BRUSH_Y_X                    0x1474
293 #define RADEON_BUS_CNTL                     0x0030
303 #define RADEON_BUS_CNTL1                    0x0034
305 #define RV370_BUS_CNTL                      0x004c
308 #define RADEON_MSI_REARM_EN		    0x0160
309 #	define RV370_MSI_REARM_EN	     (1 << 0)
311 /* #define RADEON_PCIE_INDEX                   0x0030 */
312 /* #define RADEON_PCIE_DATA                    0x0034 */
313 #define RADEON_PCIE_LC_LINK_WIDTH_CNTL             0xa2 /* PCIE */
314 #       define RADEON_PCIE_LC_LINK_WIDTH_SHIFT     0
315 #       define RADEON_PCIE_LC_LINK_WIDTH_MASK      0x7
316 #       define RADEON_PCIE_LC_LINK_WIDTH_X0        0
324 #       define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK   0x70
335 #define R600_TARGET_AND_CURRENT_PROFILE_INDEX      0x70c
336 #define R700_TARGET_AND_CURRENT_PROFILE_INDEX      0x66c
338 #define RADEON_CACHE_CNTL                   0x1724
339 #define RADEON_CACHE_LINE                   0x0f0c /* PCI */
340 #define RADEON_CAPABILITIES_ID              0x0f50 /* PCI */
341 #define RADEON_CAPABILITIES_PTR             0x0f34 /* PCI */
342 #define RADEON_CLK_PIN_CNTL                 0x0001 /* PLL */
345 #define RADEON_CLOCK_CNTL_DATA              0x000c
346 #define RADEON_CLOCK_CNTL_INDEX             0x0008
350 #define RADEON_CLK_PWRMGT_CNTL              0x0014
358 #       define RADEON_CG_NO1_DEBUG_MASK     (0x1f << 24)
362 #define RADEON_PLL_PWRMGT_CNTL              0x0015 /* PLL */
365 #define RADEON_CLR_CMP_CLR_3D               0x1a24
366 #define RADEON_CLR_CMP_CLR_DST              0x15c8
367 #define RADEON_CLR_CMP_CLR_SRC              0x15c4
368 #define RADEON_CLR_CMP_CNTL                 0x15c0
369 #       define RADEON_SRC_CMP_EQ_COLOR      (4 <<  0)
370 #       define RADEON_SRC_CMP_NEQ_COLOR     (5 <<  0)
372 #define RADEON_CLR_CMP_MASK                 0x15cc
373 #       define RADEON_CLR_CMP_MSK           0xffffffff
374 #define RADEON_CLR_CMP_MASK_3D              0x1A28
375 #define RADEON_COMMAND                      0x0f04 /* PCI */
376 #define RADEON_COMPOSITE_SHADOW_ID          0x1a0c
377 #define RADEON_CONFIG_APER_0_BASE           0x0100
378 #define RADEON_CONFIG_APER_1_BASE           0x0104
379 #define RADEON_CONFIG_APER_SIZE             0x0108
380 #define RADEON_CONFIG_BONDS                 0x00e8
381 #define RADEON_CONFIG_CNTL                  0x00e0
384 #       define RADEON_CFG_ATI_REV_A11       (0   << 16)
387 #       define RADEON_CFG_ATI_REV_ID_MASK   (0xf << 16)
388 #define RADEON_CONFIG_MEMSIZE               0x00f8
389 #define RADEON_CONFIG_MEMSIZE_EMBEDDED      0x0114
390 #define RADEON_CONFIG_REG_1_BASE            0x010c
391 #define RADEON_CONFIG_REG_APER_SIZE         0x0110
392 #define RADEON_CONFIG_XSTRAP                0x00e4
393 #define RADEON_CONSTANT_COLOR_C             0x1d34
394 #       define RADEON_CONSTANT_COLOR_MASK   0x00ffffff
395 #       define RADEON_CONSTANT_COLOR_ONE    0x00ffffff
396 #       define RADEON_CONSTANT_COLOR_ZERO   0x00000000
397 #define RADEON_CRC_CMDFIFO_ADDR             0x0740
398 #define RADEON_CRC_CMDFIFO_DOUT             0x0744
399 #define RADEON_GRPH_BUFFER_CNTL             0x02f0
400 #       define RADEON_GRPH_START_REQ_MASK          (0x7f)
401 #       define RADEON_GRPH_START_REQ_SHIFT         0
402 #       define RADEON_GRPH_STOP_REQ_MASK           (0x7f<<8)
404 #       define RADEON_GRPH_CRITICAL_POINT_MASK     (0x7f<<16)
410 #define RADEON_GRPH2_BUFFER_CNTL            0x03f0
411 #       define RADEON_GRPH2_START_REQ_MASK         (0x7f)
412 #       define RADEON_GRPH2_START_REQ_SHIFT         0
413 #       define RADEON_GRPH2_STOP_REQ_MASK          (0x7f<<8)
415 #       define RADEON_GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)
421 #define RADEON_CRTC_CRNT_FRAME              0x0214
422 #define RADEON_CRTC_EXT_CNTL                0x0054
423 #       define RADEON_CRTC_VGA_XOVERSCAN    (1 <<  0)
431 #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE      0x0055
432 #       define RADEON_CRTC_HSYNC_DIS_BYTE   (1 <<  0)
435 #define RADEON_CRTC_GEN_CNTL                0x0050
436 #       define RADEON_CRTC_DBL_SCAN_EN      (1 <<  0)
444 #       define RADEON_CRTC_CUR_MODE_MONO    0
449 #define RADEON_CRTC2_GEN_CNTL               0x03f8
450 #       define RADEON_CRTC2_DBL_SCAN_EN     (1 <<  0)
457 #       define RADEON_CRTC2_PIX_WIDTH_MASK  (0xf << 8)
467 #define RADEON_CRTC_MORE_CNTL               0x27c
472 #define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
473 #define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
474 #       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
475 #       define RADEON_CRTC_H_SYNC_STRT_CHAR       (0x3ff <<  3)
477 #       define RADEON_CRTC_H_SYNC_WID             (0x3f  << 16)
480 #define RADEON_CRTC2_H_SYNC_STRT_WID        0x0304
481 #       define RADEON_CRTC2_H_SYNC_STRT_PIX        (0x07  <<  0)
482 #       define RADEON_CRTC2_H_SYNC_STRT_CHAR       (0x3ff <<  3)
484 #       define RADEON_CRTC2_H_SYNC_WID             (0x3f  << 16)
487 #define RADEON_CRTC_H_TOTAL_DISP            0x0200
488 #       define RADEON_CRTC_H_TOTAL          (0x03ff << 0)
489 #       define RADEON_CRTC_H_TOTAL_SHIFT    0
490 #       define RADEON_CRTC_H_DISP           (0x01ff << 16)
492 #define RADEON_CRTC2_H_TOTAL_DISP           0x0300
493 #       define RADEON_CRTC2_H_TOTAL         (0x03ff << 0)
494 #       define RADEON_CRTC2_H_TOTAL_SHIFT   0
495 #       define RADEON_CRTC2_H_DISP          (0x01ff << 16)
498 #define RADEON_CRTC_OFFSET_RIGHT	    0x0220
499 #define RADEON_CRTC_OFFSET                  0x0224
503 #define RADEON_CRTC2_OFFSET                 0x0324
506 #define RADEON_CRTC_OFFSET_CNTL             0x0228
507 #       define RADEON_CRTC_TILE_LINE_SHIFT              0
511 #	define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO   (0 << 7)
517 #	define R300_CRTC_MICRO_TILE_BUFFER_AUTO		(0 << 10)
532 #define R300_CRTC_TILE_X0_Y0	            0x0350
533 #define R300_CRTC2_TILE_X0_Y0	            0x0358
535 #define RADEON_CRTC2_OFFSET_CNTL            0x0328
538 #define RADEON_CRTC_PITCH                   0x022c
539 #	define RADEON_CRTC_PITCH__SHIFT		 0
542 #define RADEON_CRTC2_PITCH                  0x032c
543 #define RADEON_CRTC_STATUS                  0x005c
544 #       define RADEON_CRTC_VBLANK_CUR       (1 <<  0)
547 #define RADEON_CRTC2_STATUS                  0x03fc
548 #       define RADEON_CRTC2_VBLANK_CUR       (1 <<  0)
551 #define RADEON_CRTC_V_SYNC_STRT_WID         0x020c
552 #       define RADEON_CRTC_V_SYNC_STRT        (0x7ff <<  0)
553 #       define RADEON_CRTC_V_SYNC_STRT_SHIFT  0
554 #       define RADEON_CRTC_V_SYNC_WID         (0x1f  << 16)
557 #define RADEON_CRTC2_V_SYNC_STRT_WID        0x030c
558 #       define RADEON_CRTC2_V_SYNC_STRT       (0x7ff <<  0)
559 #       define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
560 #       define RADEON_CRTC2_V_SYNC_WID        (0x1f  << 16)
563 #define RADEON_CRTC_V_TOTAL_DISP            0x0208
564 #       define RADEON_CRTC_V_TOTAL          (0x07ff << 0)
565 #       define RADEON_CRTC_V_TOTAL_SHIFT    0
566 #       define RADEON_CRTC_V_DISP           (0x07ff << 16)
568 #define RADEON_CRTC2_V_TOTAL_DISP           0x0308
569 #       define RADEON_CRTC2_V_TOTAL         (0x07ff << 0)
570 #       define RADEON_CRTC2_V_TOTAL_SHIFT   0
571 #       define RADEON_CRTC2_V_DISP          (0x07ff << 16)
573 #define RADEON_CRTC_VLINE_CRNT_VLINE        0x0210
574 #       define RADEON_CRTC_CRNT_VLINE_MASK  (0x7ff << 16)
575 #define RADEON_CRTC2_CRNT_FRAME             0x0314
576 #define RADEON_CRTC2_GUI_TRIG_VLINE         0x0318
577 #define RADEON_CRTC2_VLINE_CRNT_VLINE       0x0310
578 #define RADEON_CRTC8_DATA                   0x03d5 /* VGA, 0x3b5 */
579 #define RADEON_CRTC8_IDX                    0x03d4 /* VGA, 0x3b4 */
580 #define RADEON_CUR_CLR0                     0x026c
581 #define RADEON_CUR_CLR1                     0x0270
582 #define RADEON_CUR_HORZ_VERT_OFF            0x0268
583 #define RADEON_CUR_HORZ_VERT_POSN           0x0264
584 #define RADEON_CUR_OFFSET                   0x0260
586 #define RADEON_CUR2_CLR0                    0x036c
587 #define RADEON_CUR2_CLR1                    0x0370
588 #define RADEON_CUR2_HORZ_VERT_OFF           0x0368
589 #define RADEON_CUR2_HORZ_VERT_POSN          0x0364
590 #define RADEON_CUR2_OFFSET                  0x0360
593 #define RADEON_DAC_CNTL                     0x0058
594 #       define RADEON_DAC_RANGE_CNTL        (3 <<  0)
595 #       define RADEON_DAC_RANGE_CNTL_PS2    (2 <<  0)
596 #       define RADEON_DAC_RANGE_CNTL_MASK   0x03
604 #       define RADEON_DAC_MASK_ALL          (0xff << 24)
605 #define RADEON_DAC_CNTL2                    0x007c
606 #       define RADEON_DAC2_TV_CLK_SEL       (0 <<  1)
607 #       define RADEON_DAC2_DAC_CLK_SEL      (1 <<  0)
615 #define RADEON_DAC_EXT_CNTL                 0x0280
616 #       define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
621 #       define RADEON_DAC_FORCE_DATA_SEL_R    (0 << 6)
625 #       define RADEON_DAC_FORCE_DATA_MASK   0x0003ff00
627 #define RADEON_DAC_MACRO_CNTL               0x0d04
631 #define RADEON_DISP_PWR_MAN                 0x0d08
632 #       define RADEON_DISP_PWR_MAN_D3_CRTC_EN      (1 << 0)
634 #       define RADEON_DISP_PWR_MAN_DPMS_ON  (0 << 8)
649 #define RADEON_TV_DAC_CNTL                  0x088c
650 #       define RADEON_TV_DAC_NBLANK         (1 << 0)
656 #       define RADEON_TV_DAC_STD_PAL        (0 <<  8)
661 #       define RADEON_TV_DAC_BGADJ_MASK     (0xf <<  16)
663 #       define RADEON_TV_DAC_DACADJ_MASK    (0xf <<  20)
671 #       define R420_TV_DAC_DACADJ_MASK      (0x1f <<  20)
676 #define RADEON_DISP_HW_DEBUG                0x0d14
678 #define RADEON_DISP_OUTPUT_CNTL             0x0d64
679 #       define RADEON_DISP_DAC_SOURCE_MASK  0x03
680 #       define RADEON_DISP_DAC2_SOURCE_MASK  0x0c
681 #       define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
682 #       define RADEON_DISP_DAC_SOURCE_RMX   0x02
683 #       define RADEON_DISP_DAC_SOURCE_LTU   0x03
684 #       define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
685 #       define RADEON_DISP_TVDAC_SOURCE_MASK  (0x03 << 2)
686 #       define RADEON_DISP_TVDAC_SOURCE_CRTC  0x0
687 #       define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
688 #       define RADEON_DISP_TVDAC_SOURCE_RMX   (0x02 << 2)
689 #       define RADEON_DISP_TVDAC_SOURCE_LTU   (0x03 << 2)
690 #       define RADEON_DISP_TRANS_MATRIX_MASK  (0x03 << 4)
691 #       define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
692 #       define RADEON_DISP_TRANS_MATRIX_GRAPHICS  (0x01 << 4)
693 #       define RADEON_DISP_TRANS_MATRIX_VIDEO     (0x02 << 4)
695 #       define RADEON_DISP_TV_SOURCE_LTU    (0 << 16) /* linear transform unit */
696 #define RADEON_DISP_TV_OUT_CNTL             0x0d6c
698 #       define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
699 #define RADEON_DAC_CRC_SIG                  0x02cc
700 #define RADEON_DAC_DATA                     0x03c9 /* VGA */
701 #define RADEON_DAC_MASK                     0x03c6 /* VGA */
702 #define RADEON_DAC_R_INDEX                  0x03c7 /* VGA */
703 #define RADEON_DAC_W_INDEX                  0x03c8 /* VGA */
704 #define RADEON_DDA_CONFIG                   0x02e0
705 #define RADEON_DDA_ON_OFF                   0x02e4
706 #define RADEON_DEFAULT_OFFSET               0x16e0
707 #define RADEON_DEFAULT_PITCH                0x16e4
708 #define RADEON_DEFAULT_SC_BOTTOM_RIGHT      0x16e8
709 #       define RADEON_DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)
710 #       define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
711 #define RADEON_DESTINATION_3D_CLR_CMP_VAL   0x1820
712 #define RADEON_DESTINATION_3D_CLR_CMP_MSK   0x1824
713 #define RADEON_DEVICE_ID                    0x0f02 /* PCI */
714 #define RADEON_DISP_MISC_CNTL               0x0d00
715 #       define RADEON_SOFT_RESET_GRPH_PP    (1 << 0)
716 #define RADEON_DISP_MERGE_CNTL		  0x0d60
717 #       define RADEON_DISP_ALPHA_MODE_MASK  0x03
718 #       define RADEON_DISP_ALPHA_MODE_KEY   0
722 #       define RADEON_DISP_GRPH_ALPHA_MASK  (0xff << 16)
723 #       define RADEON_DISP_OV0_ALPHA_MASK   (0xff << 24)
724 #	define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
725 #define RADEON_DISP2_MERGE_CNTL		    0x0d68
727 #define RADEON_DISP_LIN_TRANS_GRPH_A        0x0d80
728 #define RADEON_DISP_LIN_TRANS_GRPH_B        0x0d84
729 #define RADEON_DISP_LIN_TRANS_GRPH_C        0x0d88
730 #define RADEON_DISP_LIN_TRANS_GRPH_D        0x0d8c
731 #define RADEON_DISP_LIN_TRANS_GRPH_E        0x0d90
732 #define RADEON_DISP_LIN_TRANS_GRPH_F        0x0d98
733 #define RADEON_DP_BRUSH_BKGD_CLR            0x1478
734 #define RADEON_DP_BRUSH_FRGD_CLR            0x147c
735 #define RADEON_DP_CNTL                      0x16c0
736 #       define RADEON_DST_X_LEFT_TO_RIGHT   (1 <<  0)
738 #       define RADEON_DP_DST_TILE_LINEAR    (0 <<  3)
742 #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0
746 #define RADEON_DP_DATATYPE                  0x16c4
748 #define RADEON_DP_GUI_MASTER_CNTL           0x146c
749 #       define RADEON_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
753 #       define RADEON_GMC_BRUSH_DATATYPE_MASK     (0x0f <<  4)
754 #       define RADEON_GMC_BRUSH_8X8_MONO_FG_BG    (0    <<  4)
778 #       define RADEON_GMC_DST_DATATYPE_MASK       (0x0f <<  8)
781 #       define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)
785 #       define RADEON_GMC_BYTE_MSB_TO_LSB         (0    << 14)
788 #       define RADEON_GMC_CONVERSION_TEMP_6500    (0    << 15)
790 #       define RADEON_GMC_ROP3_MASK               (0xff << 16)
799 #       define RADEON_ROP3_ZERO             0x00000000
800 #       define RADEON_ROP3_DSa              0x00880000
801 #       define RADEON_ROP3_SDna             0x00440000
802 #       define RADEON_ROP3_S                0x00cc0000
803 #       define RADEON_ROP3_DSna             0x00220000
804 #       define RADEON_ROP3_D                0x00aa0000
805 #       define RADEON_ROP3_DSx              0x00660000
806 #       define RADEON_ROP3_DSo              0x00ee0000
807 #       define RADEON_ROP3_DSon             0x00110000
808 #       define RADEON_ROP3_DSxn             0x00990000
809 #       define RADEON_ROP3_Dn               0x00550000
810 #       define RADEON_ROP3_SDno             0x00dd0000
811 #       define RADEON_ROP3_Sn               0x00330000
812 #       define RADEON_ROP3_DSno             0x00bb0000
813 #       define RADEON_ROP3_DSan             0x00770000
814 #       define RADEON_ROP3_ONE              0x00ff0000
815 #       define RADEON_ROP3_DPa              0x00a00000
816 #       define RADEON_ROP3_PDna             0x00500000
817 #       define RADEON_ROP3_P                0x00f00000
818 #       define RADEON_ROP3_DPna             0x000a0000
819 #       define RADEON_ROP3_D                0x00aa0000
820 #       define RADEON_ROP3_DPx              0x005a0000
821 #       define RADEON_ROP3_DPo              0x00fa0000
822 #       define RADEON_ROP3_DPon             0x00050000
823 #       define RADEON_ROP3_PDxn             0x00a50000
824 #       define RADEON_ROP3_PDno             0x00f50000
825 #       define RADEON_ROP3_Pn               0x000f0000
826 #       define RADEON_ROP3_DPno             0x00af0000
827 #       define RADEON_ROP3_DPan             0x005f0000
828 #define RADEON_DP_GUI_MASTER_CNTL_C         0x1c84
829 #define RADEON_DP_MIX                       0x16c8
830 #define RADEON_DP_SRC_BKGD_CLR              0x15dc
831 #define RADEON_DP_SRC_FRGD_CLR              0x15d8
832 #define RADEON_DP_WRITE_MASK                0x16cc
833 #define RADEON_DST_BRES_DEC                 0x1630
834 #define RADEON_DST_BRES_ERR                 0x1628
835 #define RADEON_DST_BRES_INC                 0x162c
836 #define RADEON_DST_BRES_LNTH                0x1634
837 #define RADEON_DST_BRES_LNTH_SUB            0x1638
838 #define RADEON_DST_HEIGHT                   0x1410
839 #define RADEON_DST_HEIGHT_WIDTH             0x143c
840 #define RADEON_DST_HEIGHT_WIDTH_8           0x158c
841 #define RADEON_DST_HEIGHT_WIDTH_BW          0x15b4
842 #define RADEON_DST_HEIGHT_Y                 0x15a0
843 #define RADEON_DST_LINE_START               0x1600
844 #define RADEON_DST_LINE_END                 0x1604
845 #define RADEON_DST_LINE_PATCOUNT            0x1608
847 #define RADEON_DST_OFFSET                   0x1404
848 #define RADEON_DST_PITCH                    0x1408
849 #define RADEON_DST_PITCH_OFFSET             0x142c
850 #define RADEON_DST_PITCH_OFFSET_C           0x1c80
852 #       define RADEON_DST_TILE_LINEAR       (0 << 30)
856 #define RADEON_DST_WIDTH                    0x140c
857 #define RADEON_DST_WIDTH_HEIGHT             0x1598
858 #define RADEON_DST_WIDTH_X                  0x1588
859 #define RADEON_DST_WIDTH_X_INCY             0x159c
860 #define RADEON_DST_X                        0x141c
861 #define RADEON_DST_X_SUB                    0x15a4
862 #define RADEON_DST_X_Y                      0x1594
863 #define RADEON_DST_Y                        0x1420
864 #define RADEON_DST_Y_SUB                    0x15a8
865 #define RADEON_DST_Y_X                      0x1438
867 #define RADEON_FCP_CNTL                     0x0910
868 #      define RADEON_FCP0_SRC_PCICLK             0
874 #define RADEON_FLUSH_1                      0x1704
875 #define RADEON_FLUSH_2                      0x1708
876 #define RADEON_FLUSH_3                      0x170c
877 #define RADEON_FLUSH_4                      0x1710
878 #define RADEON_FLUSH_5                      0x1714
879 #define RADEON_FLUSH_6                      0x1718
880 #define RADEON_FLUSH_7                      0x171c
881 #define RADEON_FOG_3D_TABLE_START           0x1810
882 #define RADEON_FOG_3D_TABLE_END             0x1814
883 #define RADEON_FOG_3D_TABLE_DENSITY         0x181c
884 #define RADEON_FOG_TABLE_INDEX              0x1a14
885 #define RADEON_FOG_TABLE_DATA               0x1a18
886 #define RADEON_FP_CRTC_H_TOTAL_DISP         0x0250
887 #define RADEON_FP_CRTC_V_TOTAL_DISP         0x0254
888 #       define RADEON_FP_CRTC_H_TOTAL_MASK      0x000003ff
889 #       define RADEON_FP_CRTC_H_DISP_MASK       0x01ff0000
890 #       define RADEON_FP_CRTC_V_TOTAL_MASK      0x00000fff
891 #       define RADEON_FP_CRTC_V_DISP_MASK       0x0fff0000
892 #       define RADEON_FP_H_SYNC_STRT_CHAR_MASK  0x00001ff8
893 #       define RADEON_FP_H_SYNC_WID_MASK        0x003f0000
894 #       define RADEON_FP_V_SYNC_STRT_MASK       0x00000fff
895 #       define RADEON_FP_V_SYNC_WID_MASK        0x001f0000
896 #       define RADEON_FP_CRTC_H_TOTAL_SHIFT     0x00000000
897 #       define RADEON_FP_CRTC_H_DISP_SHIFT      0x00000010
898 #       define RADEON_FP_CRTC_V_TOTAL_SHIFT     0x00000000
899 #       define RADEON_FP_CRTC_V_DISP_SHIFT      0x00000010
900 #       define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
901 #       define RADEON_FP_H_SYNC_WID_SHIFT       0x00000010
902 #       define RADEON_FP_V_SYNC_STRT_SHIFT      0x00000000
903 #       define RADEON_FP_V_SYNC_WID_SHIFT       0x00000010
904 #define RADEON_FP_GEN_CNTL                  0x0284
905 #       define RADEON_FP_FPON                  (1 <<  0)
913 #       define R200_FP_SOURCE_SEL_CRTC1        (0 <<  10)
917 #       define RADEON_FP_SEL_CRTC1             (0 << 13)
930 #define RADEON_FP2_GEN_CNTL                 0x0288
937 #       define R200_FP2_SOURCE_SEL_CRTC1       (0 << 10)
955 #define RADEON_FP_H_SYNC_STRT_WID           0x02c4
956 #define RADEON_FP_H2_SYNC_STRT_WID          0x03c4
957 #define RADEON_FP_HORZ_STRETCH              0x028c
958 #define RADEON_FP_HORZ2_STRETCH             0x038c
959 #       define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
961 #       define RADEON_HORZ_PANEL_SIZE         (0x1ff   << 16)
963 #       define RADEON_HORZ_STRETCH_PIXREP     (0      << 25)
967 #       define RADEON_HORZ_FP_LOOP_STRETCH    (0x7    << 28)
969 #define RADEON_FP_HORZ_VERT_ACTIVE          0x0278
970 #define RADEON_FP_V_SYNC_STRT_WID           0x02c8
971 #define RADEON_FP_VERT_STRETCH              0x0290
972 #define RADEON_FP_V2_SYNC_STRT_WID          0x03c8
973 #define RADEON_FP_VERT2_STRETCH             0x0390
974 #       define RADEON_VERT_PANEL_SIZE          (0xfff << 12)
976 #       define RADEON_VERT_STRETCH_RATIO_MASK  0xfff
977 #       define RADEON_VERT_STRETCH_RATIO_SHIFT 0
980 #       define RADEON_VERT_STRETCH_LINEREP     (0     << 26)
984 #       define RADEON_VERT_STRETCH_RESERVED    0x71000000
985 #define RS400_FP_2ND_GEN_CNTL               0x0384
986 #       define RS400_FP_2ND_ON              (1 << 0)
993 #       define RS400_FP_2ND_SOURCE_SEL_CRTC1       (0 << 10)
998 #define RS400_FP2_2_GEN_CNTL                0x0388
1004 #       define RS400_FP2_2_SOURCE_SEL_CRTC1       (0 << 10)
1008 #define RS400_TMDS2_CNTL                    0x0394
1009 #define RS400_TMDS2_TRANSMITTER_CNTL        0x03a4
1010 #       define RS400_TMDS2_PLLEN            (1 << 0)
1013 #define RADEON_GEN_INT_CNTL                 0x0040
1014 #	define RADEON_CRTC_VBLANK_MASK		(1 << 0)
1020 #define RADEON_GEN_INT_STATUS               0x0044
1021 #	define AVIVO_DISPLAY_INT_STATUS		(1 << 0)
1022 #	define RADEON_CRTC_VBLANK_STAT		(1 << 0)
1023 #	define RADEON_CRTC_VBLANK_STAT_ACK	(1 << 0)
1035 #define RADEON_GENENB                       0x03c3 /* VGA */
1036 #define RADEON_GENFC_RD                     0x03ca /* VGA */
1037 #define RADEON_GENFC_WT                     0x03da /* VGA, 0x03ba */
1038 #define RADEON_GENMO_RD                     0x03cc /* VGA */
1039 #define RADEON_GENMO_WT                     0x03c2 /* VGA */
1040 #define RADEON_GENS0                        0x03c2 /* VGA */
1041 #define RADEON_GENS1                        0x03da /* VGA, 0x03ba */
1042 #define RADEON_GPIO_MONID                   0x0068 /* DDC interface via I2C */ /* DDC3 */
1043 #define RADEON_GPIO_MONIDB                  0x006c
1044 #define RADEON_GPIO_CRT2_DDC                0x006c
1045 #define RADEON_GPIO_DVI_DDC                 0x0064 /* DDC2 */
1046 #define RADEON_GPIO_VGA_DDC                 0x0060 /* DDC1 */
1047 #       define RADEON_GPIO_A_0              (1 <<  0)
1057 #define RADEON_GRPH8_DATA                   0x03cf /* VGA */
1058 #define RADEON_GRPH8_IDX                    0x03ce /* VGA */
1059 #define RADEON_GUI_SCRATCH_REG0             0x15e0
1060 #define RADEON_GUI_SCRATCH_REG1             0x15e4
1061 #define RADEON_GUI_SCRATCH_REG2             0x15e8
1062 #define RADEON_GUI_SCRATCH_REG3             0x15ec
1063 #define RADEON_GUI_SCRATCH_REG4             0x15f0
1064 #define RADEON_GUI_SCRATCH_REG5             0x15f4
1066 #define RADEON_HEADER                       0x0f0e /* PCI */
1067 #define RADEON_HOST_DATA0                   0x17c0
1068 #define RADEON_HOST_DATA1                   0x17c4
1069 #define RADEON_HOST_DATA2                   0x17c8
1070 #define RADEON_HOST_DATA3                   0x17cc
1071 #define RADEON_HOST_DATA4                   0x17d0
1072 #define RADEON_HOST_DATA5                   0x17d4
1073 #define RADEON_HOST_DATA6                   0x17d8
1074 #define RADEON_HOST_DATA7                   0x17dc
1075 #define RADEON_HOST_DATA_LAST               0x17e0
1076 #define RADEON_HOST_PATH_CNTL               0x0130
1081 #define RADEON_HTOTAL_CNTL                  0x0009 /* PLL */
1083 #define RADEON_HTOTAL2_CNTL                 0x002e /* PLL */
1086 #define RADEON_I2C_CNTL_0		    0x0090
1087 #       define RADEON_I2C_DONE              (1 << 0)
1099 #define RADEON_I2C_CNTL_1                   0x0094
1100 #       define RADEON_I2C_DATA_COUNT_SHIFT  0
1106 #define RADEON_I2C_DATA			    0x0098
1108 #define RADEON_DVI_I2C_CNTL_0		    0x02e0
1110 #       define R200_SEL_DDC1                0 /* depends on asic */
1119 #define RADEON_DVI_I2C_CNTL_1               0x02e4
1120 #define RADEON_DVI_I2C_DATA		    0x02e8
1122 #define RADEON_INTERRUPT_LINE               0x0f3c /* PCI */
1123 #define RADEON_INTERRUPT_PIN                0x0f3d /* PCI */
1124 #define RADEON_IO_BASE                      0x0f14 /* PCI */
1126 #define RADEON_LATENCY                      0x0f0d /* PCI */
1127 #define RADEON_LEAD_BRES_DEC                0x1608
1128 #define RADEON_LEAD_BRES_LNTH               0x161c
1129 #define RADEON_LEAD_BRES_LNTH_SUB           0x1624
1130 #define RADEON_LVDS_GEN_CNTL                0x02d0
1131 #       define RADEON_LVDS_ON               (1   <<  0)
1135 #       define RADEON_LVDS_NO_FM            (0   <<  4)
1141 #       define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1152 #define RADEON_LVDS_PLL_CNTL                0x02d4
1154 #       define RADEON_HSYNC_DELAY_MASK      (0xf << 28)
1158 #       define R300_LVDS_SRC_SEL_CRTC1      (0   << 18)
1161 #define RADEON_LVDS_SS_GEN_CNTL             0x02ec
1165 #define RADEON_MAX_LATENCY                  0x0f3f /* PCI */
1166 #define RADEON_DISPLAY_BASE_ADDR            0x23c
1167 #define RADEON_DISPLAY2_BASE_ADDR           0x33c
1168 #define RADEON_OV0_BASE_ADDR                0x43c
1169 #define RADEON_NB_TOM                       0x15c
1170 #define R300_MC_INIT_MISC_LAT_TIMER         0x180
1172 #       define R300_MC_DISP0R_INIT_LAT_MASK  0xf
1174 #       define R300_MC_DISP1R_INIT_LAT_MASK  0xf
1175 #define RADEON_MCLK_CNTL                    0x0012 /* PLL */
1176 #       define RADEON_MCLKA_SRC_SEL_MASK    0x7
1185 #define RADEON_MCLK_MISC                    0x001f /* PLL */
1191 #define RADEON_GPIOPAD_MASK                 0x0198
1192 #define RADEON_GPIOPAD_A		    0x019c
1193 #define RADEON_GPIOPAD_EN                   0x01a0
1194 #define RADEON_GPIOPAD_Y                    0x01a4
1195 #define RADEON_MDGPIO_MASK                  0x01a8
1196 #define RADEON_MDGPIO_A                     0x01ac
1197 #define RADEON_MDGPIO_EN                    0x01b0
1198 #define RADEON_MDGPIO_Y                     0x01b4
1200 #define RADEON_MEM_ADDR_CONFIG              0x0148
1201 #define RADEON_MEM_BASE                     0x0f10 /* PCI */
1202 #define RADEON_MEM_CNTL                     0x0140
1203 #       define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1206 #       define R300_MEM_NUM_CHANNELS_MASK   0x03
1208 #define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
1209 #define RADEON_MEM_INIT_LAT_TIMER           0x0154
1210 #define RADEON_MEM_INTF_CNTL                0x014c
1211 #define RADEON_MEM_SDRAM_MODE_REG           0x0158
1212 #       define RADEON_SDRAM_MODE_MASK       0xffff0000
1213 #       define RADEON_B3MEM_RESET_MASK      0x6fffffff
1215 #define RADEON_MEM_STR_CNTL                 0x0150
1216 #       define RADEON_MEM_PWRUP_COMPL_A     (1 <<  0)
1220 #       define RADEON_MEM_PWRUP_COMPLETE    0x03
1221 #       define R300_MEM_PWRUP_COMPLETE      0x0f
1222 #define RADEON_MC_STATUS                    0x0150
1225 #define RADEON_MEM_VGA_RP_SEL               0x003c
1226 #define RADEON_MEM_VGA_WP_SEL               0x0038
1227 #define RADEON_MIN_GRANT                    0x0f3e /* PCI */
1228 #define RADEON_MM_DATA                      0x0004
1229 #define RADEON_MM_INDEX                     0x0000
1231 #define RADEON_MPLL_CNTL                    0x000e /* PLL */
1232 #define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */
1233 #define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */
1234 #define RADEON_SEPROM_CNTL1                 0x01c0
1236 #       define RADEON_SCK_PRESCALE_MASK     (0xff << 24)
1237 #define R300_MC_IND_INDEX                   0x01f8
1238 #       define R300_MC_IND_ADDR_MASK        0x3f
1240 #define R300_MC_IND_DATA                    0x01fc
1241 #define R300_MC_READ_CNTL_AB                0x017c
1242 #       define R300_MEM_RBS_POSITION_A_MASK 0x03
1243 #define R300_MC_READ_CNTL_CD_mcind	    0x24
1244 #       define R300_MEM_RBS_POSITION_C_MASK 0x03
1246 #define RADEON_N_VIF_COUNT                  0x0248
1248 #define RADEON_OV0_AUTO_FLIP_CNTL           0x0470
1249 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM        0x00000007
1250 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD   0x00000008
1251 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD        0x00000010
1252 #       define  RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
1253 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE     0x00000040
1254 #       define  RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT     0x00000300
1255 #       define  RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN  0x00010000
1256 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN     0x00040000
1257 #       define  RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN      0x00080000
1258 #       define  RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE    0x00800000
1260 #define RADEON_OV0_COLOUR_CNTL              0x04E0
1261 #define RADEON_OV0_DEINTERLACE_PATTERN      0x0474
1262 #define RADEON_OV0_EXCLUSIVE_HORZ           0x0408
1263 #       define  RADEON_EXCL_HORZ_START_MASK        0x000000ff
1264 #       define  RADEON_EXCL_HORZ_END_MASK          0x0000ff00
1265 #       define  RADEON_EXCL_HORZ_BACK_PORCH_MASK   0x00ff0000
1266 #       define  RADEON_EXCL_HORZ_EXCLUSIVE_EN      0x80000000
1267 #define RADEON_OV0_EXCLUSIVE_VERT           0x040C
1268 #       define  RADEON_EXCL_VERT_START_MASK        0x000003ff
1269 #       define  RADEON_EXCL_VERT_END_MASK          0x03ff0000
1270 #define RADEON_OV0_FILTER_CNTL              0x04A0
1271 #       define RADEON_FILTER_PROGRAMMABLE_COEF            0x0
1272 #       define RADEON_FILTER_HC_COEF_HORZ_Y               0x1
1273 #       define RADEON_FILTER_HC_COEF_HORZ_UV              0x2
1274 #       define RADEON_FILTER_HC_COEF_VERT_Y               0x4
1275 #       define RADEON_FILTER_HC_COEF_VERT_UV              0x8
1276 #       define RADEON_FILTER_HARDCODED_COEF               0xf
1277 #       define RADEON_FILTER_COEF_MASK                    0xf
1279 #define RADEON_OV0_FOUR_TAP_COEF_0          0x04B0
1280 #define RADEON_OV0_FOUR_TAP_COEF_1          0x04B4
1281 #define RADEON_OV0_FOUR_TAP_COEF_2          0x04B8
1282 #define RADEON_OV0_FOUR_TAP_COEF_3          0x04BC
1283 #define RADEON_OV0_FOUR_TAP_COEF_4          0x04C0
1284 #define RADEON_OV0_FLAG_CNTL                0x04DC
1285 #define RADEON_OV0_GAMMA_000_00F            0x0d40
1286 #define RADEON_OV0_GAMMA_010_01F            0x0d44
1287 #define RADEON_OV0_GAMMA_020_03F            0x0d48
1288 #define RADEON_OV0_GAMMA_040_07F            0x0d4c
1289 #define RADEON_OV0_GAMMA_080_0BF            0x0e00
1290 #define RADEON_OV0_GAMMA_0C0_0FF            0x0e04
1291 #define RADEON_OV0_GAMMA_100_13F            0x0e08
1292 #define RADEON_OV0_GAMMA_140_17F            0x0e0c
1293 #define RADEON_OV0_GAMMA_180_1BF            0x0e10
1294 #define RADEON_OV0_GAMMA_1C0_1FF            0x0e14
1295 #define RADEON_OV0_GAMMA_200_23F            0x0e18
1296 #define RADEON_OV0_GAMMA_240_27F            0x0e1c
1297 #define RADEON_OV0_GAMMA_280_2BF            0x0e20
1298 #define RADEON_OV0_GAMMA_2C0_2FF            0x0e24
1299 #define RADEON_OV0_GAMMA_300_33F            0x0e28
1300 #define RADEON_OV0_GAMMA_340_37F            0x0e2c
1301 #define RADEON_OV0_GAMMA_380_3BF            0x0d50
1302 #define RADEON_OV0_GAMMA_3C0_3FF            0x0d54
1303 #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW     0x04EC
1304 #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH    0x04F0
1305 #define RADEON_OV0_H_INC                    0x0480
1306 #define RADEON_OV0_KEY_CNTL                 0x04F4
1307 #       define  RADEON_VIDEO_KEY_FN_MASK    0x00000003L
1308 #       define  RADEON_VIDEO_KEY_FN_FALSE   0x00000000L
1309 #       define  RADEON_VIDEO_KEY_FN_TRUE    0x00000001L
1310 #       define  RADEON_VIDEO_KEY_FN_EQ      0x00000002L
1311 #       define  RADEON_VIDEO_KEY_FN_NE      0x00000003L
1312 #       define  RADEON_GRAPHIC_KEY_FN_MASK  0x00000030L
1313 #       define  RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1314 #       define  RADEON_GRAPHIC_KEY_FN_TRUE  0x00000010L
1315 #       define  RADEON_GRAPHIC_KEY_FN_EQ    0x00000020L
1316 #       define  RADEON_GRAPHIC_KEY_FN_NE    0x00000030L
1317 #       define  RADEON_CMP_MIX_MASK         0x00000100L
1318 #       define  RADEON_CMP_MIX_OR           0x00000000L
1319 #       define  RADEON_CMP_MIX_AND          0x00000100L
1320 #define RADEON_OV0_LIN_TRANS_A              0x0d20
1321 #define RADEON_OV0_LIN_TRANS_B              0x0d24
1322 #define RADEON_OV0_LIN_TRANS_C              0x0d28
1323 #define RADEON_OV0_LIN_TRANS_D              0x0d2c
1324 #define RADEON_OV0_LIN_TRANS_E              0x0d30
1325 #define RADEON_OV0_LIN_TRANS_F              0x0d34
1326 #define RADEON_OV0_P1_BLANK_LINES_AT_TOP    0x0430
1327 #       define  RADEON_P1_BLNK_LN_AT_TOP_M1_MASK   0x00000fffL
1328 #       define  RADEON_P1_ACTIVE_LINES_M1          0x0fff0000L
1329 #define RADEON_OV0_P1_H_ACCUM_INIT          0x0488
1330 #define RADEON_OV0_P1_V_ACCUM_INIT          0x0428
1331 #       define  RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1332 #       define  RADEON_OV0_P1_V_ACCUM_INIT_MASK    0x01ff8000L
1333 #define RADEON_OV0_P1_X_START_END           0x0494
1334 #define RADEON_OV0_P2_X_START_END           0x0498
1335 #define RADEON_OV0_P23_BLANK_LINES_AT_TOP   0x0434
1336 #       define  RADEON_P23_BLNK_LN_AT_TOP_M1_MASK  0x000007ffL
1337 #       define  RADEON_P23_ACTIVE_LINES_M1         0x07ff0000L
1338 #define RADEON_OV0_P23_H_ACCUM_INIT         0x048C
1339 #define RADEON_OV0_P23_V_ACCUM_INIT         0x042C
1340 #define RADEON_OV0_P3_X_START_END           0x049C
1341 #define RADEON_OV0_REG_LOAD_CNTL            0x0410
1342 #       define  RADEON_REG_LD_CTL_LOCK                 0x00000001L
1343 #       define  RADEON_REG_LD_CTL_VBLANK_DURING_LOCK   0x00000002L
1344 #       define  RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1345 #       define  RADEON_REG_LD_CTL_LOCK_READBACK        0x00000008L
1346 #       define  RADEON_REG_LD_CTL_FLIP_READBACK        0x00000010L
1347 #define RADEON_OV0_SCALE_CNTL               0x0420
1348 #       define  RADEON_SCALER_HORZ_PICK_NEAREST    0x00000004L
1349 #       define  RADEON_SCALER_VERT_PICK_NEAREST    0x00000008L
1350 #       define  RADEON_SCALER_SIGNED_UV            0x00000010L
1351 #       define  RADEON_SCALER_GAMMA_SEL_MASK       0x00000060L
1352 #       define  RADEON_SCALER_GAMMA_SEL_BRIGHT     0x00000000L
1353 #       define  RADEON_SCALER_GAMMA_SEL_G22        0x00000020L
1354 #       define  RADEON_SCALER_GAMMA_SEL_G18        0x00000040L
1355 #       define  RADEON_SCALER_GAMMA_SEL_G14        0x00000060L
1356 #       define  RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1357 #       define  RADEON_SCALER_SURFAC_FORMAT        0x00000f00L
1358 #       define  RADEON_SCALER_SOURCE_15BPP         0x00000300L
1359 #       define  RADEON_SCALER_SOURCE_16BPP         0x00000400L
1360 #       define  RADEON_SCALER_SOURCE_32BPP         0x00000600L
1361 #       define  RADEON_SCALER_SOURCE_YUV9          0x00000900L
1362 #       define  RADEON_SCALER_SOURCE_YUV12         0x00000A00L
1363 #       define  RADEON_SCALER_SOURCE_VYUY422       0x00000B00L
1364 #       define  RADEON_SCALER_SOURCE_YVYU422       0x00000C00L
1365 #       define  RADEON_SCALER_ADAPTIVE_DEINT       0x00001000L
1366 #       define  RADEON_SCALER_TEMPORAL_DEINT       0x00002000L
1367 #       define  RADEON_SCALER_CRTC_SEL             0x00004000L
1368 #       define  RADEON_SCALER_SMART_SWITCH         0x00008000L
1369 #       define  RADEON_SCALER_BURST_PER_PLANE      0x007F0000L
1370 #       define  RADEON_SCALER_DOUBLE_BUFFER        0x01000000L
1371 #       define  RADEON_SCALER_DIS_LIMIT            0x08000000L
1372 #       define  RADEON_SCALER_LIN_TRANS_BYPASS     0x10000000L
1373 #       define  RADEON_SCALER_INT_EMU              0x20000000L
1374 #       define  RADEON_SCALER_ENABLE               0x40000000L
1375 #       define  RADEON_SCALER_SOFT_RESET           0x80000000L
1376 #define RADEON_OV0_STEP_BY                  0x0484
1377 #define RADEON_OV0_TEST                     0x04F8
1378 #define RADEON_OV0_V_INC                    0x0424
1379 #define RADEON_OV0_VID_BUF_PITCH0_VALUE     0x0460
1380 #define RADEON_OV0_VID_BUF_PITCH1_VALUE     0x0464
1381 #define RADEON_OV0_VID_BUF0_BASE_ADRS       0x0440
1382 #       define  RADEON_VIF_BUF0_PITCH_SEL          0x00000001L
1383 #       define  RADEON_VIF_BUF0_TILE_ADRS          0x00000002L
1384 #       define  RADEON_VIF_BUF0_BASE_ADRS_MASK     0x03fffff0L
1385 #       define  RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
1386 #define RADEON_OV0_VID_BUF1_BASE_ADRS       0x0444
1387 #       define  RADEON_VIF_BUF1_PITCH_SEL          0x00000001L
1388 #       define  RADEON_VIF_BUF1_TILE_ADRS          0x00000002L
1389 #       define  RADEON_VIF_BUF1_BASE_ADRS_MASK     0x03fffff0L
1390 #       define  RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
1391 #define RADEON_OV0_VID_BUF2_BASE_ADRS       0x0448
1392 #       define  RADEON_VIF_BUF2_PITCH_SEL          0x00000001L
1393 #       define  RADEON_VIF_BUF2_TILE_ADRS          0x00000002L
1394 #       define  RADEON_VIF_BUF2_BASE_ADRS_MASK     0x03fffff0L
1395 #       define  RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
1396 #define RADEON_OV0_VID_BUF3_BASE_ADRS       0x044C
1397 #define RADEON_OV0_VID_BUF4_BASE_ADRS       0x0450
1398 #define RADEON_OV0_VID_BUF5_BASE_ADRS       0x0454
1399 #define RADEON_OV0_VIDEO_KEY_CLR_HIGH       0x04E8
1400 #define RADEON_OV0_VIDEO_KEY_CLR_LOW        0x04E4
1401 #define RADEON_OV0_Y_X_START                0x0400
1402 #define RADEON_OV0_Y_X_END                  0x0404
1403 #define RADEON_OV1_Y_X_START                0x0600
1404 #define RADEON_OV1_Y_X_END                  0x0604
1405 #define RADEON_OVR_CLR                      0x0230
1406 #define RADEON_OVR_WID_LEFT_RIGHT           0x0234
1407 #define RADEON_OVR_WID_TOP_BOTTOM           0x0238
1408 #define RADEON_OVR2_CLR                     0x0330
1409 #define RADEON_OVR2_WID_LEFT_RIGHT          0x0334
1410 #define RADEON_OVR2_WID_TOP_BOTTOM          0x0338
1414 #define RADEON_CAP0_BUF0_OFFSET           0x0920
1415 #define RADEON_CAP0_BUF1_OFFSET           0x0924
1416 #define RADEON_CAP0_BUF0_EVEN_OFFSET      0x0928
1417 #define RADEON_CAP0_BUF1_EVEN_OFFSET      0x092C
1419 #define RADEON_CAP0_BUF_PITCH             0x0930
1420 #define RADEON_CAP0_V_WINDOW              0x0934
1421 #define RADEON_CAP0_H_WINDOW              0x0938
1422 #define RADEON_CAP0_VBI0_OFFSET           0x093C
1423 #define RADEON_CAP0_VBI1_OFFSET           0x0940
1424 #define RADEON_CAP0_VBI_V_WINDOW          0x0944
1425 #define RADEON_CAP0_VBI_H_WINDOW          0x0948
1426 #define RADEON_CAP0_PORT_MODE_CNTL        0x094C
1427 #define RADEON_CAP0_TRIG_CNTL             0x0950
1428 #define RADEON_CAP0_DEBUG                 0x0954
1429 #define RADEON_CAP0_CONFIG                0x0958
1430 #       define RADEON_CAP0_CONFIG_CONTINUOS          0x00000001
1431 #       define RADEON_CAP0_CONFIG_START_FIELD_EVEN   0x00000002
1432 #       define RADEON_CAP0_CONFIG_START_BUF_GET      0x00000004
1433 #       define RADEON_CAP0_CONFIG_START_BUF_SET      0x00000008
1434 #       define RADEON_CAP0_CONFIG_BUF_TYPE_ALT       0x00000010
1435 #       define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME     0x00000020
1436 #       define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1437 #       define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE    0x00000080
1438 #       define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE    0x00000100
1439 #       define RADEON_CAP0_CONFIG_MIRROR_EN          0x00000200
1440 #       define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN  0x00000400
1441 #       define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV    0x00000800
1442 #       define RADEON_CAP0_CONFIG_ANC_DECODE_EN      0x00001000
1443 #       define RADEON_CAP0_CONFIG_VBI_EN             0x00002000
1444 #       define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN  0x00004000
1445 #       define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1446 #       define RADEON_CAP0_CONFIG_FAKE_FIELD_EN      0x00010000
1447 #       define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE  0x00020000
1448 #       define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1449 #       define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2      0x00080000
1450 #       define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4      0x00100000
1451 #       define RADEON_CAP0_CONFIG_VERT_DIVIDE_2      0x00200000
1452 #       define RADEON_CAP0_CONFIG_VERT_DIVIDE_4      0x00400000
1453 #       define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE   0x00000000
1454 #       define RADEON_CAP0_CONFIG_FORMAT_CCIR656     0x00800000
1455 #       define RADEON_CAP0_CONFIG_FORMAT_ZV          0x01000000
1456 #       define RADEON_CAP0_CONFIG_FORMAT_VIP         0x01800000
1457 #       define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT   0x02000000
1458 #       define RADEON_CAP0_CONFIG_HORZ_DECIMATOR     0x04000000
1459 #       define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422   0x00000000
1460 #       define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422   0x20000000
1461 #       define RADEON_CAP0_CONFIG_VBI_DIVIDE_2       0x40000000
1462 #       define RADEON_CAP0_CONFIG_VBI_DIVIDE_4       0x80000000
1463 #define RADEON_CAP0_ANC_ODD_OFFSET        0x095C
1464 #define RADEON_CAP0_ANC_EVEN_OFFSET       0x0960
1465 #define RADEON_CAP0_ANC_H_WINDOW          0x0964
1466 #define RADEON_CAP0_VIDEO_SYNC_TEST       0x0968
1467 #define RADEON_CAP0_ONESHOT_BUF_OFFSET    0x096C
1468 #define RADEON_CAP0_BUF_STATUS            0x0970
1469 /* #define RADEON_CAP0_DWNSC_XRATIO       0x0978 */
1470 /* #define RADEON_CAP0_XSHARPNESS                 0x097C */
1471 #define RADEON_CAP0_VBI2_OFFSET           0x0980
1472 #define RADEON_CAP0_VBI3_OFFSET           0x0984
1473 #define RADEON_CAP0_ANC2_OFFSET           0x0988
1474 #define RADEON_CAP0_ANC3_OFFSET           0x098C
1475 #define RADEON_VID_BUFFER_CONTROL         0x0900
1479 #define RADEON_CAP1_BUF0_OFFSET           0x0990
1480 #define RADEON_CAP1_BUF1_OFFSET           0x0994
1481 #define RADEON_CAP1_BUF0_EVEN_OFFSET      0x0998
1482 #define RADEON_CAP1_BUF1_EVEN_OFFSET      0x099C
1484 #define RADEON_CAP1_BUF_PITCH             0x09A0
1485 #define RADEON_CAP1_V_WINDOW              0x09A4
1486 #define RADEON_CAP1_H_WINDOW              0x09A8
1487 #define RADEON_CAP1_VBI_ODD_OFFSET        0x09AC
1488 #define RADEON_CAP1_VBI_EVEN_OFFSET       0x09B0
1489 #define RADEON_CAP1_VBI_V_WINDOW                  0x09B4
1490 #define RADEON_CAP1_VBI_H_WINDOW                  0x09B8
1491 #define RADEON_CAP1_PORT_MODE_CNTL        0x09BC
1492 #define RADEON_CAP1_TRIG_CNTL             0x09C0
1493 #define RADEON_CAP1_DEBUG                         0x09C4
1494 #define RADEON_CAP1_CONFIG                0x09C8
1495 #define RADEON_CAP1_ANC_ODD_OFFSET        0x09CC
1496 #define RADEON_CAP1_ANC_EVEN_OFFSET       0x09D0
1497 #define RADEON_CAP1_ANC_H_WINDOW                  0x09D4
1498 #define RADEON_CAP1_VIDEO_SYNC_TEST       0x09D8
1499 #define RADEON_CAP1_ONESHOT_BUF_OFFSET    0x09DC
1500 #define RADEON_CAP1_BUF_STATUS            0x09E0
1501 #define RADEON_CAP1_DWNSC_XRATIO                  0x09E8
1502 #define RADEON_CAP1_XSHARPNESS            0x09EC
1506 #define RADEON_IDCT_RUNS                  0x1F80
1507 #define RADEON_IDCT_LEVELS                0x1F84
1508 #define RADEON_IDCT_CONTROL               0x1FBC
1509 #define RADEON_IDCT_AUTH_CONTROL          0x1F88
1510 #define RADEON_IDCT_AUTH                  0x1F8C
1512 #define RADEON_P2PLL_CNTL                   0x002a /* P2PLL */
1513 #       define RADEON_P2PLL_RESET                (1 <<  0)
1520 #define RADEON_P2PLL_DIV_0                  0x002c
1521 #       define RADEON_P2PLL_FB0_DIV_MASK    0x07ff
1522 #       define RADEON_P2PLL_POST0_DIV_MASK  0x00070000
1523 #define RADEON_P2PLL_REF_DIV                0x002B /* PLL */
1524 #       define RADEON_P2PLL_REF_DIV_MASK    0x03ff
1527 #       define R300_PPLL_REF_DIV_ACC_MASK   (0x3ff << 18)
1529 #define RADEON_PALETTE_DATA                 0x00b4
1530 #define RADEON_PALETTE_30_DATA              0x00b8
1531 #define RADEON_PALETTE_INDEX                0x00b0
1532 #define RADEON_PCI_GART_PAGE                0x017c
1533 #define RADEON_PIXCLKS_CNTL                 0x002d
1534 #       define RADEON_PIX2CLK_SRC_SEL_MASK     0x03
1535 #       define RADEON_PIX2CLK_SRC_SEL_CPUCLK   0x00
1536 #       define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1537 #       define RADEON_PIX2CLK_SRC_SEL_BYTECLK  0x02
1538 #       define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1555 #define RADEON_PLANE_3D_MASK_C              0x1d44
1556 #define RADEON_PLL_TEST_CNTL                0x0013 /* PLL */
1558 #define RADEON_PMI_CAP_ID                   0x0f5c /* PCI */
1559 #define RADEON_PMI_DATA                     0x0f63 /* PCI */
1560 #define RADEON_PMI_NXT_CAP_PTR              0x0f5d /* PCI */
1561 #define RADEON_PMI_PMC_REG                  0x0f5e /* PCI */
1562 #define RADEON_PMI_PMCSR_REG                0x0f60 /* PCI */
1563 #define RADEON_PMI_REGISTER                 0x0f5c /* PCI */
1564 #define RADEON_PPLL_CNTL                    0x0002 /* PLL */
1565 #       define RADEON_PPLL_RESET                (1 <<  0)
1572 #define RADEON_PPLL_DIV_0                   0x0004 /* PLL */
1573 #define RADEON_PPLL_DIV_1                   0x0005 /* PLL */
1574 #define RADEON_PPLL_DIV_2                   0x0006 /* PLL */
1575 #define RADEON_PPLL_DIV_3                   0x0007 /* PLL */
1576 #       define RADEON_PPLL_FB3_DIV_MASK     0x07ff
1577 #       define RADEON_PPLL_POST3_DIV_MASK   0x00070000
1578 #define RADEON_PPLL_REF_DIV                 0x0003 /* PLL */
1579 #       define RADEON_PPLL_REF_DIV_MASK     0x03ff
1582 #define RADEON_PWR_MNGMT_CNTL_STATUS        0x0f60 /* PCI */
1584 #define RADEON_RBBM_GUICNTL                 0x172c
1585 #       define RADEON_HOST_DATA_SWAP_NONE   (0 << 0)
1586 #       define RADEON_HOST_DATA_SWAP_16BIT  (1 << 0)
1587 #       define RADEON_HOST_DATA_SWAP_32BIT  (2 << 0)
1588 #       define RADEON_HOST_DATA_SWAP_HDW    (3 << 0)
1589 #define RADEON_RBBM_SOFT_RESET              0x00f0
1590 #       define RADEON_SOFT_RESET_CP         (1 <<  0)
1598 #define RADEON_RBBM_STATUS                  0x0e40
1599 #       define RADEON_RBBM_FIFOCNT_MASK     0x007f
1601 #define RADEON_RB2D_DSTCACHE_CTLSTAT        0x342c
1602 #       define RADEON_RB2D_DC_FLUSH         (3 << 0)
1604 #       define RADEON_RB2D_DC_FLUSH_ALL     0xf
1606 #define RADEON_RB2D_DSTCACHE_MODE           0x3428
1607 #define RADEON_DSTCACHE_CTLSTAT             0x1714
1609 #define RADEON_RB3D_ZCACHE_MODE             0x3250
1610 #define RADEON_RB3D_ZCACHE_CTLSTAT          0x3254
1611 #       define RADEON_RB3D_ZC_FLUSH_ALL     0x5
1612 #define RADEON_RB3D_DSTCACHE_MODE           0x3258
1613 # define RADEON_RB3D_DC_CACHE_ENABLE            (0)
1627 #define RADEON_RB3D_DSTCACHE_CTLSTAT            0x325C
1628 # define RADEON_RB3D_DC_FLUSH                   (3 << 0)
1630 # define RADEON_RB3D_DC_FLUSH_ALL               0xf
1633 #define RADEON_REG_BASE                     0x0f18 /* PCI */
1634 #define RADEON_REGPROG_INF                  0x0f09 /* PCI */
1635 #define RADEON_REVISION_ID                  0x0f08 /* PCI */
1637 #define RADEON_SC_BOTTOM                    0x164c
1638 #define RADEON_SC_BOTTOM_RIGHT              0x16f0
1639 #define RADEON_SC_BOTTOM_RIGHT_C            0x1c8c
1640 #define RADEON_SC_LEFT                      0x1640
1641 #define RADEON_SC_RIGHT                     0x1644
1642 #define RADEON_SC_TOP                       0x1648
1643 #define RADEON_SC_TOP_LEFT                  0x16ec
1644 #define RADEON_SC_TOP_LEFT_C                0x1c88
1645 #       define RADEON_SC_SIGN_MASK_LO       0x8000
1646 #       define RADEON_SC_SIGN_MASK_HI       0x80000000
1647 #define RADEON_M_SPLL_REF_FB_DIV            0x000a /* PLL */
1648 #	define RADEON_M_SPLL_REF_DIV_SHIFT  0
1649 #	define RADEON_M_SPLL_REF_DIV_MASK   0xff
1651 #	define RADEON_MPLL_FB_DIV_MASK      0xff
1653 #	define RADEON_SPLL_FB_DIV_MASK      0xff
1654 #define RADEON_SPLL_CNTL                    0x000c /* PLL */
1655 #       define RADEON_SPLL_SLEEP            (1 << 0)
1657 #       define RADEON_SPLL_PCP_MASK         0x7
1659 #       define RADEON_SPLL_PVG_MASK         0x7
1661 #       define RADEON_SPLL_PDC_MASK         0x3
1663 #define RADEON_SCLK_CNTL                    0x000d /* PLL */
1664 #       define RADEON_SCLK_SRC_SEL_MASK     0x0007
1665 #       define RADEON_DYN_STOP_LAT_MASK     0x00007ff8
1666 #       define RADEON_CP_MAX_DYN_STOP_LAT   0x0008
1667 #       define RADEON_SCLK_FORCEON_MASK     0xffff8000
1691 #define R300_SCLK_CNTL2                     0x1e   /* PLL */
1698 #define RADEON_SCLK_MORE_CNTL               0x0035 /* PLL */
1699 #       define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1700 #       define RADEON_SCLK_MORE_FORCEON     0x0700
1701 #define RADEON_SDRAM_MODE_REG               0x0158
1702 #define RADEON_SEQ8_DATA                    0x03c5 /* VGA */
1703 #define RADEON_SEQ8_IDX                     0x03c4 /* VGA */
1704 #define RADEON_SNAPSHOT_F_COUNT             0x0244
1705 #define RADEON_SNAPSHOT_VH_COUNTS           0x0240
1706 #define RADEON_SNAPSHOT_VIF_COUNT           0x024c
1707 #define RADEON_SRC_OFFSET                   0x15ac
1708 #define RADEON_SRC_PITCH                    0x15b0
1709 #define RADEON_SRC_PITCH_OFFSET             0x1428
1710 #define RADEON_SRC_SC_BOTTOM                0x165c
1711 #define RADEON_SRC_SC_BOTTOM_RIGHT          0x16f4
1712 #define RADEON_SRC_SC_RIGHT                 0x1654
1713 #define RADEON_SRC_X                        0x1414
1714 #define RADEON_SRC_X_Y                      0x1590
1715 #define RADEON_SRC_Y                        0x1418
1716 #define RADEON_SRC_Y_X                      0x1434
1717 #define RADEON_STATUS                       0x0f06 /* PCI */
1718 #define RADEON_SUBPIC_CNTL                  0x0540 /* ? */
1719 #define RADEON_SUB_CLASS                    0x0f0a /* PCI */
1720 #define RADEON_SURFACE_CNTL                 0x0b00
1726 #define RADEON_SURFACE0_INFO                0x0b0c
1727 #       define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1731 #       define R200_SURF_TILE_NONE          (0 << 16)
1737 #       define R300_SURF_TILE_NONE          (0 << 16)
1744 #define RADEON_SURFACE0_LOWER_BOUND         0x0b04
1745 #define RADEON_SURFACE0_UPPER_BOUND         0x0b08
1746 #define RADEON_SURFACE1_INFO                0x0b1c
1747 #define RADEON_SURFACE1_LOWER_BOUND         0x0b14
1748 #define RADEON_SURFACE1_UPPER_BOUND         0x0b18
1749 #define RADEON_SURFACE2_INFO                0x0b2c
1750 #define RADEON_SURFACE2_LOWER_BOUND         0x0b24
1751 #define RADEON_SURFACE2_UPPER_BOUND         0x0b28
1752 #define RADEON_SURFACE3_INFO                0x0b3c
1753 #define RADEON_SURFACE3_LOWER_BOUND         0x0b34
1754 #define RADEON_SURFACE3_UPPER_BOUND         0x0b38
1755 #define RADEON_SURFACE4_INFO                0x0b4c
1756 #define RADEON_SURFACE4_LOWER_BOUND         0x0b44
1757 #define RADEON_SURFACE4_UPPER_BOUND         0x0b48
1758 #define RADEON_SURFACE5_INFO                0x0b5c
1759 #define RADEON_SURFACE5_LOWER_BOUND         0x0b54
1760 #define RADEON_SURFACE5_UPPER_BOUND         0x0b58
1761 #define RADEON_SURFACE6_INFO                0x0b6c
1762 #define RADEON_SURFACE6_LOWER_BOUND         0x0b64
1763 #define RADEON_SURFACE6_UPPER_BOUND         0x0b68
1764 #define RADEON_SURFACE7_INFO                0x0b7c
1765 #define RADEON_SURFACE7_LOWER_BOUND         0x0b74
1766 #define RADEON_SURFACE7_UPPER_BOUND         0x0b78
1767 #define RADEON_SW_SEMAPHORE                 0x013c
1769 #define RADEON_TEST_DEBUG_CNTL              0x0120
1770 #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
1772 #define RADEON_TEST_DEBUG_MUX               0x0124
1773 #define RADEON_TEST_DEBUG_OUT               0x012c
1774 #define RADEON_TMDS_PLL_CNTL                0x02a8
1775 #define RADEON_TMDS_TRANSMITTER_CNTL        0x02a4
1778 #define RADEON_TRAIL_BRES_DEC               0x1614
1779 #define RADEON_TRAIL_BRES_ERR               0x160c
1780 #define RADEON_TRAIL_BRES_INC               0x1610
1781 #define RADEON_TRAIL_X                      0x1618
1782 #define RADEON_TRAIL_X_SUB                  0x1620
1784 #define RADEON_VCLK_ECP_CNTL                0x0008 /* PLL */
1785 #       define RADEON_VCLK_SRC_SEL_MASK     0x03
1786 #       define RADEON_VCLK_SRC_SEL_CPUCLK   0x00
1787 #       define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1788 #       define RADEON_VCLK_SRC_SEL_BYTECLK  0x02
1789 #       define RADEON_VCLK_SRC_SEL_PPLLCLK  0x03
1794 #define RADEON_VENDOR_ID                    0x0f00 /* PCI */
1795 #define RADEON_VGA_DDA_CONFIG               0x02e8
1796 #define RADEON_VGA_DDA_ON_OFF               0x02ec
1797 #define RADEON_VID_BUFFER_CONTROL           0x0900
1798 #define RADEON_VIDEOMUX_CNTL                0x0190
1801 #define RADEON_VIPH_CH0_DATA                0x0c00
1802 #define RADEON_VIPH_CH1_DATA                0x0c04
1803 #define RADEON_VIPH_CH2_DATA                0x0c08
1804 #define RADEON_VIPH_CH3_DATA                0x0c0c
1805 #define RADEON_VIPH_CH0_ADDR                0x0c10
1806 #define RADEON_VIPH_CH1_ADDR                0x0c14
1807 #define RADEON_VIPH_CH2_ADDR                0x0c18
1808 #define RADEON_VIPH_CH3_ADDR                0x0c1c
1809 #define RADEON_VIPH_CH0_SBCNT               0x0c20
1810 #define RADEON_VIPH_CH1_SBCNT               0x0c24
1811 #define RADEON_VIPH_CH2_SBCNT               0x0c28
1812 #define RADEON_VIPH_CH3_SBCNT               0x0c2c
1813 #define RADEON_VIPH_CH0_ABCNT               0x0c30
1814 #define RADEON_VIPH_CH1_ABCNT               0x0c34
1815 #define RADEON_VIPH_CH2_ABCNT               0x0c38
1816 #define RADEON_VIPH_CH3_ABCNT               0x0c3c
1817 #define RADEON_VIPH_CONTROL                 0x0c40
1818 #       define RADEON_VIP_BUSY 0
1822 #define RADEON_VIPH_DV_LAT                  0x0c44
1823 #define RADEON_VIPH_BM_CHUNK                0x0c48
1824 #define RADEON_VIPH_DV_INT                  0x0c4c
1825 #define RADEON_VIPH_TIMEOUT_STAT            0x0c50
1826 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1827 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK   0x00000010
1828 #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1830 #define RADEON_VIPH_REG_DATA                0x0084
1831 #define RADEON_VIPH_REG_ADDR                0x0080
1834 #define RADEON_WAIT_UNTIL                   0x1720
1835 #       define RADEON_WAIT_CRTC_PFLIP       (1 << 0)
1850 #       define RADEON_CMDFIFO_ENTRIES_MASK  0x7f
1853 #       define RADEON_ENG_DISPLAY_SELECT_CRTC0    (0 << 31)
1856 #define RADEON_X_MPLL_REF_FB_DIV            0x000a /* PLL */
1857 #define RADEON_XCLK_CNTL                    0x000d /* PLL */
1858 #define RADEON_XDLL_CNTL                    0x000c /* PLL */
1859 #define RADEON_XPLL_CNTL                    0x000b /* PLL */
1864 #define RADEON_PP_BORDER_COLOR_0            0x1d40
1865 #define RADEON_PP_BORDER_COLOR_1            0x1d44
1866 #define RADEON_PP_BORDER_COLOR_2            0x1d48
1867 #define RADEON_PP_CNTL                      0x1c38
1868 #       define RADEON_STIPPLE_ENABLE        (1 <<  0)
1872 #       define RADEON_TEX_ENABLE_MASK       (0xf << 4)
1877 #       define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1886 #       define RADEON_ANTI_ALIAS_NONE       (0 << 24)
1891 #       define RADEON_BUMPED_MAP_T0         (0 << 27)
1897 #define RADEON_PP_FOG_COLOR                 0x1c18
1898 #       define RADEON_FOG_COLOR_MASK        0x00ffffff
1899 #       define RADEON_FOG_VERTEX            (0 << 24)
1901 #       define RADEON_FOG_USE_DEPTH         (0 << 25)
1904 #define RADEON_PP_LUM_MATRIX                0x1d00
1905 #define RADEON_PP_MISC                      0x1c14
1906 #       define RADEON_REF_ALPHA_MASK        0x000000ff
1907 #       define RADEON_ALPHA_TEST_FAIL       (0 << 8)
1916 #       define RADEON_CHROMA_FUNC_FAIL      (0 << 16)
1920 #       define RADEON_CHROMA_KEY_NEAREST    (0 << 18)
1923 #       define RADEON_SHADOW_FUNC_EQUAL     (0 << 21)
1925 #       define RADEON_SHADOW_PASS_1         (0 << 22)
1927 #       define RADEON_RIGHT_HAND_CUBE_D3D   (0 << 24)
1929 #define RADEON_PP_ROT_MATRIX_0              0x1d58
1930 #define RADEON_PP_ROT_MATRIX_1              0x1d5c
1931 #define RADEON_PP_TXFILTER_0                0x1c54
1932 #define RADEON_PP_TXFILTER_1                0x1c6c
1933 #define RADEON_PP_TXFILTER_2                0x1c84
1934 #       define RADEON_MAG_FILTER_NEAREST                   (0  <<  0)
1935 #       define RADEON_MAG_FILTER_LINEAR                    (1  <<  0)
1936 #       define RADEON_MAG_FILTER_MASK                      (1  <<  0)
1937 #       define RADEON_MIN_FILTER_NEAREST                   (0  <<  1)
1948 #       define RADEON_MAX_ANISO_1_TO_1                     (0  <<  5)
1954 #       define RADEON_LOD_BIAS_MASK                        (0xff <<  8)
1956 #       define RADEON_MAX_MIP_LEVEL_MASK                   (0x0f << 16)
1959 #       define RADEON_YUV_TEMPERATURE_COOL                 (0  << 21)
1963 #       define RADEON_CLAMP_S_WRAP                         (0  << 23)
1973 #       define RADEON_CLAMP_T_WRAP                         (0  << 27)
1982 #       define RADEON_BORDER_MODE_OGL                      (0  << 31)
1984 #define RADEON_PP_TXFORMAT_0                0x1c58
1985 #define RADEON_PP_TXFORMAT_1                0x1c70
1986 #define RADEON_PP_TXFORMAT_2                0x1c88
1987 #       define RADEON_TXFORMAT_I8                 (0  <<  0)
1988 #       define RADEON_TXFORMAT_AI88               (1  <<  0)
1989 #       define RADEON_TXFORMAT_RGB332             (2  <<  0)
1990 #       define RADEON_TXFORMAT_ARGB1555           (3  <<  0)
1991 #       define RADEON_TXFORMAT_RGB565             (4  <<  0)
1992 #       define RADEON_TXFORMAT_ARGB4444           (5  <<  0)
1993 #       define RADEON_TXFORMAT_ARGB8888           (6  <<  0)
1994 #       define RADEON_TXFORMAT_RGBA8888           (7  <<  0)
1995 #       define RADEON_TXFORMAT_Y8                 (8  <<  0)
1996 #       define RADEON_TXFORMAT_VYUY422            (10 <<  0)
1997 #       define RADEON_TXFORMAT_YVYU422            (11 <<  0)
1998 #       define RADEON_TXFORMAT_DXT1               (12 <<  0)
1999 #       define RADEON_TXFORMAT_DXT23              (14 <<  0)
2000 #       define RADEON_TXFORMAT_DXT45              (15 <<  0)
2001 #	define RADEON_TXFORMAT_SHADOW16           (16 <<  0)
2002 #	define RADEON_TXFORMAT_SHADOW32           (17 <<  0)
2003 #       define RADEON_TXFORMAT_DUDV88             (18 <<  0)
2004 #       define RADEON_TXFORMAT_LDUDV655           (19 <<  0)
2005 #       define RADEON_TXFORMAT_LDUDUV8888         (20 <<  0)
2006 #       define RADEON_TXFORMAT_FORMAT_MASK        (31 <<  0)
2007 #       define RADEON_TXFORMAT_FORMAT_SHIFT       0
2019 #       define RADEON_TXFORMAT_ST_ROUTE_STQ0      (0  << 24)
2023 #       define RADEON_TXFORMAT_ENDIAN_NO_SWAP     (0  << 26)
2031 #define RADEON_PP_CUBIC_FACES_0             0x1d24
2032 #define RADEON_PP_CUBIC_FACES_1             0x1d28
2033 #define RADEON_PP_CUBIC_FACES_2             0x1d2c
2034 #       define RADEON_FACE_WIDTH_1_SHIFT          0
2036 #       define RADEON_FACE_WIDTH_1_MASK           (0xf << 0)
2037 #       define RADEON_FACE_HEIGHT_1_MASK          (0xf << 4)
2040 #       define RADEON_FACE_WIDTH_2_MASK           (0xf << 8)
2041 #       define RADEON_FACE_HEIGHT_2_MASK          (0xf << 12)
2044 #       define RADEON_FACE_WIDTH_3_MASK           (0xf << 16)
2045 #       define RADEON_FACE_HEIGHT_3_MASK          (0xf << 20)
2048 #       define RADEON_FACE_WIDTH_4_MASK           (0xf << 24)
2049 #       define RADEON_FACE_HEIGHT_4_MASK          (0xf << 28)
2051 #define RADEON_PP_TXOFFSET_0                0x1c5c
2052 #define RADEON_PP_TXOFFSET_1                0x1c74
2053 #define RADEON_PP_TXOFFSET_2                0x1c8c
2054 #       define RADEON_TXO_ENDIAN_NO_SWAP     (0 << 0)
2055 #       define RADEON_TXO_ENDIAN_BYTE_SWAP   (1 << 0)
2056 #       define RADEON_TXO_ENDIAN_WORD_SWAP   (2 << 0)
2057 #       define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
2058 #       define RADEON_TXO_MACRO_LINEAR       (0 << 2)
2060 #       define RADEON_TXO_MICRO_LINEAR       (0 << 3)
2063 #       define RADEON_TXO_OFFSET_MASK        0xffffffe0
2066 #define RADEON_PP_CUBIC_OFFSET_T0_0         0x1dd0  /* bits [31:5] */
2067 #define RADEON_PP_CUBIC_OFFSET_T0_1         0x1dd4
2068 #define RADEON_PP_CUBIC_OFFSET_T0_2         0x1dd8
2069 #define RADEON_PP_CUBIC_OFFSET_T0_3         0x1ddc
2070 #define RADEON_PP_CUBIC_OFFSET_T0_4         0x1de0
2071 #define RADEON_PP_CUBIC_OFFSET_T1_0         0x1e00
2072 #define RADEON_PP_CUBIC_OFFSET_T1_1         0x1e04
2073 #define RADEON_PP_CUBIC_OFFSET_T1_2         0x1e08
2074 #define RADEON_PP_CUBIC_OFFSET_T1_3         0x1e0c
2075 #define RADEON_PP_CUBIC_OFFSET_T1_4         0x1e10
2076 #define RADEON_PP_CUBIC_OFFSET_T2_0         0x1e14
2077 #define RADEON_PP_CUBIC_OFFSET_T2_1         0x1e18
2078 #define RADEON_PP_CUBIC_OFFSET_T2_2         0x1e1c
2079 #define RADEON_PP_CUBIC_OFFSET_T2_3         0x1e20
2080 #define RADEON_PP_CUBIC_OFFSET_T2_4         0x1e24
2082 #define RADEON_PP_TEX_SIZE_0                0x1d04  /* NPOT */
2083 #define RADEON_PP_TEX_SIZE_1                0x1d0c
2084 #define RADEON_PP_TEX_SIZE_2                0x1d14
2085 #       define RADEON_TEX_USIZE_MASK        (0x7ff << 0)
2086 #       define RADEON_TEX_USIZE_SHIFT       0
2087 #       define RADEON_TEX_VSIZE_MASK        (0x7ff << 16)
2093 #define RADEON_PP_TEX_PITCH_0               0x1d08  /* NPOT */
2094 #define RADEON_PP_TEX_PITCH_1               0x1d10  /* NPOT */
2095 #define RADEON_PP_TEX_PITCH_2               0x1d18  /* NPOT */
2098 #define RADEON_PP_TXCBLEND_0                0x1c60
2099 #define RADEON_PP_TXCBLEND_1                0x1c78
2100 #define RADEON_PP_TXCBLEND_2                0x1c90
2101 #       define RADEON_COLOR_ARG_A_SHIFT          0
2102 #       define RADEON_COLOR_ARG_A_MASK           (0x1f << 0)
2103 #       define RADEON_COLOR_ARG_A_ZERO           (0    << 0)
2104 #       define RADEON_COLOR_ARG_A_CURRENT_COLOR  (2    << 0)
2105 #       define RADEON_COLOR_ARG_A_CURRENT_ALPHA  (3    << 0)
2106 #       define RADEON_COLOR_ARG_A_DIFFUSE_COLOR  (4    << 0)
2107 #       define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA  (5    << 0)
2108 #       define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6    << 0)
2109 #       define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7    << 0)
2110 #       define RADEON_COLOR_ARG_A_TFACTOR_COLOR  (8    << 0)
2111 #       define RADEON_COLOR_ARG_A_TFACTOR_ALPHA  (9    << 0)
2112 #       define RADEON_COLOR_ARG_A_T0_COLOR       (10   << 0)
2113 #       define RADEON_COLOR_ARG_A_T0_ALPHA       (11   << 0)
2114 #       define RADEON_COLOR_ARG_A_T1_COLOR       (12   << 0)
2115 #       define RADEON_COLOR_ARG_A_T1_ALPHA       (13   << 0)
2116 #       define RADEON_COLOR_ARG_A_T2_COLOR       (14   << 0)
2117 #       define RADEON_COLOR_ARG_A_T2_ALPHA       (15   << 0)
2118 #       define RADEON_COLOR_ARG_A_T3_COLOR       (16   << 0)
2119 #       define RADEON_COLOR_ARG_A_T3_ALPHA       (17   << 0)
2121 #       define RADEON_COLOR_ARG_B_MASK           (0x1f << 5)
2122 #       define RADEON_COLOR_ARG_B_ZERO           (0    << 5)
2140 #       define RADEON_COLOR_ARG_C_MASK           (0x1f << 10)
2141 #       define RADEON_COLOR_ARG_C_ZERO           (0    << 10)
2165 #       define RADEON_BLEND_CTL_ADD              (0 << 18)
2172 #       define RADEON_SCALE_1X                   (0 << 21)
2180 #       define RADEON_COLOR_ARG_MASK             0x1f
2182 #define RADEON_PP_TXABLEND_0                0x1c64
2183 #define RADEON_PP_TXABLEND_1                0x1c7c
2184 #define RADEON_PP_TXABLEND_2                0x1c94
2185 #       define RADEON_ALPHA_ARG_A_SHIFT          0
2186 #       define RADEON_ALPHA_ARG_A_MASK           (0xf << 0)
2187 #       define RADEON_ALPHA_ARG_A_ZERO           (0   << 0)
2188 #       define RADEON_ALPHA_ARG_A_CURRENT_ALPHA  (1   << 0)
2189 #       define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA  (2   << 0)
2190 #       define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3   << 0)
2191 #       define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA  (4   << 0)
2192 #       define RADEON_ALPHA_ARG_A_T0_ALPHA       (5   << 0)
2193 #       define RADEON_ALPHA_ARG_A_T1_ALPHA       (6   << 0)
2194 #       define RADEON_ALPHA_ARG_A_T2_ALPHA       (7   << 0)
2195 #       define RADEON_ALPHA_ARG_A_T3_ALPHA       (8   << 0)
2197 #       define RADEON_ALPHA_ARG_B_MASK           (0xf << 4)
2198 #       define RADEON_ALPHA_ARG_B_ZERO           (0   << 4)
2208 #       define RADEON_ALPHA_ARG_C_MASK           (0xf << 8)
2209 #       define RADEON_ALPHA_ARG_C_ZERO           (0   << 8)
2219 #       define RADEON_ALPHA_ARG_MASK             0xf
2221 #define RADEON_PP_TFACTOR_0                 0x1c68
2222 #define RADEON_PP_TFACTOR_1                 0x1c80
2223 #define RADEON_PP_TFACTOR_2                 0x1c98
2225 #define RADEON_RB3D_BLENDCNTL               0x1c20
2227 #       define RADEON_COMB_FCN_ADD_CLAMP               (0  << 12)
2254 #define RADEON_RB3D_CNTL                    0x1c3c
2255 #       define RADEON_ALPHA_BLEND_ENABLE       (1  <<  0)
2279 #define RADEON_RB3D_COLOROFFSET             0x1c40
2280 #       define RADEON_COLOROFFSET_MASK      0xfffffff0
2281 #define RADEON_RB3D_COLORPITCH              0x1c48
2282 #       define RADEON_COLORPITCH_MASK         0x000001ff8
2285 #       define RADEON_COLOR_ENDIAN_NO_SWAP    (0 << 18)
2288 #define RADEON_RB3D_DEPTHOFFSET             0x1c24
2289 #define RADEON_RB3D_DEPTHPITCH              0x1c28
2290 #       define RADEON_DEPTHPITCH_MASK         0x00001ff8
2291 #       define RADEON_DEPTH_ENDIAN_NO_SWAP    (0 << 18)
2294 #define RADEON_RB3D_PLANEMASK               0x1d84
2295 #define RADEON_RB3D_ROPCNTL                 0x1d80
2297 #       define RADEON_ROP_CLEAR             (0  << 8)
2313 #define RADEON_RB3D_STENCILREFMASK          0x1d7c
2314 #       define RADEON_STENCIL_REF_SHIFT       0
2315 #       define RADEON_STENCIL_REF_MASK        (0xff << 0)
2317 #       define RADEON_STENCIL_VALUE_MASK      (0xff << 16)
2319 #       define RADEON_STENCIL_WRITE_MASK      (0xff << 24)
2320 #define RADEON_RB3D_ZSTENCILCNTL            0x1c2c
2321 #       define RADEON_DEPTH_FORMAT_MASK          (0xf << 0)
2322 #       define RADEON_DEPTH_FORMAT_16BIT_INT_Z   (0  <<  0)
2323 #       define RADEON_DEPTH_FORMAT_24BIT_INT_Z   (2  <<  0)
2324 #       define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3  <<  0)
2325 #       define RADEON_DEPTH_FORMAT_32BIT_INT_Z   (4  <<  0)
2326 #       define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5  <<  0)
2327 #       define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7  <<  0)
2328 #       define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9  <<  0)
2329 #       define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 <<  0)
2330 #       define RADEON_Z_TEST_NEVER               (0  <<  4)
2339 #       define RADEON_STENCIL_TEST_NEVER         (0  << 12)
2347 #       define RADEON_STENCIL_TEST_MASK          (0x7 << 12)
2348 #       define RADEON_STENCIL_FAIL_KEEP          (0  << 16)
2354 #       define RADEON_STENCIL_FAIL_MASK          (0x7 << 16)
2355 #       define RADEON_STENCIL_ZPASS_KEEP         (0  << 20)
2361 #       define RADEON_STENCIL_ZPASS_MASK         (0x7 << 20)
2362 #       define RADEON_STENCIL_ZFAIL_KEEP         (0  << 24)
2368 #       define RADEON_STENCIL_ZFAIL_MASK         (0x7 << 24)
2372 #define RADEON_RE_LINE_PATTERN              0x1cd0
2373 #       define RADEON_LINE_PATTERN_MASK             0x0000ffff
2376 #       define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
2379 #define RADEON_RE_LINE_STATE                0x1cd4
2380 #       define RADEON_LINE_CURRENT_PTR_SHIFT   0
2382 #define RADEON_RE_MISC                      0x26c4
2383 #       define RADEON_STIPPLE_COORD_MASK       0x1f
2384 #       define RADEON_STIPPLE_X_OFFSET_SHIFT   0
2385 #       define RADEON_STIPPLE_X_OFFSET_MASK    (0x1f << 0)
2387 #       define RADEON_STIPPLE_Y_OFFSET_MASK    (0x1f << 8)
2388 #       define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
2390 #define RADEON_RE_SOLID_COLOR               0x1c1c
2391 #define RADEON_RE_TOP_LEFT                  0x26c0
2392 #       define RADEON_RE_LEFT_SHIFT         0
2394 #define RADEON_RE_WIDTH_HEIGHT              0x1c44
2395 #       define RADEON_RE_WIDTH_SHIFT        0
2398 #define RADEON_RB3D_ZPASS_DATA 0x3290
2399 #define RADEON_RB3D_ZPASS_ADDR 0x3294
2401 #define RADEON_SE_CNTL                      0x1c4c
2402 #       define RADEON_FFACE_CULL_CW          (0 <<  0)
2403 #       define RADEON_FFACE_CULL_CCW         (1 <<  0)
2404 #       define RADEON_FFACE_CULL_DIR_MASK    (1 <<  0)
2405 #       define RADEON_BFACE_CULL             (0 <<  1)
2407 #       define RADEON_FFACE_CULL             (0 <<  3)
2411 #       define RADEON_FLAT_SHADE_VTX_0       (0 <<  6)
2415 #       define RADEON_DIFFUSE_SHADE_SOLID    (0 <<  8)
2419 #       define RADEON_ALPHA_SHADE_SOLID      (0 << 10)
2423 #       define RADEON_SPECULAR_SHADE_SOLID   (0 << 12)
2427 #       define RADEON_FOG_SHADE_SOLID        (0 << 14)
2437 #       define RADEON_VTX_PIX_CENTER_D3D     (0 << 27)
2439 #       define RADEON_ROUND_MODE_TRUNC       (0 << 28)
2443 #       define RADEON_ROUND_PREC_16TH_PIX    (0 << 30)
2447 #define R200_RE_CNTL				0x1c50
2448 #       define R200_STIPPLE_ENABLE		0x1
2449 #       define R200_SCISSOR_ENABLE		0x2
2450 #       define R200_PATTERN_ENABLE		0x4
2451 #       define R200_PERSPECTIVE_ENABLE		0x8
2452 #       define R200_POINT_SMOOTH		0x20
2453 #       define R200_VTX_STQ0_D3D		0x00010000
2454 #       define R200_VTX_STQ1_D3D		0x00040000
2455 #       define R200_VTX_STQ2_D3D		0x00100000
2456 #       define R200_VTX_STQ3_D3D		0x00400000
2457 #       define R200_VTX_STQ4_D3D		0x01000000
2458 #       define R200_VTX_STQ5_D3D		0x04000000
2459 #define RADEON_SE_CNTL_STATUS               0x2140
2460 #       define RADEON_VC_NO_SWAP            (0 << 0)
2461 #       define RADEON_VC_16BIT_SWAP         (1 << 0)
2462 #       define RADEON_VC_32BIT_SWAP         (2 << 0)
2463 #       define RADEON_VC_HALF_DWORD_SWAP    (3 << 0)
2465 #define RADEON_SE_COORD_FMT                 0x1c50
2466 #       define RADEON_VTX_XY_PRE_MULT_1_OVER_W0  (1 <<  0)
2478 #       define RADEON_TEX1_W_ROUTING_USE_W0      (0 << 26)
2480 #define RADEON_SE_LINE_WIDTH                0x1db8
2481 #define RADEON_SE_TCL_LIGHT_MODEL_CTL       0x226c
2482 #       define RADEON_LIGHTING_ENABLE              (1 << 0)
2492 #       define RADEON_LM_SOURCE_STATE_PREMULT      0
2500 #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED     0x2220
2501 #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN   0x2224
2502 #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE    0x2228
2503 #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA   0x222c
2504 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED     0x2230
2505 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN   0x2234
2506 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE    0x2238
2507 #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA   0x223c
2508 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED   0x2210
2509 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
2510 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE  0x2218
2511 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
2512 #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED    0x2240
2513 #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN  0x2244
2514 #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE   0x2248
2515 #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA  0x224c
2516 #define RADEON_SE_TCL_MATRIX_SELECT_0       0x225c
2517 #       define RADEON_MODELVIEW_0_SHIFT        0
2525 #define RADEON_SE_TCL_MATRIX_SELECT_1       0x2260
2526 #       define RADEON_MODELPROJECT_0_SHIFT     0
2536 #define RADEON_SE_TCL_OUTPUT_VTX_FMT        0x2254
2537 #       define RADEON_TCL_VTX_W0                 (1 <<  0)
2560 #define RADEON_SE_TCL_OUTPUT_VTX_SEL        0x2258
2561 #       define RADEON_TCL_COMPUTE_XYZW           (1 << 0)
2566 #       define RADEON_TCL_TEX_INPUT_TEX_0        0
2579 #define RADEON_SE_TCL_PER_LIGHT_CTL_0       0x2270
2580 #       define RADEON_LIGHT_0_ENABLE               (1 <<  0)
2588 #       define RADEON_LIGHT_0_SHIFT                0
2598 #define RADEON_SE_TCL_PER_LIGHT_CTL_1       0x2274
2599 #       define RADEON_LIGHT_2_SHIFT            0
2601 #define RADEON_SE_TCL_PER_LIGHT_CTL_2       0x2278
2602 #       define RADEON_LIGHT_4_SHIFT            0
2604 #define RADEON_SE_TCL_PER_LIGHT_CTL_3       0x227c
2605 #       define RADEON_LIGHT_6_SHIFT            0
2608 #define RADEON_SE_TCL_SHININESS             0x2250
2610 #define RADEON_SE_TCL_TEXTURE_PROC_CTL      0x2268
2611 #       define RADEON_TEXGEN_TEXMAT_0_ENABLE      (1 << 0)
2619 #       define RADEON_TEXGEN_INPUT_MASK           0xf
2620 #       define RADEON_TEXGEN_INPUT_TEXCOORD_0     0
2634 #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL    0x2264
2635 #       define RADEON_UCP_IN_CLIP_SPACE            (1 <<  0)
2644 #       define RADEON_TCL_FOG_DISABLE              (0 <<  8)
2663 #       define RADEON_CULL_FRONT_IS_CW             (0 << 28)
2669 #define RADEON_SE_VPORT_XSCALE              0x1d98
2670 #define RADEON_SE_VPORT_XOFFSET             0x1d9c
2671 #define RADEON_SE_VPORT_YSCALE              0x1da0
2672 #define RADEON_SE_VPORT_YOFFSET             0x1da4
2673 #define RADEON_SE_VPORT_ZSCALE              0x1da8
2674 #define RADEON_SE_VPORT_ZOFFSET             0x1dac
2675 #define RADEON_SE_ZBIAS_FACTOR              0x1db0
2676 #define RADEON_SE_ZBIAS_CONSTANT            0x1db4
2678 #define RADEON_SE_VTX_FMT                   0x2080
2679 #       define RADEON_SE_VTX_FMT_XY         0x00000000
2680 #       define RADEON_SE_VTX_FMT_W0         0x00000001
2681 #       define RADEON_SE_VTX_FMT_FPCOLOR    0x00000002
2682 #       define RADEON_SE_VTX_FMT_FPALPHA    0x00000004
2683 #       define RADEON_SE_VTX_FMT_PKCOLOR    0x00000008
2684 #       define RADEON_SE_VTX_FMT_FPSPEC     0x00000010
2685 #       define RADEON_SE_VTX_FMT_FPFOG      0x00000020
2686 #       define RADEON_SE_VTX_FMT_PKSPEC     0x00000040
2687 #       define RADEON_SE_VTX_FMT_ST0        0x00000080
2688 #       define RADEON_SE_VTX_FMT_ST1        0x00000100
2689 #       define RADEON_SE_VTX_FMT_Q1         0x00000200
2690 #       define RADEON_SE_VTX_FMT_ST2        0x00000400
2691 #       define RADEON_SE_VTX_FMT_Q2         0x00000800
2692 #       define RADEON_SE_VTX_FMT_ST3        0x00001000
2693 #       define RADEON_SE_VTX_FMT_Q3         0x00002000
2694 #       define RADEON_SE_VTX_FMT_Q0         0x00004000
2695 #       define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK  0x00038000
2696 #       define RADEON_SE_VTX_FMT_N0         0x00040000
2697 #       define RADEON_SE_VTX_FMT_XY1        0x08000000
2698 #       define RADEON_SE_VTX_FMT_Z1         0x10000000
2699 #       define RADEON_SE_VTX_FMT_W1         0x20000000
2700 #       define RADEON_SE_VTX_FMT_N1         0x40000000
2701 #       define RADEON_SE_VTX_FMT_Z          0x80000000
2703 #define RADEON_SE_VF_CNTL                             0x2084
2719 #       define RADEON_VF_PRIM_WALK_STATE              (0<<4)
2730 #define RADEON_SE_PORT_DATA0			0x2000
2732 #define R200_SE_VAP_CNTL			0x2080
2733 #       define R200_VAP_TCL_ENABLE		0x00000001
2734 #       define R200_VAP_SINGLE_BUF_STATE_ENABLE	0x00000010
2735 #       define R200_VAP_FORCE_W_TO_ONE		0x00010000
2736 #       define R200_VAP_D3D_TEX_DEFAULT		0x00020000
2739 #       define R200_VAP_DX_CLIP_SPACE_DEF	0x00400000
2740 #define R200_VF_MAX_VTX_INDX			0x210c
2741 #define R200_VF_MIN_VTX_INDX			0x2110
2742 #define R200_SE_VTE_CNTL			0x20b0
2743 #       define R200_VPORT_X_SCALE_ENA			0x00000001
2744 #       define R200_VPORT_X_OFFSET_ENA			0x00000002
2745 #       define R200_VPORT_Y_SCALE_ENA			0x00000004
2746 #       define R200_VPORT_Y_OFFSET_ENA			0x00000008
2747 #       define R200_VPORT_Z_SCALE_ENA			0x00000010
2748 #       define R200_VPORT_Z_OFFSET_ENA			0x00000020
2749 #       define R200_VTX_XY_FMT				0x00000100
2750 #       define R200_VTX_Z_FMT				0x00000200
2751 #       define R200_VTX_W0_FMT				0x00000400
2752 #       define R200_VTX_W0_NORMALIZE			0x00000800
2753 #       define R200_VTX_ST_DENORMALIZED		0x00001000
2754 #define R200_SE_VAP_CNTL_STATUS			0x2140
2755 #       define R200_VC_NO_SWAP			(0 << 0)
2756 #       define R200_VC_16BIT_SWAP		(1 << 0)
2757 #       define R200_VC_32BIT_SWAP		(2 << 0)
2758 #define R200_PP_TXFILTER_0			0x2c00
2759 #define R200_PP_TXFILTER_1			0x2c20
2760 #define R200_PP_TXFILTER_2			0x2c40
2761 #define R200_PP_TXFILTER_3			0x2c60
2762 #define R200_PP_TXFILTER_4			0x2c80
2763 #define R200_PP_TXFILTER_5			0x2ca0
2764 #       define R200_MAG_FILTER_NEAREST		(0  <<  0)
2765 #       define R200_MAG_FILTER_LINEAR		(1  <<  0)
2766 #       define R200_MAG_FILTER_MASK		(1  <<  0)
2767 #       define R200_MIN_FILTER_NEAREST		(0  <<  1)
2778 #       define R200_MAX_ANISO_1_TO_1		(0  <<  5)
2784 #       define R200_MAX_MIP_LEVEL_MASK		(0x0f << 16)
2787 #       define R200_YUV_TEMPERATURE_COOL	(0  << 21)
2791 #       define R200_CLAMP_S_WRAP		(0  << 23)
2801 #       define R200_CLAMP_T_WRAP		(0  << 27)
2811 #       define R200_BORDER_MODE_OGL		(0  << 31)
2813 #define R200_PP_TXFORMAT_0			0x2c04
2814 #define R200_PP_TXFORMAT_1			0x2c24
2815 #define R200_PP_TXFORMAT_2			0x2c44
2816 #define R200_PP_TXFORMAT_3			0x2c64
2817 #define R200_PP_TXFORMAT_4			0x2c84
2818 #define R200_PP_TXFORMAT_5			0x2ca4
2819 #       define R200_TXFORMAT_I8			(0 << 0)
2820 #       define R200_TXFORMAT_AI88		(1 << 0)
2821 #       define R200_TXFORMAT_RGB332		(2 << 0)
2822 #       define R200_TXFORMAT_ARGB1555		(3 << 0)
2823 #       define R200_TXFORMAT_RGB565		(4 << 0)
2824 #       define R200_TXFORMAT_ARGB4444		(5 << 0)
2825 #       define R200_TXFORMAT_ARGB8888		(6 << 0)
2826 #       define R200_TXFORMAT_RGBA8888		(7 << 0)
2827 #       define R200_TXFORMAT_Y8			(8 << 0)
2828 #       define R200_TXFORMAT_AVYU4444		(9 << 0)
2829 #       define R200_TXFORMAT_VYUY422		(10 << 0)
2830 #       define R200_TXFORMAT_YVYU422		(11 << 0)
2831 #       define R200_TXFORMAT_DXT1		(12 << 0)
2832 #       define R200_TXFORMAT_DXT23		(14 << 0)
2833 #       define R200_TXFORMAT_DXT45		(15 << 0)
2834 #       define R200_TXFORMAT_DVDU88		(18 << 0)
2835 #       define R200_TXFORMAT_LDVDU655		(19 << 0)
2836 #       define R200_TXFORMAT_LDVDU8888		(20 << 0)
2837 #       define R200_TXFORMAT_GR1616		(21 << 0)
2838 #       define R200_TXFORMAT_ABGR8888		(22 << 0)
2839 #       define R200_TXFORMAT_BGR111110		(23 << 0)
2840 #       define R200_TXFORMAT_FORMAT_MASK	(31 <<	0)
2841 #       define R200_TXFORMAT_FORMAT_SHIFT	0
2852 #       define R200_TXFORMAT_ST_ROUTE_STQ0	(0 << 24)
2864 #define R200_PP_TXFORMAT_X_0                    0x2c08
2865 #define R200_PP_TXFORMAT_X_1                    0x2c28
2866 #define R200_PP_TXFORMAT_X_2                    0x2c48
2867 #define R200_PP_TXFORMAT_X_3                    0x2c68
2868 #define R200_PP_TXFORMAT_X_4                    0x2c88
2869 #define R200_PP_TXFORMAT_X_5                    0x2ca8
2871 #define R200_PP_TXSIZE_0			0x2c0c /* NPOT only */
2872 #define R200_PP_TXSIZE_1			0x2c2c /* NPOT only */
2873 #define R200_PP_TXSIZE_2			0x2c4c /* NPOT only */
2874 #define R200_PP_TXSIZE_3			0x2c6c /* NPOT only */
2875 #define R200_PP_TXSIZE_4			0x2c8c /* NPOT only */
2876 #define R200_PP_TXSIZE_5			0x2cac /* NPOT only */
2878 #define R200_PP_TXPITCH_0                       0x2c10 /* NPOT only */
2879 #define R200_PP_TXPITCH_1			0x2c30 /* NPOT only */
2880 #define R200_PP_TXPITCH_2			0x2c50 /* NPOT only */
2881 #define R200_PP_TXPITCH_3			0x2c70 /* NPOT only */
2882 #define R200_PP_TXPITCH_4			0x2c90 /* NPOT only */
2883 #define R200_PP_TXPITCH_5			0x2cb0 /* NPOT only */
2885 #define R200_PP_CUBIC_FACES_0			0x2c18
2886 #define R200_PP_CUBIC_FACES_1			0x2c38
2887 #define R200_PP_CUBIC_FACES_2			0x2c58
2888 #define R200_PP_CUBIC_FACES_3			0x2c78
2889 #define R200_PP_CUBIC_FACES_4			0x2c98
2890 #define R200_PP_CUBIC_FACES_5			0x2cb8
2892 #define R200_PP_TXOFFSET_0			0x2d00
2893 #       define R200_TXO_ENDIAN_NO_SWAP		(0 << 0)
2894 #       define R200_TXO_ENDIAN_BYTE_SWAP	(1 << 0)
2895 #       define R200_TXO_ENDIAN_WORD_SWAP	(2 << 0)
2896 #       define R200_TXO_ENDIAN_HALFDW_SWAP	(3 << 0)
2897 #       define R200_TXO_MACRO_LINEAR		(0 << 2)
2899 #       define R200_TXO_MICRO_LINEAR		(0 << 3)
2901 #       define R200_TXO_OFFSET_MASK		0xffffffe0
2903 #define R200_PP_CUBIC_OFFSET_F1_0         0x2d04
2904 #define R200_PP_CUBIC_OFFSET_F2_0         0x2d08
2905 #define R200_PP_CUBIC_OFFSET_F3_0         0x2d0c
2906 #define R200_PP_CUBIC_OFFSET_F4_0         0x2d10
2907 #define R200_PP_CUBIC_OFFSET_F5_0         0x2d14
2909 #define R200_PP_TXOFFSET_1			0x2d18
2910 #define R200_PP_CUBIC_OFFSET_F1_1         0x2d1c
2911 #define R200_PP_CUBIC_OFFSET_F2_1         0x2d20
2912 #define R200_PP_CUBIC_OFFSET_F3_1         0x2d24
2913 #define R200_PP_CUBIC_OFFSET_F4_1         0x2d28
2914 #define R200_PP_CUBIC_OFFSET_F5_1         0x2d2c
2916 #define R200_PP_TXOFFSET_2			0x2d30
2917 #define R200_PP_CUBIC_OFFSET_F1_2         0x2d34
2918 #define R200_PP_CUBIC_OFFSET_F2_2         0x2d38
2919 #define R200_PP_CUBIC_OFFSET_F3_2         0x2d3c
2920 #define R200_PP_CUBIC_OFFSET_F4_2         0x2d40
2921 #define R200_PP_CUBIC_OFFSET_F5_2         0x2d44
2923 #define R200_PP_TXOFFSET_3			0x2d48
2924 #define R200_PP_CUBIC_OFFSET_F1_3         0x2d4c
2925 #define R200_PP_CUBIC_OFFSET_F2_3         0x2d50
2926 #define R200_PP_CUBIC_OFFSET_F3_3         0x2d54
2927 #define R200_PP_CUBIC_OFFSET_F4_3         0x2d58
2928 #define R200_PP_CUBIC_OFFSET_F5_3         0x2d5c
2929 #define R200_PP_TXOFFSET_4			0x2d60
2930 #define R200_PP_CUBIC_OFFSET_F1_4         0x2d64
2931 #define R200_PP_CUBIC_OFFSET_F2_4         0x2d68
2932 #define R200_PP_CUBIC_OFFSET_F3_4         0x2d6c
2933 #define R200_PP_CUBIC_OFFSET_F4_4         0x2d70
2934 #define R200_PP_CUBIC_OFFSET_F5_4         0x2d74
2935 #define R200_PP_TXOFFSET_5			0x2d78
2936 #define R200_PP_CUBIC_OFFSET_F1_5         0x2d7c
2937 #define R200_PP_CUBIC_OFFSET_F2_5         0x2d80
2938 #define R200_PP_CUBIC_OFFSET_F3_5         0x2d84
2939 #define R200_PP_CUBIC_OFFSET_F4_5         0x2d88
2940 #define R200_PP_CUBIC_OFFSET_F5_5         0x2d8c
2942 #define R200_PP_TFACTOR_0			0x2ee0
2943 #define R200_PP_TFACTOR_1			0x2ee4
2944 #define R200_PP_TFACTOR_2			0x2ee8
2945 #define R200_PP_TFACTOR_3			0x2eec
2946 #define R200_PP_TFACTOR_4			0x2ef0
2947 #define R200_PP_TFACTOR_5			0x2ef4
2949 #define R200_PP_TXCBLEND_0			0x2f00
2950 #       define R200_TXC_ARG_A_ZERO		(0)
2973 #       define R200_TXC_ARG_A_MASK		(31 << 0)
2974 #       define R200_TXC_ARG_A_SHIFT		0
2975 #       define R200_TXC_ARG_B_ZERO		(0 << 5)
3000 #       define R200_TXC_ARG_C_ZERO		(0 << 10)
3040 #       define R200_TXC_OP_MADD			(0 << 28)
3048 #define R200_PP_TXCBLEND2_0		0x2f04
3049 #       define R200_TXC_TFACTOR_SEL_SHIFT	0
3050 #       define R200_TXC_TFACTOR_SEL_MASK	0x7
3052 #       define R200_TXC_TFACTOR1_SEL_MASK	(0x7 << 4)
3055 #       define R200_TXC_SCALE_1X		(0 << 8)
3064 #       define R200_TXC_CLAMP_WRAP		(0 << 12)
3068 #       define R200_TXC_OUTPUT_REG_NONE		(0 << 16)
3076 #       define R200_TXC_OUTPUT_MASK_RGB		(0 << 20)
3084 #       define R200_TXC_REPL_NORMAL		0
3094 #define R200_PP_TXABLEND_0			0x2f08
3095 #       define R200_TXA_ARG_A_ZERO		(0)
3118 #       define R200_TXA_ARG_A_MASK		(31 << 0)
3119 #       define R200_TXA_ARG_A_SHIFT		0
3120 #       define R200_TXA_ARG_B_ZERO		(0 << 5)
3145 #       define R200_TXA_ARG_C_ZERO		(0 << 10)
3185 #       define R200_TXA_OP_MADD			(0 << 28)
3190 #define R200_PP_TXABLEND2_0			0x2f0c
3191 #       define R200_TXA_TFACTOR_SEL_SHIFT	0
3192 #       define R200_TXA_TFACTOR_SEL_MASK	0x7
3194 #       define R200_TXA_TFACTOR1_SEL_MASK	(0x7 << 4)
3197 #       define R200_TXA_SCALE_1X		(0 << 8)
3206 #       define R200_TXA_CLAMP_WRAP		(0 << 12)
3210 #       define R200_TXA_OUTPUT_REG_NONE		(0 << 16)
3218 #       define R200_TXA_REPL_NORMAL		0
3228 #define R200_SE_VTX_FMT_0			0x2088
3229 #       define R200_VTX_XY			0 /* always have xy */
3230 #       define R200_VTX_Z0			(1<<0)
3239 #       define   R200_VTX_COLOR_NOT_PRESENT	0
3256 #define R200_SE_VTX_FMT_1			0x208c
3257 #       define R200_VTX_TEX0_COMP_CNT_SHIFT	0
3264 #define R200_SE_TCL_OUTPUT_VTX_FMT_0		0x2090
3265 #define R200_SE_TCL_OUTPUT_VTX_FMT_1		0x2094
3266 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL		0x2250
3267 #       define R200_OUTPUT_XYZW			(1<<0)
3276 #       define R200_OUTPUT_TEX_MASK		(0x3f<<16)
3280 #define R200_PP_CNTL_X				0x2cc4
3281 #define R200_PP_TXMULTI_CTL_0			0x2c1c
3282 #define R200_PP_TXMULTI_CTL_1			0x2c3c
3283 #define R200_PP_TXMULTI_CTL_2			0x2c5c
3284 #define R200_PP_TXMULTI_CTL_3			0x2c7c
3285 #define R200_PP_TXMULTI_CTL_4			0x2c9c
3286 #define R200_PP_TXMULTI_CTL_5			0x2cbc
3287 #define R200_SE_VTX_STATE_CNTL			0x2180
3291 #define RADEON_CP_ME_RAM_ADDR               0x07d4
3292 #define RADEON_CP_ME_RAM_RADDR              0x07d8
3293 #define RADEON_CP_ME_RAM_DATAH              0x07dc
3294 #define RADEON_CP_ME_RAM_DATAL              0x07e0
3296 #define RADEON_CP_RB_BASE                   0x0700
3297 #define RADEON_CP_RB_CNTL                   0x0704
3298 #	define RADEON_RB_BUFSZ_SHIFT		0
3299 #	define RADEON_RB_BUFSZ_MASK		(0x3f << 0)
3301 #	define RADEON_RB_BLKSZ_MASK		(0x3f << 8)
3304 #	define RADEON_MAX_FETCH_MASK		(0x3 << 18)
3307 #define RADEON_CP_RB_RPTR_ADDR              0x070c
3308 #define RADEON_CP_RB_RPTR                   0x0710
3309 #define RADEON_CP_RB_WPTR                   0x0714
3310 #define RADEON_CP_RB_RPTR_WR                0x071c
3312 #define RADEON_SCRATCH_UMSK		    0x0770
3313 #define RADEON_SCRATCH_ADDR		    0x0774
3315 #define R600_CP_RB_BASE                     0xc100
3316 #define R600_CP_RB_CNTL                     0xc104
3317 #       define R600_RB_BUFSZ(x)             ((x) << 0)
3321 #define R600_CP_RB_RPTR_WR                  0xc108
3322 #define R600_CP_RB_RPTR_ADDR                0xc10c
3323 #define R600_CP_RB_RPTR_ADDR_HI             0xc110
3324 #define R600_CP_RB_WPTR                     0xc114
3325 #define R600_CP_RB_WPTR_ADDR                0xc118
3326 #define R600_CP_RB_WPTR_ADDR_HI             0xc11c
3327 #define R600_CP_RB_RPTR                     0x8700
3328 #define R600_CP_RB_WPTR_DELAY               0x8704
3330 #define RADEON_CP_IB_BASE                   0x0738
3331 #define RADEON_CP_IB_BUFSZ                  0x073c
3333 #define RADEON_CP_CSQ_CNTL                  0x0740
3334 #       define RADEON_CSQ_CNT_PRIMARY_MASK     (0xff << 0)
3335 #       define RADEON_CSQ_PRIDIS_INDDIS        (0    << 28)
3342 #define R300_CP_RESYNC_ADDR                 0x778
3343 #define R300_CP_RESYNC_DATA                 0x77c
3345 #define RADEON_CP_CSQ_STAT                  0x07f8
3346 #       define RADEON_CSQ_RPTR_PRIMARY_MASK    (0xff <<  0)
3347 #       define RADEON_CSQ_WPTR_PRIMARY_MASK    (0xff <<  8)
3348 #       define RADEON_CSQ_RPTR_INDIRECT_MASK   (0xff << 16)
3349 #       define RADEON_CSQ_WPTR_INDIRECT_MASK   (0xff << 24)
3350 #define RADEON_CP_CSQ2_STAT                  0x07fc
3351 #define RADEON_CP_CSQ_ADDR                  0x07f0
3352 #define RADEON_CP_CSQ_DATA                  0x07f4
3353 #define RADEON_CP_CSQ_APER_PRIMARY          0x1000
3354 #define RADEON_CP_CSQ_APER_INDIRECT         0x1300
3356 #define RADEON_CP_RB_WPTR_DELAY             0x0718
3357 #       define RADEON_PRE_WRITE_TIMER_SHIFT    0
3359 #define RADEON_CP_CSQ_MODE		0x0744
3360 #	define RADEON_INDIRECT2_START_SHIFT	0
3361 #	define RADEON_INDIRECT2_START_MASK	(0x7f << 0)
3363 #	define RADEON_INDIRECT1_START_MASK	(0x7f << 8)
3365 #define RADEON_AIC_CNTL                     0x01d0
3366 #       define RADEON_PCIGART_TRANSLATE_EN     (1 << 0)
3369 #define RADEON_AIC_LO_ADDR                  0x01dc
3370 #define RADEON_AIC_PT_BASE		0x01d8
3371 #define RADEON_AIC_HI_ADDR		0x01e0
3382 #define RADEON_CP_PACKET0                           0x00000000
3383 #define RADEON_CP_PACKET1                           0x40000000
3384 #define RADEON_CP_PACKET2                           0x80000000
3385 #define RADEON_CP_PACKET3                           0xC0000000
3386 #       define RADEON_CP_PACKET_MASK                0xC0000000
3387 #       define RADEON_CP_PACKET_COUNT_MASK          0x3fff0000
3389 #       define RADEON_CP_PACKET0_REG_MASK           0x000007ff
3390 #       define R300_CP_PACKET0_REG_MASK             0x00001fff
3391 #       define R600_CP_PACKET0_REG_MASK             0x0000ffff
3392 #       define RADEON_CP_PACKET1_REG0_MASK          0x000007ff
3393 #       define RADEON_CP_PACKET1_REG1_MASK          0x003ff800
3395 #define RADEON_CP_PACKET0_ONE_REG_WR                0x00008000
3397 #define RADEON_CP_PACKET3_NOP                       0xC0001000
3398 #define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
3399 #define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
3400 #define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
3401 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
3402 #define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
3403 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
3404 #define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
3405 #define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
3406 #define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
3407 #define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
3408 #define R200_CP_PACKET3_3D_DRAW_IMMD_2              0xc0003500
3409 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
3410 #define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
3411 #define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
3412 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
3413 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
3414 #define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
3415 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
3416 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
3417 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
3418 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
3421 #define RADEON_CP_VC_FRMT_XY                        0x00000000
3422 #define RADEON_CP_VC_FRMT_W0                        0x00000001
3423 #define RADEON_CP_VC_FRMT_FPCOLOR                   0x00000002
3424 #define RADEON_CP_VC_FRMT_FPALPHA                   0x00000004
3425 #define RADEON_CP_VC_FRMT_PKCOLOR                   0x00000008
3426 #define RADEON_CP_VC_FRMT_FPSPEC                    0x00000010
3427 #define RADEON_CP_VC_FRMT_FPFOG                     0x00000020
3428 #define RADEON_CP_VC_FRMT_PKSPEC                    0x00000040
3429 #define RADEON_CP_VC_FRMT_ST0                       0x00000080
3430 #define RADEON_CP_VC_FRMT_ST1                       0x00000100
3431 #define RADEON_CP_VC_FRMT_Q1                        0x00000200
3432 #define RADEON_CP_VC_FRMT_ST2                       0x00000400
3433 #define RADEON_CP_VC_FRMT_Q2                        0x00000800
3434 #define RADEON_CP_VC_FRMT_ST3                       0x00001000
3435 #define RADEON_CP_VC_FRMT_Q3                        0x00002000
3436 #define RADEON_CP_VC_FRMT_Q0                        0x00004000
3437 #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK      0x00038000
3438 #define RADEON_CP_VC_FRMT_N0                        0x00040000
3439 #define RADEON_CP_VC_FRMT_XY1                       0x08000000
3440 #define RADEON_CP_VC_FRMT_Z1                        0x10000000
3441 #define RADEON_CP_VC_FRMT_W1                        0x20000000
3442 #define RADEON_CP_VC_FRMT_N1                        0x40000000
3443 #define RADEON_CP_VC_FRMT_Z                         0x80000000
3445 #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE            0x00000000
3446 #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT           0x00000001
3447 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE            0x00000002
3448 #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP      0x00000003
3449 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST        0x00000004
3450 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN         0x00000005
3451 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP       0x00000006
3452 #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2      0x00000007
3453 #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST       0x00000008
3454 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
3455 #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST  0x0000000a
3456 #define RADEON_CP_VC_CNTL_PRIM_WALK_IND             0x00000010
3457 #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST            0x00000020
3458 #define RADEON_CP_VC_CNTL_PRIM_WALK_RING            0x00000030
3459 #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA          0x00000000
3460 #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA          0x00000040
3461 #define RADEON_CP_VC_CNTL_MAOS_ENABLE               0x00000080
3462 #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE   0x00000000
3463 #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE       0x00000100
3464 #define RADEON_CP_VC_CNTL_TCL_DISABLE               0x00000000
3465 #define RADEON_CP_VC_CNTL_TCL_ENABLE                0x00000200
3468 #define RADEON_VS_MATRIX_0_ADDR                   0
3496 #define RADEON_SS_LIGHT_DCD_ADDR                  0
3507 #define RADEON_TV_MASTER_CNTL                    0x0800
3508 #       define RADEON_TV_ASYNC_RST               (1 <<  0)
3520 #define RADEON_TV_PRE_DAC_MUX_CNTL               0x0888
3521 #       define RADEON_Y_RED_EN                   (1 << 0)
3529 #define RADEON_TV_RGB_CNTL                           0x0804
3533 #       define RADEON_RGB_SRC_SEL_CRTC1		  (0 <<  8)
3542 #define RADEON_TV_SYNC_CNTL                          0x0808
3543 #       define RADEON_SYNC_OE                     (1 <<  0)
3549 #define RADEON_TV_HTOTAL                             0x080c
3550 #define RADEON_TV_HDISP                              0x0810
3551 #define RADEON_TV_HSTART                             0x0818
3552 #define RADEON_TV_HCOUNT                             0x081C
3553 #define RADEON_TV_VTOTAL                             0x0820
3554 #define RADEON_TV_VDISP                              0x0824
3555 #define RADEON_TV_VCOUNT                             0x0828
3556 #define RADEON_TV_FTOTAL                             0x082c
3557 #define RADEON_TV_FCOUNT                             0x0830
3558 #define RADEON_TV_FRESTART                           0x0834
3559 #define RADEON_TV_HRESTART                           0x0838
3560 #define RADEON_TV_VRESTART                           0x083c
3561 #define RADEON_TV_HOST_READ_DATA                     0x0840
3562 #define RADEON_TV_HOST_WRITE_DATA                    0x0844
3563 #define RADEON_TV_HOST_RD_WT_CNTL                    0x0848
3568 #define RADEON_TV_VSCALER_CNTL1                      0x084c
3569 #       define RADEON_UV_INC_MASK                0xffff
3570 #       define RADEON_UV_INC_SHIFT               0
3572 #       define RADEON_RESTART_FIELD              (1 << 29) /* restart on field 0 */
3574 #define RADEON_TV_TIMING_CNTL                        0x0850
3575 #       define RADEON_H_INC_MASK                 0xfff
3576 #       define RADEON_H_INC_SHIFT                0
3581 #define RADEON_TV_VSCALER_CNTL2                      0x0854
3582 #       define RADEON_DITHER_MODE                (1 <<  0)
3586 #define RADEON_TV_Y_FALL_CNTL                        0x0858
3589 #define RADEON_TV_Y_RISE_CNTL                        0x085c
3591 #define RADEON_TV_Y_SAW_TOOTH_CNTL                   0x0860
3592 #define RADEON_TV_UPSAMP_AND_GAIN_CNTL               0x0864
3593 #	define RADEON_YUPSAMP_EN		 (1 <<  0)
3595 #define RADEON_TV_GAIN_LIMIT_SETTINGS                0x0868
3596 #       define RADEON_Y_GAIN_LIMIT_SHIFT         0
3598 #define RADEON_TV_LINEAR_GAIN_SETTINGS               0x086c
3599 #       define RADEON_Y_GAIN_SHIFT               0
3601 #define RADEON_TV_MODULATOR_CNTL1                    0x0870
3610 #define RADEON_TV_MODULATOR_CNTL2                    0x0874
3611 #       define RADEON_TV_U_BURST_LEVEL_MASK     0x1ff
3612 #       define RADEON_TV_V_BURST_LEVEL_MASK     0x1ff
3614 #define RADEON_TV_CRC_CNTL                           0x0890
3615 #define RADEON_TV_UV_ADR                             0x08ac
3616 #	define RADEON_MAX_UV_ADR_MASK		 0x000000ff
3617 #	define RADEON_MAX_UV_ADR_SHIFT		 0
3618 #	define RADEON_TABLE1_BOT_ADR_MASK	 0x0000ff00
3620 #	define RADEON_TABLE3_TOP_ADR_MASK	 0x00ff0000
3622 #	define RADEON_HCODE_TABLE_SEL_MASK	 0x06000000
3624 #	define RADEON_VCODE_TABLE_SEL_MASK	 0x18000000
3626 #	define RADEON_TV_MAX_FIFO_ADDR		 0x1a7
3627 #	define RADEON_TV_MAX_FIFO_ADDR_INTERNAL	 0x1ff
3628 #define RADEON_TV_PLL_FINE_CNTL			     0x0020	/* PLL */
3629 #define RADEON_TV_PLL_CNTL                           0x0021	/* PLL */
3630 #       define RADEON_TV_M0LO_MASK               0xff
3631 #       define RADEON_TV_M0HI_MASK               0x7
3633 #       define RADEON_TV_N0LO_MASK               0x1ff
3635 #       define RADEON_TV_N0HI_MASK               0x3
3637 #       define RADEON_TV_P_MASK                  0xf
3641 #define RADEON_TV_PLL_CNTL1                          0x0022	/* PLL */
3654 #define RS400_DISP2_REQ_CNTL1			0xe30
3655 #       define RS400_DISP2_START_REQ_LEVEL_SHIFT   0
3656 #       define RS400_DISP2_START_REQ_LEVEL_MASK    0x3ff
3658 #       define RS400_DISP2_STOP_REQ_LEVEL_MASK     0x3ff
3660 #       define RS400_DISP2_ALLOW_FID_LEVEL_MASK    0x3ff
3661 #define RS400_DISP2_REQ_CNTL2			0xe34
3663 #       define RS400_DISP2_CRITICAL_POINT_START_MASK     0x3ff
3665 #       define RS400_DISP2_CRITICAL_POINT_STOP_MASK      0x3ff
3666 #define RS400_DMIF_MEM_CNTL1			0xe38
3667 #       define RS400_DISP2_START_ADR_SHIFT      0
3668 #       define RS400_DISP2_START_ADR_MASK       0x3ff
3670 #       define RS400_DISP1_CRITICAL_POINT_START_MASK     0x3ff
3672 #       define RS400_DISP1_CRITICAL_POINT_STOP_MASK      0x3ff
3673 #define RS400_DISP1_REQ_CNTL1			0xe3c
3674 #       define RS400_DISP1_START_REQ_LEVEL_SHIFT   0
3675 #       define RS400_DISP1_START_REQ_LEVEL_MASK    0x3ff
3677 #       define RS400_DISP1_STOP_REQ_LEVEL_MASK     0x3ff
3679 #       define RS400_DISP1_ALLOW_FID_LEVEL_MASK    0x3ff
3681 #define RADEON_PCIE_INDEX               0x0030
3682 #define RADEON_PCIE_DATA                0x0034
3683 #define RADEON_PCIE_TX_GART_CNTL	0x10
3684 #	define RADEON_PCIE_TX_GART_EN		(1 << 0)
3685 #	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
3688 #	define RADEON_PCIE_TX_GART_MODE_32_128_CACHE	(0 << 3)
3692 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
3693 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
3694 #define RADEON_PCIE_TX_GART_BASE	0x13
3695 #define RADEON_PCIE_TX_GART_START_LO	0x14
3696 #define RADEON_PCIE_TX_GART_START_HI	0x15
3697 #define RADEON_PCIE_TX_GART_END_LO	0x16
3698 #define RADEON_PCIE_TX_GART_END_HI	0x17
3699 #define RADEON_PCIE_TX_GART_ERROR	0x18
3701 #define RADEON_SCRATCH_REG0		0x15e0
3702 #define RADEON_SCRATCH_REG1		0x15e4
3703 #define RADEON_SCRATCH_REG2		0x15e8
3704 #define RADEON_SCRATCH_REG3		0x15ec
3705 #define RADEON_SCRATCH_REG4		0x15f0
3706 #define RADEON_SCRATCH_REG5		0x15f4
3708 #define RV530_GB_PIPE_SELECT2           0x4124
3711 #define RADEON_CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
3713 #define RADEON_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
3714 #define R100_CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
3715 #define R600_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
3716 #define RADEON_PACKET_TYPE0 0
3721 #define RADEON_PACKET3_NOP 0x10