344 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr)  in radeon_get_htiming_tables_addr()  argument
348 	switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) {  in radeon_get_htiming_tables_addr()
353 		h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2;  in radeon_get_htiming_tables_addr()
356 		h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2;  in radeon_get_htiming_tables_addr()
365 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr)  in radeon_get_vtiming_tables_addr()  argument
369 	switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) {  in radeon_get_vtiming_tables_addr()
371 		v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1;  in radeon_get_vtiming_tables_addr()
374 		v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1;  in radeon_get_vtiming_tables_addr()
377 		v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1;  in radeon_get_vtiming_tables_addr()
395 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);  in radeon_restore_tv_timing_tables()
396 	h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr);  in radeon_restore_tv_timing_tables()
397 	v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr);  in radeon_restore_tv_timing_tables()
711 	tv_dac->tv.tv_uv_adr = 0xc8;  in radeon_legacy_tv_mode_set()