Lines Matching refs:pll_ref_div
747 uint32_t pll_ref_div = 0; in radeon_set_pll() local
802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
836 pll_ref_div = reference_div; in radeon_set_pll()
850 pll_ref_div & 0x3ff, in radeon_set_pll()
860 &pll_ref_div, &pll_fb_post_div, in radeon_set_pll()
877 pll_ref_div, in radeon_set_pll()
900 (unsigned)pll_ref_div, in radeon_set_pll()
905 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, in radeon_set_pll()
923 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, in radeon_set_pll()
934 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && in radeon_set_pll()
967 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_set_pll()
972 pll_ref_div, in radeon_set_pll()
977 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_set_pll()
982 pll_ref_div, in radeon_set_pll()
1006 pll_ref_div, in radeon_set_pll()
1011 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, in radeon_set_pll()