Lines Matching +full:flip +full:- +full:horizontal
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
53 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
66 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
68 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
73 r = crtc->gamma_store; in avivo_crtc_load_lut()
74 g = r + crtc->gamma_size; in avivo_crtc_load_lut()
75 b = g + crtc->gamma_size; in avivo_crtc_load_lut()
84 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); in avivo_crtc_load_lut()
90 struct drm_device *dev = crtc->dev; in dce4_crtc_load_lut()
91 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_load_lut()
95 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce4_crtc_load_lut()
96 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
98 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
99 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
100 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
102 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
103 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
104 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
106 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
107 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce4_crtc_load_lut()
109 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
110 r = crtc->gamma_store; in dce4_crtc_load_lut()
111 g = r + crtc->gamma_size; in dce4_crtc_load_lut()
112 b = g + crtc->gamma_size; in dce4_crtc_load_lut()
114 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce4_crtc_load_lut()
124 struct drm_device *dev = crtc->dev; in dce5_crtc_load_lut()
125 struct radeon_device *rdev = dev->dev_private; in dce5_crtc_load_lut()
129 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce5_crtc_load_lut()
133 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
136 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
138 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
140 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
144 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
146 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
147 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
148 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
150 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
151 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
152 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
154 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
155 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce5_crtc_load_lut()
157 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
158 r = crtc->gamma_store; in dce5_crtc_load_lut()
159 g = r + crtc->gamma_size; in dce5_crtc_load_lut()
160 b = g + crtc->gamma_size; in dce5_crtc_load_lut()
162 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
168 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
173 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
176 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
179 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
180 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | in dce5_crtc_load_lut()
183 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
188 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
196 struct drm_device *dev = crtc->dev; in legacy_crtc_load_lut()
197 struct radeon_device *rdev = dev->dev_private; in legacy_crtc_load_lut()
203 if (radeon_crtc->crtc_id == 0) in legacy_crtc_load_lut()
210 r = crtc->gamma_store; in legacy_crtc_load_lut()
211 g = r + crtc->gamma_size; in legacy_crtc_load_lut()
212 b = g + crtc->gamma_size; in legacy_crtc_load_lut()
223 struct drm_device *dev = crtc->dev; in radeon_crtc_load_lut()
224 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_load_lut()
226 if (!crtc->enabled) in radeon_crtc_load_lut()
253 destroy_workqueue(radeon_crtc->flip_queue); in radeon_crtc_destroy()
258 * radeon_unpin_work_func - unpin old buffer object
271 r = radeon_bo_reserve(work->old_rbo, false); in radeon_unpin_work_func()
273 radeon_bo_unpin(work->old_rbo); in radeon_unpin_work_func()
274 radeon_bo_unreserve(work->old_rbo); in radeon_unpin_work_func()
276 DRM_ERROR("failed to reserve buffer after flip\n"); in radeon_unpin_work_func()
278 drm_gem_object_put(&work->old_rbo->tbo.base); in radeon_unpin_work_func()
284 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
295 * irqs are a reliable and race-free method of handling pageflip in radeon_crtc_handle_vblank()
305 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_vblank()
306 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_vblank()
307 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " in radeon_crtc_handle_vblank()
309 radeon_crtc->flip_status, in radeon_crtc_handle_vblank()
311 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_vblank()
323 * know the flip will complete at leading edge of the upcoming real in radeon_crtc_handle_vblank()
324 * vblank. On pre-AVIVO hardware, flips also complete inside the real in radeon_crtc_handle_vblank()
326 * == inside real vblank, the flip will complete almost immediately. in radeon_crtc_handle_vblank()
329 * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op, in radeon_crtc_handle_vblank()
330 * but the flip still gets programmed into hw and completed during in radeon_crtc_handle_vblank()
331 * vblank, leading to a delayed emission of the flip completion event. in radeon_crtc_handle_vblank()
332 * This applies at least to pre-AVIVO hardware, where flips are always in radeon_crtc_handle_vblank()
340 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
342 /* crtc didn't flip in this target vblank interval, in radeon_crtc_handle_vblank()
343 * but flip is pending in crtc. Based on the current in radeon_crtc_handle_vblank()
345 * (nearly) complete and the flip will (likely) in radeon_crtc_handle_vblank()
350 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_vblank()
356 * radeon_crtc_handle_flip - page flip completed
361 * Called when we are sure that a page flip for this crtc is completed.
365 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
373 spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_flip()
374 work = radeon_crtc->flip_work; in radeon_crtc_handle_flip()
375 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_flip()
376 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " in radeon_crtc_handle_flip()
378 radeon_crtc->flip_status, in radeon_crtc_handle_flip()
380 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_flip()
385 radeon_crtc->flip_status = RADEON_FLIP_NONE; in radeon_crtc_handle_flip()
386 radeon_crtc->flip_work = NULL; in radeon_crtc_handle_flip()
389 if (work->event) in radeon_crtc_handle_flip()
390 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); in radeon_crtc_handle_flip()
392 spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); in radeon_crtc_handle_flip()
394 drm_crtc_vblank_put(&radeon_crtc->base); in radeon_crtc_handle_flip()
395 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); in radeon_crtc_handle_flip()
396 queue_work(radeon_crtc->flip_queue, &work->unpin_work); in radeon_crtc_handle_flip()
400 * radeon_flip_work_func - page flip framebuffer
404 * Wait for the buffer object to become idle and do the actual page flip
410 struct radeon_device *rdev = work->rdev; in radeon_flip_work_func()
412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
414 struct drm_crtc *crtc = &radeon_crtc->base; in radeon_flip_work_func()
419 down_read(&rdev->exclusive_lock); in radeon_flip_work_func()
420 if (work->fence) { in radeon_flip_work_func()
423 fence = to_radeon_fence(work->fence); in radeon_flip_work_func()
424 if (fence && fence->rdev == rdev) { in radeon_flip_work_func()
426 if (r == -EDEADLK) { in radeon_flip_work_func()
427 up_read(&rdev->exclusive_lock); in radeon_flip_work_func()
430 } while (r == -EAGAIN); in radeon_flip_work_func()
431 down_read(&rdev->exclusive_lock); in radeon_flip_work_func()
434 r = dma_fence_wait(work->fence, false); in radeon_flip_work_func()
437 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r); in radeon_flip_work_func()
439 /* We continue with the page flip even if we failed to wait on in radeon_flip_work_func()
444 dma_fence_put(work->fence); in radeon_flip_work_func()
445 work->fence = NULL; in radeon_flip_work_func()
449 * targeted by the flip. Always wait on pre DCE4 to avoid races with in radeon_flip_work_func()
450 * flip completion handling from vblank irq, as these old asics don't in radeon_flip_work_func()
453 while (radeon_crtc->enabled && in radeon_flip_work_func()
454 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0, in radeon_flip_work_func()
456 &crtc->hwmode) in radeon_flip_work_func()
460 ((int) (work->target_vblank - in radeon_flip_work_func()
461 crtc->funcs->get_vblank_counter(crtc)) > 0))) in radeon_flip_work_func()
465 spin_lock_irqsave(&crtc->dev->event_lock, flags); in radeon_flip_work_func()
468 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); in radeon_flip_work_func()
470 /* do the flip (mmio) */ in radeon_flip_work_func()
471 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async); in radeon_flip_work_func()
473 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; in radeon_flip_work_func()
474 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_flip_work_func()
475 up_read(&rdev->exclusive_lock); in radeon_flip_work_func()
485 struct drm_device *dev = crtc->dev; in radeon_crtc_page_flip_target()
486 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_page_flip_target()
498 return -ENOMEM; in radeon_crtc_page_flip_target()
500 INIT_WORK(&work->flip_work, radeon_flip_work_func); in radeon_crtc_page_flip_target()
501 INIT_WORK(&work->unpin_work, radeon_unpin_work_func); in radeon_crtc_page_flip_target()
503 work->rdev = rdev; in radeon_crtc_page_flip_target()
504 work->crtc_id = radeon_crtc->crtc_id; in radeon_crtc_page_flip_target()
505 work->event = event; in radeon_crtc_page_flip_target()
506 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; in radeon_crtc_page_flip_target()
509 obj = crtc->primary->fb->obj[0]; in radeon_crtc_page_flip_target()
513 work->old_rbo = gem_to_radeon_bo(obj); in radeon_crtc_page_flip_target()
515 obj = fb->obj[0]; in radeon_crtc_page_flip_target()
519 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n", in radeon_crtc_page_flip_target()
520 work->old_rbo, new_rbo); in radeon_crtc_page_flip_target()
524 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); in radeon_crtc_page_flip_target()
532 r = -EINVAL; in radeon_crtc_page_flip_target()
533 DRM_ERROR("failed to pin new rbo buffer before flip\n"); in radeon_crtc_page_flip_target()
536 r = dma_resv_get_singleton(new_rbo->tbo.base.resv, DMA_RESV_USAGE_WRITE, in radeon_crtc_page_flip_target()
537 &work->fence); in radeon_crtc_page_flip_target()
548 base -= radeon_crtc->legacy_display_base_addr; in radeon_crtc_page_flip_target()
549 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; in radeon_crtc_page_flip_target()
555 int byteshift = fb->format->cpp[0] * 8 >> 4; in radeon_crtc_page_flip_target()
556 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11; in radeon_crtc_page_flip_target()
557 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8); in radeon_crtc_page_flip_target()
560 int offset = crtc->y * pitch_pixels + crtc->x; in radeon_crtc_page_flip_target()
561 switch (fb->format->cpp[0] * 8) { in radeon_crtc_page_flip_target()
581 work->base = base; in radeon_crtc_page_flip_target()
582 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + in radeon_crtc_page_flip_target()
583 crtc->funcs->get_vblank_counter(crtc); in radeon_crtc_page_flip_target()
586 spin_lock_irqsave(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
588 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { in radeon_crtc_page_flip_target()
589 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); in radeon_crtc_page_flip_target()
590 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
591 r = -EBUSY; in radeon_crtc_page_flip_target()
594 radeon_crtc->flip_status = RADEON_FLIP_PENDING; in radeon_crtc_page_flip_target()
595 radeon_crtc->flip_work = work; in radeon_crtc_page_flip_target()
598 crtc->primary->fb = fb; in radeon_crtc_page_flip_target()
600 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in radeon_crtc_page_flip_target()
602 queue_work(radeon_crtc->flip_queue, &work->flip_work); in radeon_crtc_page_flip_target()
614 drm_gem_object_put(&work->old_rbo->tbo.base); in radeon_crtc_page_flip_target()
615 dma_fence_put(work->fence); in radeon_crtc_page_flip_target()
630 if (!set || !set->crtc) in radeon_crtc_set_config()
631 return -EINVAL; in radeon_crtc_set_config()
633 dev = set->crtc->dev; in radeon_crtc_set_config()
635 ret = pm_runtime_get_sync(dev->dev); in radeon_crtc_set_config()
637 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
643 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) in radeon_crtc_set_config()
644 if (crtc->enabled) in radeon_crtc_set_config()
647 pm_runtime_mark_last_busy(dev->dev); in radeon_crtc_set_config()
649 rdev = dev->dev_private; in radeon_crtc_set_config()
652 if (active && !rdev->have_disp_power_ref) { in radeon_crtc_set_config()
653 rdev->have_disp_power_ref = true; in radeon_crtc_set_config()
658 if (!active && rdev->have_disp_power_ref) { in radeon_crtc_set_config()
659 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
660 rdev->have_disp_power_ref = false; in radeon_crtc_set_config()
664 pm_runtime_put_autosuspend(dev->dev); in radeon_crtc_set_config()
683 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_init()
690 radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0); in radeon_crtc_init()
691 if (!radeon_crtc->flip_queue) { in radeon_crtc_init()
696 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); in radeon_crtc_init()
698 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); in radeon_crtc_init()
699 radeon_crtc->crtc_id = index; in radeon_crtc_init()
700 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
702 if (rdev->family >= CHIP_BONAIRE) { in radeon_crtc_init()
703 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; in radeon_crtc_init()
704 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; in radeon_crtc_init()
706 radeon_crtc->max_cursor_width = CURSOR_WIDTH; in radeon_crtc_init()
707 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; in radeon_crtc_init()
709 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; in radeon_crtc_init()
710 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; in radeon_crtc_init()
712 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) in radeon_crtc_init()
778 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in radeon_print_display_setup()
781 DRM_INFO(" %s\n", connector->name); in radeon_print_display_setup()
782 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in radeon_print_display_setup()
783 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); in radeon_print_display_setup()
784 if (radeon_connector->ddc_bus) { in radeon_print_display_setup()
786 radeon_connector->ddc_bus->rec.mask_clk_reg, in radeon_print_display_setup()
787 radeon_connector->ddc_bus->rec.mask_data_reg, in radeon_print_display_setup()
788 radeon_connector->ddc_bus->rec.a_clk_reg, in radeon_print_display_setup()
789 radeon_connector->ddc_bus->rec.a_data_reg, in radeon_print_display_setup()
790 radeon_connector->ddc_bus->rec.en_clk_reg, in radeon_print_display_setup()
791 radeon_connector->ddc_bus->rec.en_data_reg, in radeon_print_display_setup()
792 radeon_connector->ddc_bus->rec.y_clk_reg, in radeon_print_display_setup()
793 radeon_connector->ddc_bus->rec.y_data_reg); in radeon_print_display_setup()
794 if (radeon_connector->router.ddc_valid) in radeon_print_display_setup()
796 radeon_connector->router.ddc_mux_control_pin, in radeon_print_display_setup()
797 radeon_connector->router.ddc_mux_state); in radeon_print_display_setup()
798 if (radeon_connector->router.cd_valid) in radeon_print_display_setup()
800 radeon_connector->router.cd_mux_control_pin, in radeon_print_display_setup()
801 radeon_connector->router.cd_mux_state); in radeon_print_display_setup()
803 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || in radeon_print_display_setup()
804 connector->connector_type == DRM_MODE_CONNECTOR_DVII || in radeon_print_display_setup()
805 connector->connector_type == DRM_MODE_CONNECTOR_DVID || in radeon_print_display_setup()
806 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || in radeon_print_display_setup()
807 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || in radeon_print_display_setup()
808 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) in radeon_print_display_setup()
809 …DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); in radeon_print_display_setup()
812 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_print_display_setup()
814 devices = radeon_encoder->devices & radeon_connector->devices; in radeon_print_display_setup()
817 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
819 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
821 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
823 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
825 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
827 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
829 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
831 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
833 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
835 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
837 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); in radeon_print_display_setup()
846 struct radeon_device *rdev = dev->dev_private; in radeon_setup_enc_conn()
849 if (rdev->bios) { in radeon_setup_enc_conn()
850 if (rdev->is_atom_bios) { in radeon_setup_enc_conn()
874 * avivo_reduce_ratio - fractional number reduction
911 * avivo_get_fb_ref_div - feedback and ref divider calculation
943 * radeon_compute_pll_avivo - compute PLL paramaters
964 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
974 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
975 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
977 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
983 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
984 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
986 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
988 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
989 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
990 ref_div_max = pll->reference_div; in radeon_compute_pll_avivo()
991 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
993 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()
995 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()
998 if (pll->flags & RADEON_PLL_USE_POST_DIV) { in radeon_compute_pll_avivo()
999 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1000 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1004 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_avivo()
1005 vco_min = pll->lcd_pll_out_min; in radeon_compute_pll_avivo()
1006 vco_max = pll->lcd_pll_out_max; in radeon_compute_pll_avivo()
1008 vco_min = pll->pll_out_min; in radeon_compute_pll_avivo()
1009 vco_max = pll->pll_out_max; in radeon_compute_pll_avivo()
1012 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1020 if (post_div_min < pll->min_post_div) in radeon_compute_pll_avivo()
1021 post_div_min = pll->min_post_div; in radeon_compute_pll_avivo()
1025 --post_div_max; in radeon_compute_pll_avivo()
1026 if (post_div_max > pll->max_post_div) in radeon_compute_pll_avivo()
1027 post_div_max = pll->max_post_div; in radeon_compute_pll_avivo()
1032 den = pll->reference_freq; in radeon_compute_pll_avivo()
1038 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
1048 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1052 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { in radeon_compute_pll_avivo()
1069 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { in radeon_compute_pll_avivo()
1070 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); in radeon_compute_pll_avivo()
1079 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1087 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + in radeon_compute_pll_avivo()
1088 (pll->reference_freq * *frac_fb_div_p)) / in radeon_compute_pll_avivo()
1093 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", in radeon_compute_pll_avivo()
1098 /* pre-avivo */
1115 uint32_t min_ref_div = pll->min_ref_div; in radeon_compute_pll_legacy()
1116 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy()
1117 uint32_t min_post_div = pll->min_post_div; in radeon_compute_pll_legacy()
1118 uint32_t max_post_div = pll->max_post_div; in radeon_compute_pll_legacy()
1121 uint32_t best_vco = pll->best_vco; in radeon_compute_pll_legacy()
1126 uint32_t best_freq = -1; in radeon_compute_pll_legacy()
1132 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()
1135 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_legacy()
1136 pll_out_min = pll->lcd_pll_out_min; in radeon_compute_pll_legacy()
1137 pll_out_max = pll->lcd_pll_out_max; in radeon_compute_pll_legacy()
1139 pll_out_min = pll->pll_out_min; in radeon_compute_pll_legacy()
1140 pll_out_max = pll->pll_out_max; in radeon_compute_pll_legacy()
1146 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_legacy()
1147 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()
1149 while (min_ref_div < max_ref_div-1) { in radeon_compute_pll_legacy()
1151 uint32_t pll_in = pll->reference_freq / mid; in radeon_compute_pll_legacy()
1152 if (pll_in < pll->pll_in_min) in radeon_compute_pll_legacy()
1154 else if (pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1161 if (pll->flags & RADEON_PLL_USE_POST_DIV) in radeon_compute_pll_legacy()
1162 min_post_div = max_post_div = pll->post_div; in radeon_compute_pll_legacy()
1164 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_legacy()
1165 min_fractional_feed_div = pll->min_frac_feedback_div; in radeon_compute_pll_legacy()
1166 max_fractional_feed_div = pll->max_frac_feedback_div; in radeon_compute_pll_legacy()
1169 for (post_div = max_post_div; post_div >= min_post_div; --post_div) { in radeon_compute_pll_legacy()
1172 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) in radeon_compute_pll_legacy()
1176 if (pll->flags & RADEON_PLL_LEGACY) { in radeon_compute_pll_legacy()
1190 uint32_t pll_in = pll->reference_freq / ref_div; in radeon_compute_pll_legacy()
1191 uint32_t min_feed_div = pll->min_feedback_div; in radeon_compute_pll_legacy()
1192 uint32_t max_feed_div = pll->max_feedback_div + 1; in radeon_compute_pll_legacy()
1194 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1206 tmp = (uint64_t)pll->reference_freq * feedback_div; in radeon_compute_pll_legacy()
1219 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; in radeon_compute_pll_legacy()
1220 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; in radeon_compute_pll_legacy()
1223 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { in radeon_compute_pll_legacy()
1227 error = freq - current_freq; in radeon_compute_pll_legacy()
1229 error = abs(current_freq - freq); in radeon_compute_pll_legacy()
1230 vco_diff = abs(vco - best_vco); in radeon_compute_pll_legacy()
1234 ((best_error > 100 && error < best_error - 100) || in radeon_compute_pll_legacy()
1235 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { in radeon_compute_pll_legacy()
1244 if (best_freq == -1) { in radeon_compute_pll_legacy()
1252 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || in radeon_compute_pll_legacy()
1253 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || in radeon_compute_pll_legacy()
1254 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || in radeon_compute_pll_legacy()
1255 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || in radeon_compute_pll_legacy()
1256 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || in radeon_compute_pll_legacy()
1257 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { in radeon_compute_pll_legacy()
1285 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", in radeon_compute_pll_legacy()
1304 fb->obj[0] = obj; in radeon_framebuffer_init()
1308 fb->obj[0] = NULL; in radeon_framebuffer_init()
1323 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); in radeon_user_framebuffer_create()
1325 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, " in radeon_user_framebuffer_create()
1326 "can't create framebuffer\n", mode_cmd->handles[0]); in radeon_user_framebuffer_create()
1327 return ERR_PTR(-ENOENT); in radeon_user_framebuffer_create()
1330 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ in radeon_user_framebuffer_create()
1331 if (obj->import_attach) { in radeon_user_framebuffer_create()
1334 return ERR_PTR(-EINVAL); in radeon_user_framebuffer_create()
1340 return ERR_PTR(-ENOMEM); in radeon_user_framebuffer_create()
1365 { TV_STD_PAL_M, "pal-m" },
1366 { TV_STD_PAL_60, "pal-60" },
1367 { TV_STD_NTSC_J, "ntsc-j" },
1368 { TV_STD_SCART_PAL, "scart-pal" },
1369 { TV_STD_PAL_CN, "pal-cn" },
1402 if (rdev->is_atom_bios) { in radeon_modeset_create_props()
1403 rdev->mode_info.coherent_mode_property = in radeon_modeset_create_props()
1405 if (!rdev->mode_info.coherent_mode_property) in radeon_modeset_create_props()
1406 return -ENOMEM; in radeon_modeset_create_props()
1411 rdev->mode_info.tmds_pll_property = in radeon_modeset_create_props()
1417 rdev->mode_info.load_detect_property = in radeon_modeset_create_props()
1419 if (!rdev->mode_info.load_detect_property) in radeon_modeset_create_props()
1420 return -ENOMEM; in radeon_modeset_create_props()
1425 rdev->mode_info.tv_std_property = in radeon_modeset_create_props()
1431 rdev->mode_info.underscan_property = in radeon_modeset_create_props()
1436 rdev->mode_info.underscan_hborder_property = in radeon_modeset_create_props()
1439 if (!rdev->mode_info.underscan_hborder_property) in radeon_modeset_create_props()
1440 return -ENOMEM; in radeon_modeset_create_props()
1442 rdev->mode_info.underscan_vborder_property = in radeon_modeset_create_props()
1445 if (!rdev->mode_info.underscan_vborder_property) in radeon_modeset_create_props()
1446 return -ENOMEM; in radeon_modeset_create_props()
1449 rdev->mode_info.audio_property = in radeon_modeset_create_props()
1455 rdev->mode_info.dither_property = in radeon_modeset_create_props()
1461 rdev->mode_info.output_csc_property = in radeon_modeset_create_props()
1479 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && in radeon_update_display_priority()
1480 !(rdev->flags & RADEON_IS_IGP)) in radeon_update_display_priority()
1481 rdev->disp_priority = 2; in radeon_update_display_priority()
1483 rdev->disp_priority = 0; in radeon_update_display_priority()
1485 rdev->disp_priority = radeon_disp_priority; in radeon_update_display_priority()
1497 rdev->mode_info.afmt[i] = NULL; in radeon_afmt_init()
1509 0x13830 - 0x7030, in radeon_afmt_init()
1530 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1531 if (rdev->mode_info.afmt[i]) { in radeon_afmt_init()
1532 rdev->mode_info.afmt[i]->offset = eg_offsets[i]; in radeon_afmt_init()
1533 rdev->mode_info.afmt[i]->id = i; in radeon_afmt_init()
1538 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1539 if (rdev->mode_info.afmt[0]) { in radeon_afmt_init()
1540 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; in radeon_afmt_init()
1541 rdev->mode_info.afmt[0]->id = 0; in radeon_afmt_init()
1543 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1544 if (rdev->mode_info.afmt[1]) { in radeon_afmt_init()
1545 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; in radeon_afmt_init()
1546 rdev->mode_info.afmt[1]->id = 1; in radeon_afmt_init()
1550 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1551 if (rdev->mode_info.afmt[0]) { in radeon_afmt_init()
1552 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; in radeon_afmt_init()
1553 rdev->mode_info.afmt[0]->id = 0; in radeon_afmt_init()
1556 if (rdev->family >= CHIP_R600) { in radeon_afmt_init()
1557 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); in radeon_afmt_init()
1558 if (rdev->mode_info.afmt[1]) { in radeon_afmt_init()
1559 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; in radeon_afmt_init()
1560 rdev->mode_info.afmt[1]->id = 1; in radeon_afmt_init()
1571 kfree(rdev->mode_info.afmt[i]); in radeon_afmt_fini()
1572 rdev->mode_info.afmt[i] = NULL; in radeon_afmt_fini()
1582 rdev->mode_info.mode_config_initialized = true; in radeon_modeset_init()
1584 rdev_to_drm(rdev)->mode_config.funcs = &radeon_mode_funcs; in radeon_modeset_init()
1586 if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600) in radeon_modeset_init()
1587 rdev_to_drm(rdev)->mode_config.async_page_flip = true; in radeon_modeset_init()
1590 rdev_to_drm(rdev)->mode_config.max_width = 16384; in radeon_modeset_init()
1591 rdev_to_drm(rdev)->mode_config.max_height = 16384; in radeon_modeset_init()
1593 rdev_to_drm(rdev)->mode_config.max_width = 8192; in radeon_modeset_init()
1594 rdev_to_drm(rdev)->mode_config.max_height = 8192; in radeon_modeset_init()
1596 rdev_to_drm(rdev)->mode_config.max_width = 4096; in radeon_modeset_init()
1597 rdev_to_drm(rdev)->mode_config.max_height = 4096; in radeon_modeset_init()
1600 rdev_to_drm(rdev)->mode_config.preferred_depth = 24; in radeon_modeset_init()
1601 rdev_to_drm(rdev)->mode_config.prefer_shadow = 1; in radeon_modeset_init()
1603 rdev_to_drm(rdev)->mode_config.fb_modifiers_not_supported = true; in radeon_modeset_init()
1613 /* check combios for a valid hardcoded EDID - Sun servers */ in radeon_modeset_init()
1614 if (!rdev->is_atom_bios) { in radeon_modeset_init()
1620 for (i = 0; i < rdev->num_crtc; i++) { in radeon_modeset_init()
1631 if (rdev->is_atom_bios) { in radeon_modeset_init()
1652 if (rdev->mode_info.mode_config_initialized) { in radeon_modeset_fini()
1658 rdev->mode_info.mode_config_initialized = false; in radeon_modeset_fini()
1661 drm_edid_free(rdev->mode_info.bios_hardcoded_edid); in radeon_modeset_fini()
1670 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ in is_hdtv_mode()
1671 (mode->vdisplay == 576) || /* 576p */ in is_hdtv_mode()
1672 (mode->vdisplay == 720) || /* 720p */ in is_hdtv_mode()
1673 (mode->vdisplay == 1080)) /* 1080p */ in is_hdtv_mode()
1683 struct drm_device *dev = crtc->dev; in radeon_crtc_scaling_mode_fixup()
1684 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_scaling_mode_fixup()
1693 radeon_crtc->h_border = 0; in radeon_crtc_scaling_mode_fixup()
1694 radeon_crtc->v_border = 0; in radeon_crtc_scaling_mode_fixup()
1696 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_crtc_scaling_mode_fixup()
1697 if (encoder->crtc != crtc) in radeon_crtc_scaling_mode_fixup()
1704 if (radeon_encoder->rmx_type == RMX_OFF) in radeon_crtc_scaling_mode_fixup()
1705 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1706 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || in radeon_crtc_scaling_mode_fixup()
1707 mode->vdisplay < radeon_encoder->native_mode.vdisplay) in radeon_crtc_scaling_mode_fixup()
1708 radeon_crtc->rmx_type = radeon_encoder->rmx_type; in radeon_crtc_scaling_mode_fixup()
1710 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1712 memcpy(&radeon_crtc->native_mode, in radeon_crtc_scaling_mode_fixup()
1713 &radeon_encoder->native_mode, in radeon_crtc_scaling_mode_fixup()
1715 src_v = crtc->mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1716 dst_v = radeon_crtc->native_mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1717 src_h = crtc->mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1718 dst_h = radeon_crtc->native_mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1722 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && in radeon_crtc_scaling_mode_fixup()
1723 ((radeon_encoder->underscan_type == UNDERSCAN_ON) || in radeon_crtc_scaling_mode_fixup()
1724 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && in radeon_crtc_scaling_mode_fixup()
1725 connector->display_info.is_hdmi && in radeon_crtc_scaling_mode_fixup()
1727 if (radeon_encoder->underscan_hborder != 0) in radeon_crtc_scaling_mode_fixup()
1728 radeon_crtc->h_border = radeon_encoder->underscan_hborder; in radeon_crtc_scaling_mode_fixup()
1730 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1731 if (radeon_encoder->underscan_vborder != 0) in radeon_crtc_scaling_mode_fixup()
1732 radeon_crtc->v_border = radeon_encoder->underscan_vborder; in radeon_crtc_scaling_mode_fixup()
1734 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1735 radeon_crtc->rmx_type = RMX_FULL; in radeon_crtc_scaling_mode_fixup()
1736 src_v = crtc->mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1737 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); in radeon_crtc_scaling_mode_fixup()
1738 src_h = crtc->mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1739 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); in radeon_crtc_scaling_mode_fixup()
1743 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { in radeon_crtc_scaling_mode_fixup()
1755 if (radeon_crtc->rmx_type != RMX_OFF) { in radeon_crtc_scaling_mode_fixup()
1759 radeon_crtc->vsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1762 radeon_crtc->hsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1764 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1765 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1787 * \param *hpos Location where horizontal scanout position should go.
1795 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1816 struct radeon_device *rdev = dev->dev_private; in radeon_get_crtc_scanoutpos()
1879 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ in radeon_get_crtc_scanoutpos()
1912 /* Decode into vertical and horizontal scanout position. */ in radeon_get_crtc_scanoutpos()
1925 vbl_start = mode->crtc_vdisplay; in radeon_get_crtc_scanoutpos()
1932 *hpos = *vpos - vbl_start; in radeon_get_crtc_scanoutpos()
1946 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
1959 *vpos -= vbl_start; in radeon_get_crtc_scanoutpos()
1971 vtotal = mode->crtc_vtotal; in radeon_get_crtc_scanoutpos()
1972 *vpos = *vpos - vtotal; in radeon_get_crtc_scanoutpos()
1976 *vpos = *vpos - vbl_end; in radeon_get_crtc_scanoutpos()
1987 struct drm_device *dev = crtc->dev; in radeon_get_crtc_scanout_position()
1988 unsigned int pipe = crtc->index; in radeon_get_crtc_scanout_position()