58 	post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;  in radeon_legacy_get_engine_clock()
404 	tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_engine_clock()
406 	WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_engine_clock()
448 	tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_engine_clock()
465 	WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_engine_clock()
482 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
496 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
500 				tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
519 				WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
556 				tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
572 				WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
637 				tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
640 				WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
669 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
687 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
742 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
750 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
753 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
762 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
797 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
806 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()
842 			tmp = RREG32_PLL(RADEON_SCLK_CNTL);  in radeon_legacy_set_clock_gating()
867 			WREG32_PLL(RADEON_SCLK_CNTL, tmp);  in radeon_legacy_set_clock_gating()