Lines Matching refs:gpu_offset
1020 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1082 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1084 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1103 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1212 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1243 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1279 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1282 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1293 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1295 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
1306 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1375 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1384 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1673 offset = reloc->gpu_offset + in r600_packet3_check()
1714 offset = reloc->gpu_offset + in r600_packet3_check()
1766 offset = reloc->gpu_offset + in r600_packet3_check()
1806 offset = reloc->gpu_offset + tmp; in r600_packet3_check()
1836 offset = reloc->gpu_offset + tmp; in r600_packet3_check()
1862 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1878 offset = reloc->gpu_offset + in r600_packet3_check()
1900 offset = reloc->gpu_offset + in r600_packet3_check()
1965 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1979 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2009 offset64 = reloc->gpu_offset + offset; in r600_packet3_check()
2119 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2152 offset += reloc->gpu_offset; in r600_packet3_check()
2171 offset += reloc->gpu_offset; in r600_packet3_check()
2200 offset += reloc->gpu_offset; in r600_packet3_check()
2225 offset += reloc->gpu_offset; in r600_packet3_check()
2249 offset += reloc->gpu_offset; in r600_packet3_check()
2409 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2415 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2416 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2443 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2447 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2448 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2453 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2454 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2458 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2468 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2469 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2470 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2471 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2479 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2480 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2481 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2482 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2514 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2515 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()