Lines Matching full:track
43 /* value we track */
299 static void r600_cs_track_init(struct r600_cs_track *track) in r600_cs_track_init() argument
304 track->sq_config = DX9_CONSTS; in r600_cs_track_init()
306 track->cb_color_base_last[i] = 0; in r600_cs_track_init()
307 track->cb_color_size[i] = 0; in r600_cs_track_init()
308 track->cb_color_size_idx[i] = 0; in r600_cs_track_init()
309 track->cb_color_info[i] = 0; in r600_cs_track_init()
310 track->cb_color_view[i] = 0xFFFFFFFF; in r600_cs_track_init()
311 track->cb_color_bo[i] = NULL; in r600_cs_track_init()
312 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
313 track->cb_color_bo_mc[i] = 0xFFFFFFFF; in r600_cs_track_init()
314 track->cb_color_frag_bo[i] = NULL; in r600_cs_track_init()
315 track->cb_color_frag_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
316 track->cb_color_tile_bo[i] = NULL; in r600_cs_track_init()
317 track->cb_color_tile_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
318 track->cb_color_mask[i] = 0xFFFFFFFF; in r600_cs_track_init()
320 track->is_resolve = false; in r600_cs_track_init()
321 track->nsamples = 16; in r600_cs_track_init()
322 track->log_nsamples = 4; in r600_cs_track_init()
323 track->cb_target_mask = 0xFFFFFFFF; in r600_cs_track_init()
324 track->cb_shader_mask = 0xFFFFFFFF; in r600_cs_track_init()
325 track->cb_dirty = true; in r600_cs_track_init()
326 track->db_bo = NULL; in r600_cs_track_init()
327 track->db_bo_mc = 0xFFFFFFFF; in r600_cs_track_init()
329 track->db_depth_info = 7 | (1 << 25); in r600_cs_track_init()
330 track->db_depth_view = 0xFFFFC000; in r600_cs_track_init()
331 track->db_depth_size = 0xFFFFFFFF; in r600_cs_track_init()
332 track->db_depth_size_idx = 0; in r600_cs_track_init()
333 track->db_depth_control = 0xFFFFFFFF; in r600_cs_track_init()
334 track->db_dirty = true; in r600_cs_track_init()
335 track->htile_bo = NULL; in r600_cs_track_init()
336 track->htile_offset = 0xFFFFFFFF; in r600_cs_track_init()
337 track->htile_surface = 0; in r600_cs_track_init()
340 track->vgt_strmout_size[i] = 0; in r600_cs_track_init()
341 track->vgt_strmout_bo[i] = NULL; in r600_cs_track_init()
342 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in r600_cs_track_init()
343 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF; in r600_cs_track_init()
345 track->streamout_dirty = true; in r600_cs_track_init()
346 track->sx_misc_kill_all_prims = false; in r600_cs_track_init()
351 struct r600_cs_track *track = p->track; in r600_cs_track_validate_cb() local
360 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples; in r600_cs_track_validate_cb()
362 format = G_0280A0_FORMAT(track->cb_color_info[i]); in r600_cs_track_validate_cb()
366 i, track->cb_color_info[i]); in r600_cs_track_validate_cb()
370 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; in r600_cs_track_validate_cb()
371 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1; in r600_cs_track_validate_cb()
376 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]); in r600_cs_track_validate_cb()
378 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i]; in r600_cs_track_validate_cb()
380 array_check.group_size = track->group_size; in r600_cs_track_validate_cb()
381 array_check.nbanks = track->nbanks; in r600_cs_track_validate_cb()
382 array_check.npipes = track->npipes; in r600_cs_track_validate_cb()
388 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, in r600_cs_track_validate_cb()
389 track->cb_color_info[i]); in r600_cs_track_validate_cb()
406 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, in r600_cs_track_validate_cb()
407 track->cb_color_info[i]); in r600_cs_track_validate_cb()
434 tmp += track->cb_color_view[i] & 0xFF; in r600_cs_track_validate_cb()
438 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp; in r600_cs_track_validate_cb()
441 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { in r600_cs_track_validate_cb()
452 track->cb_color_bo_offset[i], tmp, in r600_cs_track_validate_cb()
453 radeon_bo_size(track->cb_color_bo[i]), in r600_cs_track_validate_cb()
466 ib[track->cb_color_size_idx[i]] = tmp; in r600_cs_track_validate_cb()
469 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) { in r600_cs_track_validate_cb()
473 if (track->nsamples > 1) { in r600_cs_track_validate_cb()
474 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]); in r600_cs_track_validate_cb()
477 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); in r600_cs_track_validate_cb()
479 if (bytes + track->cb_color_frag_offset[i] > in r600_cs_track_validate_cb()
480 radeon_bo_size(track->cb_color_frag_bo[i])) { in r600_cs_track_validate_cb()
484 track->cb_color_frag_offset[i], in r600_cs_track_validate_cb()
485 radeon_bo_size(track->cb_color_frag_bo[i])); in r600_cs_track_validate_cb()
492 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]); in r600_cs_track_validate_cb()
497 if (bytes + track->cb_color_tile_offset[i] > in r600_cs_track_validate_cb()
498 radeon_bo_size(track->cb_color_tile_bo[i])) { in r600_cs_track_validate_cb()
502 track->cb_color_tile_offset[i], in r600_cs_track_validate_cb()
503 radeon_bo_size(track->cb_color_tile_bo[i])); in r600_cs_track_validate_cb()
517 struct r600_cs_track *track = p->track; in r600_cs_track_validate_db() local
528 if (track->db_bo == NULL) { in r600_cs_track_validate_db()
532 switch (G_028010_FORMAT(track->db_depth_info)) { in r600_cs_track_validate_db()
547 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); in r600_cs_track_validate_db()
550 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { in r600_cs_track_validate_db()
551 if (!track->db_depth_size_idx) { in r600_cs_track_validate_db()
555 tmp = radeon_bo_size(track->db_bo) - track->db_offset; in r600_cs_track_validate_db()
559 track->db_depth_size, bpe, track->db_offset, in r600_cs_track_validate_db()
560 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
563 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); in r600_cs_track_validate_db()
566 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; in r600_cs_track_validate_db()
567 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; in r600_cs_track_validate_db()
572 base_offset = track->db_bo_mc + track->db_offset; in r600_cs_track_validate_db()
573 array_mode = G_028010_ARRAY_MODE(track->db_depth_info); in r600_cs_track_validate_db()
575 array_check.group_size = track->group_size; in r600_cs_track_validate_db()
576 array_check.nbanks = track->nbanks; in r600_cs_track_validate_db()
577 array_check.npipes = track->npipes; in r600_cs_track_validate_db()
578 array_check.nsamples = track->nsamples; in r600_cs_track_validate_db()
583 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
584 track->db_depth_info); in r600_cs_track_validate_db()
596 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
597 track->db_depth_info); in r600_cs_track_validate_db()
617 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; in r600_cs_track_validate_db()
618 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; in r600_cs_track_validate_db()
619 tmp = ntiles * bpe * 64 * nviews * track->nsamples; in r600_cs_track_validate_db()
620 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { in r600_cs_track_validate_db()
623 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, in r600_cs_track_validate_db()
624 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
630 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { in r600_cs_track_validate_db()
634 if (track->htile_bo == NULL) { in r600_cs_track_validate_db()
636 __func__, __LINE__, track->db_depth_info); in r600_cs_track_validate_db()
639 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { in r600_cs_track_validate_db()
641 __func__, __LINE__, track->db_depth_size); in r600_cs_track_validate_db()
647 if (G_028D24_LINEAR(track->htile_surface)) { in r600_cs_track_validate_db()
651 nby = round_up(nby, track->npipes * 8); in r600_cs_track_validate_db()
657 switch (track->npipes) { in r600_cs_track_validate_db()
680 __func__, __LINE__, track->npipes); in r600_cs_track_validate_db()
688 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in r600_cs_track_validate_db()
689 size += track->htile_offset; in r600_cs_track_validate_db()
691 if (size > radeon_bo_size(track->htile_bo)) { in r600_cs_track_validate_db()
693 __func__, __LINE__, radeon_bo_size(track->htile_bo), in r600_cs_track_validate_db()
699 track->db_dirty = false; in r600_cs_track_validate_db()
705 struct r600_cs_track *track = p->track; in r600_cs_track_check() local
714 if (track->streamout_dirty && track->vgt_strmout_en) { in r600_cs_track_check()
716 if (track->vgt_strmout_buffer_en & (1 << i)) { in r600_cs_track_check()
717 if (track->vgt_strmout_bo[i]) { in r600_cs_track_check()
718 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in r600_cs_track_check()
719 (u64)track->vgt_strmout_size[i]; in r600_cs_track_check()
720 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in r600_cs_track_check()
723 radeon_bo_size(track->vgt_strmout_bo[i])); in r600_cs_track_check()
732 track->streamout_dirty = false; in r600_cs_track_check()
735 if (track->sx_misc_kill_all_prims) in r600_cs_track_check()
741 if (track->cb_dirty) { in r600_cs_track_check()
742 tmp = track->cb_target_mask; in r600_cs_track_check()
745 if (track->is_resolve) { in r600_cs_track_check()
750 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); in r600_cs_track_check()
755 if (track->cb_color_bo[i] == NULL) { in r600_cs_track_check()
757 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in r600_cs_track_check()
766 track->cb_dirty = false; in r600_cs_track_check()
770 if (track->db_dirty && in r600_cs_track_check()
771 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && in r600_cs_track_check()
772 (G_028800_STENCIL_ENABLE(track->db_depth_control) || in r600_cs_track_check()
773 G_028800_Z_ENABLE(track->db_depth_control))) { in r600_cs_track_check()
968 struct r600_cs_track *track = (struct r600_cs_track *)p->track; in r600_cs_check_reg() local
1023 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1026 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1027 track->db_dirty = true; in r600_cs_check_reg()
1038 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1040 track->db_depth_info &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1043 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1046 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1049 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1051 track->db_dirty = true; in r600_cs_check_reg()
1054 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1055 track->db_dirty = true; in r600_cs_check_reg()
1058 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1059 track->db_depth_size_idx = idx; in r600_cs_check_reg()
1060 track->db_dirty = true; in r600_cs_check_reg()
1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1064 track->streamout_dirty = true; in r600_cs_check_reg()
1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1068 track->streamout_dirty = true; in r600_cs_check_reg()
1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1083 track->vgt_strmout_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1084 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1085 track->streamout_dirty = true; in r600_cs_check_reg()
1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1094 track->streamout_dirty = true; in r600_cs_check_reg()
1106 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1107 track->cb_dirty = true; in r600_cs_check_reg()
1110 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1114 track->log_nsamples = tmp; in r600_cs_check_reg()
1115 track->nsamples = 1 << tmp; in r600_cs_check_reg()
1116 track->cb_dirty = true; in r600_cs_check_reg()
1120 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX; in r600_cs_check_reg()
1121 track->cb_dirty = true; in r600_cs_check_reg()
1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1142 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1145 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1151 track->cb_dirty = true; in r600_cs_check_reg()
1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1163 track->cb_dirty = true; in r600_cs_check_reg()
1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1175 track->cb_color_size_idx[tmp] = idx; in r600_cs_check_reg()
1176 track->cb_dirty = true; in r600_cs_check_reg()
1197 if (!track->cb_color_base_last[tmp]) { in r600_cs_check_reg()
1201 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; in r600_cs_check_reg()
1202 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()
1203 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1210 track->cb_color_frag_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1211 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1214 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1215 track->cb_dirty = true; in r600_cs_check_reg()
1228 if (!track->cb_color_base_last[tmp]) { in r600_cs_check_reg()
1232 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; in r600_cs_check_reg()
1233 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; in r600_cs_check_reg()
1234 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1241 track->cb_color_tile_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1242 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1245 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1246 track->cb_dirty = true; in r600_cs_check_reg()
1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1259 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) { in r600_cs_check_reg()
1260 track->cb_dirty = true; in r600_cs_check_reg()
1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1280 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1281 track->cb_color_bo[tmp] = reloc->robj; in r600_cs_check_reg()
1282 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()
1283 track->cb_dirty = true; in r600_cs_check_reg()
1292 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1294 track->db_bo = reloc->robj; in r600_cs_check_reg()
1295 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()
1296 track->db_dirty = true; in r600_cs_check_reg()
1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1307 track->htile_bo = reloc->robj; in r600_cs_check_reg()
1308 track->db_dirty = true; in r600_cs_check_reg()
1311 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1314 track->db_dirty = true; in r600_cs_check_reg()
1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1476 struct r600_cs_track *track = p->track; in r600_check_texture_resource() local
1516 array_check.group_size = track->group_size; in r600_check_texture_resource()
1517 array_check.nbanks = track->nbanks; in r600_check_texture_resource()
1518 array_check.npipes = track->npipes; in r600_check_texture_resource()
1630 struct r600_cs_track *track; in r600_packet3_check() local
1638 track = (struct r600_cs_track *)p->track; in r600_packet3_check()
2024 if (track->sq_config & DX9_CONSTS) { in r600_packet3_check()
2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { in r600_packet3_check()
2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) { in r600_packet3_check()
2110 offset, track->vgt_strmout_bo_offset[idx_value]); in r600_packet3_check()
2271 struct r600_cs_track *track; in r600_cs_parse() local
2274 if (p->track == NULL) { in r600_cs_parse()
2276 track = kzalloc(sizeof(*track), GFP_KERNEL); in r600_cs_parse()
2277 if (track == NULL) in r600_cs_parse()
2279 r600_cs_track_init(track); in r600_cs_parse()
2281 track->npipes = p->rdev->config.r600.tiling_npipes; in r600_cs_parse()
2282 track->nbanks = p->rdev->config.r600.tiling_nbanks; in r600_cs_parse()
2283 track->group_size = p->rdev->config.r600.tiling_group_size; in r600_cs_parse()
2285 track->npipes = p->rdev->config.rv770.tiling_npipes; in r600_cs_parse()
2286 track->nbanks = p->rdev->config.rv770.tiling_nbanks; in r600_cs_parse()
2287 track->group_size = p->rdev->config.rv770.tiling_group_size; in r600_cs_parse()
2289 p->track = track; in r600_cs_parse()
2294 kfree(p->track); in r600_cs_parse()
2295 p->track = NULL; in r600_cs_parse()
2310 kfree(p->track); in r600_cs_parse()
2311 p->track = NULL; in r600_cs_parse()
2315 kfree(p->track); in r600_cs_parse()
2316 p->track = NULL; in r600_cs_parse()
2326 kfree(p->track); in r600_cs_parse()
2327 p->track = NULL; in r600_cs_parse()