41 	for (i = 0; i < rdev->usec_timeout; i++) {  in r520_mc_wait_for_idle()
45 			return 0;  in r520_mc_wait_for_idle()
58 	 * DST_PIPE_CONFIG		0x170C  in r520_gpu_init()
59 	 * GB_TILE_CONFIG		0x4018  in r520_gpu_init()
60 	 * GB_FIFO_SIZE			0x4024  in r520_gpu_init()
61 	 * GB_PIPE_SELECT		0x402C  in r520_gpu_init()
62 	 * GB_PIPE_SELECT2              0x4124  in r520_gpu_init()
63 	 *	Z_PIPE_SHIFT			0  in r520_gpu_init()
64 	 *	Z_PIPE_MASK			0x000000003  in r520_gpu_init()
65 	 * GB_FIFO_SIZE2                0x4128  in r520_gpu_init()
66 	 *	SC_SFIFO_SIZE_SHIFT		0  in r520_gpu_init()
67 	 *	SC_SFIFO_SIZE_MASK		0x000000003  in r520_gpu_init()
69 	 *	SC_MFIFO_SIZE_MASK		0x00000000C  in r520_gpu_init()
71 	 *	FG_SFIFO_SIZE_MASK		0x000000030  in r520_gpu_init()
73 	 *	ZB_MFIFO_SIZE_MASK		0x0000000C0  in r520_gpu_init()
74 	 * GA_ENHANCE			0x4274  in r520_gpu_init()
75 	 * SU_REG_DEST			0x42C8  in r520_gpu_init()
79 		WREG32(0x4128, 0xFF);  in r520_gpu_init()
86 	      (((gb_pipe_select >> 8) & 0xF) << 4);  in r520_gpu_init()
87 	WREG32_PLL(0x000D, tmp);  in r520_gpu_init()
101 	case 0:  in r520_vram_get_type()
126 	radeon_vram_location(rdev, &rdev->mc, 0);  in r520_mc_init()
127 	rdev->mc.gtt_base_align = 0;  in r520_mc_init()
159 		WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);  in r520_mc_program()
160 		WREG32_MC(R_000006_AGP_BASE, 0);  in r520_mc_program()
161 		WREG32_MC(R_000007_AGP_BASE_2, 0);  in r520_mc_program()
217 	return 0;  in r520_startup()
231 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r520_resume()
277 			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r520_init()
328 	return 0;  in r520_init()