Lines Matching refs:rdev
45 void r420_pm_init_profile(struct radeon_device *rdev) in r420_pm_init_profile() argument
48 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
51 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
56 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
61 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
66 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
71 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
76 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
78 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
79 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
80 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
81 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
84 static void r420_set_reg_safe(struct radeon_device *rdev) in r420_set_reg_safe() argument
86 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; in r420_set_reg_safe()
87 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); in r420_set_reg_safe()
90 void r420_pipes_init(struct radeon_device *rdev) in r420_pipes_init() argument
100 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
108 if ((rdev->pdev->device == 0x5e4c) || in r420_pipes_init()
109 (rdev->pdev->device == 0x5e4f)) in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
136 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
148 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
152 if (rdev->family == CHIP_RV530) { in r420_pipes_init()
155 rdev->num_z_pipes = 2; in r420_pipes_init()
157 rdev->num_z_pipes = 1; in r420_pipes_init()
159 rdev->num_z_pipes = 1; in r420_pipes_init()
162 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
165 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) in r420_mc_rreg() argument
170 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
173 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
177 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r420_mc_wreg() argument
181 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
185 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
188 static void r420_debugfs(struct radeon_device *rdev) in r420_debugfs() argument
190 r100_debugfs_rbbm_init(rdev); in r420_debugfs()
191 r420_debugfs_pipes_info_init(rdev); in r420_debugfs()
194 static void r420_clock_resume(struct radeon_device *rdev) in r420_clock_resume() argument
199 radeon_atom_set_clock_gating(rdev, 1); in r420_clock_resume()
202 if (rdev->family == CHIP_R420) in r420_clock_resume()
207 static void r420_cp_errata_init(struct radeon_device *rdev) in r420_cp_errata_init() argument
210 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
218 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
219 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_init()
222 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
224 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_init()
227 static void r420_cp_errata_fini(struct radeon_device *rdev) in r420_cp_errata_fini() argument
230 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
235 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_fini()
239 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_fini()
240 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
243 static int r420_startup(struct radeon_device *rdev) in r420_startup() argument
248 r100_set_common_regs(rdev); in r420_startup()
250 r300_mc_program(rdev); in r420_startup()
252 r420_clock_resume(rdev); in r420_startup()
255 if (rdev->flags & RADEON_IS_PCIE) { in r420_startup()
256 r = rv370_pcie_gart_enable(rdev); in r420_startup()
260 if (rdev->flags & RADEON_IS_PCI) { in r420_startup()
261 r = r100_pci_gart_enable(rdev); in r420_startup()
265 r420_pipes_init(rdev); in r420_startup()
268 r = radeon_wb_init(rdev); in r420_startup()
272 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
274 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r420_startup()
279 if (!rdev->irq.installed) { in r420_startup()
280 r = radeon_irq_kms_init(rdev); in r420_startup()
285 r100_irq_set(rdev); in r420_startup()
286 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
288 r = r100_cp_init(rdev, 1024 * 1024); in r420_startup()
290 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r420_startup()
293 r420_cp_errata_init(rdev); in r420_startup()
295 r = radeon_ib_pool_init(rdev); in r420_startup()
297 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r420_startup()
304 int r420_resume(struct radeon_device *rdev) in r420_resume() argument
309 if (rdev->flags & RADEON_IS_PCIE) in r420_resume()
310 rv370_pcie_gart_disable(rdev); in r420_resume()
311 if (rdev->flags & RADEON_IS_PCI) in r420_resume()
312 r100_pci_gart_disable(rdev); in r420_resume()
314 r420_clock_resume(rdev); in r420_resume()
316 if (radeon_asic_reset(rdev)) { in r420_resume()
317 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
322 if (rdev->is_atom_bios) { in r420_resume()
323 atom_asic_init(rdev->mode_info.atom_context); in r420_resume()
325 radeon_combios_asic_init(rdev_to_drm(rdev)); in r420_resume()
328 r420_clock_resume(rdev); in r420_resume()
330 radeon_surface_init(rdev); in r420_resume()
332 rdev->accel_working = true; in r420_resume()
333 r = r420_startup(rdev); in r420_resume()
335 rdev->accel_working = false; in r420_resume()
340 int r420_suspend(struct radeon_device *rdev) in r420_suspend() argument
342 radeon_pm_suspend(rdev); in r420_suspend()
343 r420_cp_errata_fini(rdev); in r420_suspend()
344 r100_cp_disable(rdev); in r420_suspend()
345 radeon_wb_disable(rdev); in r420_suspend()
346 r100_irq_disable(rdev); in r420_suspend()
347 if (rdev->flags & RADEON_IS_PCIE) in r420_suspend()
348 rv370_pcie_gart_disable(rdev); in r420_suspend()
349 if (rdev->flags & RADEON_IS_PCI) in r420_suspend()
350 r100_pci_gart_disable(rdev); in r420_suspend()
354 void r420_fini(struct radeon_device *rdev) in r420_fini() argument
356 radeon_pm_fini(rdev); in r420_fini()
357 r100_cp_fini(rdev); in r420_fini()
358 radeon_wb_fini(rdev); in r420_fini()
359 radeon_ib_pool_fini(rdev); in r420_fini()
360 radeon_gem_fini(rdev); in r420_fini()
361 if (rdev->flags & RADEON_IS_PCIE) in r420_fini()
362 rv370_pcie_gart_fini(rdev); in r420_fini()
363 if (rdev->flags & RADEON_IS_PCI) in r420_fini()
364 r100_pci_gart_fini(rdev); in r420_fini()
365 radeon_agp_fini(rdev); in r420_fini()
366 radeon_irq_kms_fini(rdev); in r420_fini()
367 radeon_fence_driver_fini(rdev); in r420_fini()
368 radeon_bo_fini(rdev); in r420_fini()
369 if (rdev->is_atom_bios) { in r420_fini()
370 radeon_atombios_fini(rdev); in r420_fini()
372 radeon_combios_fini(rdev); in r420_fini()
374 kfree(rdev->bios); in r420_fini()
375 rdev->bios = NULL; in r420_fini()
378 int r420_init(struct radeon_device *rdev) in r420_init() argument
383 radeon_scratch_init(rdev); in r420_init()
385 radeon_surface_init(rdev); in r420_init()
388 r100_restore_sanity(rdev); in r420_init()
390 if (!radeon_get_bios(rdev)) { in r420_init()
391 if (ASIC_IS_AVIVO(rdev)) in r420_init()
394 if (rdev->is_atom_bios) { in r420_init()
395 r = radeon_atombios_init(rdev); in r420_init()
400 r = radeon_combios_init(rdev); in r420_init()
406 if (radeon_asic_reset(rdev)) { in r420_init()
407 dev_warn(rdev->dev, in r420_init()
413 if (radeon_boot_test_post_card(rdev) == false) in r420_init()
417 radeon_get_clock_info(rdev_to_drm(rdev)); in r420_init()
419 if (rdev->flags & RADEON_IS_AGP) { in r420_init()
420 r = radeon_agp_init(rdev); in r420_init()
422 radeon_agp_disable(rdev); in r420_init()
426 r300_mc_init(rdev); in r420_init()
427 r420_debugfs(rdev); in r420_init()
429 radeon_fence_driver_init(rdev); in r420_init()
431 r = radeon_bo_init(rdev); in r420_init()
435 if (rdev->family == CHIP_R420) in r420_init()
436 r100_enable_bm(rdev); in r420_init()
438 if (rdev->flags & RADEON_IS_PCIE) { in r420_init()
439 r = rv370_pcie_gart_init(rdev); in r420_init()
443 if (rdev->flags & RADEON_IS_PCI) { in r420_init()
444 r = r100_pci_gart_init(rdev); in r420_init()
448 r420_set_reg_safe(rdev); in r420_init()
451 radeon_pm_init(rdev); in r420_init()
453 rdev->accel_working = true; in r420_init()
454 r = r420_startup(rdev); in r420_init()
457 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r420_init()
458 r100_cp_fini(rdev); in r420_init()
459 radeon_wb_fini(rdev); in r420_init()
460 radeon_ib_pool_fini(rdev); in r420_init()
461 radeon_irq_kms_fini(rdev); in r420_init()
462 if (rdev->flags & RADEON_IS_PCIE) in r420_init()
463 rv370_pcie_gart_fini(rdev); in r420_init()
464 if (rdev->flags & RADEON_IS_PCI) in r420_init()
465 r100_pci_gart_fini(rdev); in r420_init()
466 radeon_agp_fini(rdev); in r420_init()
467 rdev->accel_working = false; in r420_init()
478 struct radeon_device *rdev = m->private; in r420_debugfs_pipes_info_show() local
493 void r420_debugfs_pipes_info_init(struct radeon_device *rdev) in r420_debugfs_pipes_info_init() argument
496 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; in r420_debugfs_pipes_info_init()
498 debugfs_create_file("r420_pipes_info", 0444, root, rdev, in r420_debugfs_pipes_info_init()