Lines Matching +full:full +full:- +full:size
111 * r100_wait_for_vblank - vblank wait asic callback.
116 * Wait for vblank on the requested crtc (r1xx-r4xx).
122 if (crtc >= rdev->num_crtc) in r100_wait_for_vblank()
152 * r100_page_flip - pageflip callback.
159 * Does the actual pageflip (r1xx-r4xx).
166 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip()
168 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in r100_page_flip()
174 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
177 pitch_pixels = fb->pitches[0] / fb->format->cpp[0]; in r100_page_flip()
178 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8, in r100_page_flip()
179 fb->format->cpp[0] * 8 * 8); in r100_page_flip()
181 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in r100_page_flip()
184 for (i = 0; i < rdev->usec_timeout; i++) { in r100_page_flip()
185 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
191 /* Unlock the lock, so double-buffering can take place inside vblank */ in r100_page_flip()
193 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
198 * r100_page_flip_pending - check if page flip is still pending
203 * Check if the last pagefilp is still pending (r1xx-r4xx).
208 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending()
211 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
216 * r100_pm_get_dynpm_state - look up dynpm power state callback.
221 * current state of the GPU (r1xx-r5xx).
227 rdev->pm.dynpm_can_upclock = true; in r100_pm_get_dynpm_state()
228 rdev->pm.dynpm_can_downclock = true; in r100_pm_get_dynpm_state()
230 switch (rdev->pm.dynpm_planned_action) { in r100_pm_get_dynpm_state()
232 rdev->pm.requested_power_state_index = 0; in r100_pm_get_dynpm_state()
233 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
236 if (rdev->pm.current_power_state_index == 0) { in r100_pm_get_dynpm_state()
237 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
238 rdev->pm.dynpm_can_downclock = false; in r100_pm_get_dynpm_state()
240 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
241 for (i = 0; i < rdev->pm.num_power_states; i++) { in r100_pm_get_dynpm_state()
242 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
244 else if (i >= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
245 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
248 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
253 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
254 rdev->pm.current_power_state_index - 1; in r100_pm_get_dynpm_state()
257 if ((rdev->pm.active_crtc_count > 0) && in r100_pm_get_dynpm_state()
258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & in r100_pm_get_dynpm_state()
260 rdev->pm.requested_power_state_index++; in r100_pm_get_dynpm_state()
264 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r100_pm_get_dynpm_state()
265 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
266 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
268 if (rdev->pm.active_crtc_count > 1) { in r100_pm_get_dynpm_state()
269 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r100_pm_get_dynpm_state()
270 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r100_pm_get_dynpm_state()
272 else if (i <= rdev->pm.current_power_state_index) { in r100_pm_get_dynpm_state()
273 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r100_pm_get_dynpm_state()
276 rdev->pm.requested_power_state_index = i; in r100_pm_get_dynpm_state()
281 rdev->pm.requested_power_state_index = in r100_pm_get_dynpm_state()
282 rdev->pm.current_power_state_index + 1; in r100_pm_get_dynpm_state()
286 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r100_pm_get_dynpm_state()
287 rdev->pm.dynpm_can_upclock = false; in r100_pm_get_dynpm_state()
295 rdev->pm.requested_clock_mode_index = 0; in r100_pm_get_dynpm_state()
298 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
299 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r100_pm_get_dynpm_state()
300 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
301 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r100_pm_get_dynpm_state()
302 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
307 * r100_pm_init_profile - Initialize power profiles callback.
312 * (r1xx-r3xx).
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
321 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
326 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in r100_pm_init_profile()
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r100_pm_init_profile()
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r100_pm_init_profile()
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r100_pm_init_profile()
351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r100_pm_init_profile()
355 * r100_pm_misc - set additional pm hw parameters callback.
359 * Set non-clock parameters associated with a power state
360 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
364 int requested_index = rdev->pm.requested_power_state_index; in r100_pm_misc()
365 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in r100_pm_misc()
366 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in r100_pm_misc()
369 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in r100_pm_misc()
370 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in r100_pm_misc()
371 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
372 if (voltage->active_high) in r100_pm_misc()
373 tmp |= voltage->gpio.mask; in r100_pm_misc()
375 tmp &= ~(voltage->gpio.mask); in r100_pm_misc()
376 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
377 if (voltage->delay) in r100_pm_misc()
378 udelay(voltage->delay); in r100_pm_misc()
380 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
381 if (voltage->active_high) in r100_pm_misc()
382 tmp &= ~voltage->gpio.mask; in r100_pm_misc()
384 tmp |= voltage->gpio.mask; in r100_pm_misc()
385 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
386 if (voltage->delay) in r100_pm_misc()
387 udelay(voltage->delay); in r100_pm_misc()
396 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in r100_pm_misc()
398 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) in r100_pm_misc()
402 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) in r100_pm_misc()
404 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) in r100_pm_misc()
409 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in r100_pm_misc()
411 if (voltage->delay) { in r100_pm_misc()
413 switch (voltage->delay) { in r100_pm_misc()
432 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in r100_pm_misc()
442 if ((rdev->flags & RADEON_IS_PCIE) && in r100_pm_misc()
443 !(rdev->flags & RADEON_IS_IGP) && in r100_pm_misc()
444 rdev->asic->pm.set_pcie_lanes && in r100_pm_misc()
445 (ps->pcie_lanes != in r100_pm_misc()
446 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in r100_pm_misc()
448 ps->pcie_lanes); in r100_pm_misc()
449 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); in r100_pm_misc()
454 * r100_pm_prepare - pre-power state change callback.
458 * Prepare for a power state change (r1xx-r4xx).
468 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_prepare()
470 if (radeon_crtc->enabled) { in r100_pm_prepare()
471 if (radeon_crtc->crtc_id) { in r100_pm_prepare()
485 * r100_pm_finish - post-power state change callback.
489 * Clean up after a power state change (r1xx-r4xx).
499 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in r100_pm_finish()
501 if (radeon_crtc->enabled) { in r100_pm_finish()
502 if (radeon_crtc->crtc_id) { in r100_pm_finish()
516 * r100_gui_idle - gui idle callback.
520 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
533 * r100_hpd_sense - hpd sense callback.
538 * Checks if a digital monitor is connected (r1xx-r4xx).
561 * r100_hpd_set_polarity - hpd set polarity callback.
566 * Set the polarity of the hpd pin (r1xx-r4xx).
597 * r100_hpd_init - hpd setup callback.
601 * Setup the hpd pins used by the card (r1xx-r4xx).
610 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_init()
612 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_init()
613 enable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_init()
614 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r100_hpd_init()
620 * r100_hpd_fini - hpd tear down callback.
624 * Tear down the hpd pins used by the card (r1xx-r4xx).
633 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r100_hpd_fini()
635 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r100_hpd_fini()
636 disable |= 1 << radeon_connector->hpd.hpd; in r100_hpd_fini()
656 if (rdev->gart.ptr) { in r100_pci_gart_init()
664 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
665 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
666 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
667 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
679 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); in r100_pci_gart_enable()
680 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); in r100_pci_gart_enable()
681 /* set PCI GART page-table base address */ in r100_pci_gart_enable()
682 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
687 (unsigned)(rdev->mc.gtt_size >> 20), in r100_pci_gart_enable()
688 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
689 rdev->gart.ready = true; in r100_pci_gart_enable()
712 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
727 if (!rdev->irq.installed) { in r100_irq_set()
730 return -EINVAL; in r100_irq_set()
732 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r100_irq_set()
735 if (rdev->irq.crtc_vblank_int[0] || in r100_irq_set()
736 atomic_read(&rdev->irq.pflip[0])) { in r100_irq_set()
739 if (rdev->irq.crtc_vblank_int[1] || in r100_irq_set()
740 atomic_read(&rdev->irq.pflip[1])) { in r100_irq_set()
743 if (rdev->irq.hpd[0]) { in r100_irq_set()
746 if (rdev->irq.hpd[1]) { in r100_irq_set()
790 if (rdev->shutdown) { in r100_irq_process()
800 if (rdev->irq.crtc_vblank_int[0]) { in r100_irq_process()
802 rdev->pm.vblank_sync = true; in r100_irq_process()
803 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
805 if (atomic_read(&rdev->irq.pflip[0])) in r100_irq_process()
809 if (rdev->irq.crtc_vblank_int[1]) { in r100_irq_process()
811 rdev->pm.vblank_sync = true; in r100_irq_process()
812 wake_up(&rdev->irq.vblank_queue); in r100_irq_process()
814 if (atomic_read(&rdev->irq.pflip[1])) in r100_irq_process()
828 schedule_delayed_work(&rdev->hotplug_work, 0); in r100_irq_process()
829 if (rdev->msi_enabled) { in r100_irq_process()
830 switch (rdev->family) { in r100_irq_process()
854 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | in r100_ring_hdp_flush()
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); in r100_ring_hdp_flush()
872 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r100_fence_ring_emit()
885 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
886 radeon_ring_write(ring, fence->seq); in r100_fence_ring_emit()
907 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_copy_blit()
929 return ERR_PTR(-EINVAL); in r100_copy_blit()
936 num_gpu_pages -= cur_pages; in r100_copy_blit()
938 /* pages are in Y direction - height in r100_copy_blit()
939 page width in X direction - width */ in r100_copy_blit()
983 for (i = 0; i < rdev->usec_timeout; i++) { in r100_cp_wait_for_idle()
990 return -1; in r100_cp_wait_for_idle()
1019 switch (rdev->family) { in r100_cp_init_microcode()
1076 DRM_ERROR("Unsupported Radeon family %u\n", rdev->family); in r100_cp_init_microcode()
1077 return -EINVAL; in r100_cp_init_microcode()
1080 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r100_cp_init_microcode()
1083 } else if (rdev->me_fw->size % 8) { in r100_cp_init_microcode()
1085 rdev->me_fw->size, fw_name); in r100_cp_init_microcode()
1086 err = -EINVAL; in r100_cp_init_microcode()
1087 release_firmware(rdev->me_fw); in r100_cp_init_microcode()
1088 rdev->me_fw = NULL; in r100_cp_init_microcode()
1098 if (rdev->wb.enabled) in r100_gfx_get_rptr()
1099 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); in r100_gfx_get_rptr()
1115 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_gfx_set_wptr()
1122 int i, size; in r100_cp_load_microcode() local
1128 if (rdev->me_fw) { in r100_cp_load_microcode()
1129 size = rdev->me_fw->size / 4; in r100_cp_load_microcode()
1130 fw_data = (const __be32 *)&rdev->me_fw->data[0]; in r100_cp_load_microcode()
1132 for (i = 0; i < size; i += 2) { in r100_cp_load_microcode()
1143 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_cp_init()
1155 if (!rdev->me_fw) { in r100_cp_init()
1163 /* Align ring size */ in r100_cp_init()
1177 ring->align_mask = 16 - 1; in r100_cp_init()
1184 /* Setup the cp cache like this (cache size is 96 dwords) : in r100_cp_init()
1188 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1189 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1190 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) in r100_cp_init()
1207 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); in r100_cp_init()
1208 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); in r100_cp_init()
1212 ring->wptr = 0; in r100_cp_init()
1213 WREG32(RADEON_CP_RB_WPTR, ring->wptr); in r100_cp_init()
1217 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); in r100_cp_init()
1218 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); in r100_cp_init()
1220 if (rdev->wb.enabled) in r100_cp_init()
1238 pci_set_master(rdev->pdev); in r100_cp_init()
1240 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_init()
1246 ring->ready = true; in r100_cp_init()
1247 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r100_cp_init()
1249 if (!ring->rptr_save_reg /* not resuming from suspend */ in r100_cp_init()
1251 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r100_cp_init()
1254 ring->rptr_save_reg = 0; in r100_cp_init()
1267 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); in r100_cp_fini()
1268 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_fini()
1275 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r100_cp_disable()
1276 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_cp_disable()
1309 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1311 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_reloc_pitch_offset()
1312 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1314 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1318 return -EINVAL; in r100_reloc_pitch_offset()
1324 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; in r100_reloc_pitch_offset()
1326 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; in r100_reloc_pitch_offset()
1341 ib = p->ib.ptr; in r100_packet3_load_vbpntr()
1342 track = (struct r100_cs_track *)p->track; in r100_packet3_load_vbpntr()
1346 pkt->opcode); in r100_packet3_load_vbpntr()
1348 return -EINVAL; in r100_packet3_load_vbpntr()
1350 track->num_arrays = c; in r100_packet3_load_vbpntr()
1351 for (i = 0; i < (c - 1); i += 2, idx += 3) { in r100_packet3_load_vbpntr()
1355 pkt->opcode); in r100_packet3_load_vbpntr()
1360 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1362 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1363 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1364 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1368 pkt->opcode); in r100_packet3_load_vbpntr()
1372 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1373 track->arrays[i + 1].robj = reloc->robj; in r100_packet3_load_vbpntr()
1374 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1375 track->arrays[i + 1].esize &= 0x7F; in r100_packet3_load_vbpntr()
1381 pkt->opcode); in r100_packet3_load_vbpntr()
1386 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1387 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1388 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1389 track->arrays[i + 0].esize &= 0x7F; in r100_packet3_load_vbpntr()
1404 idx = pkt->idx + 1; in r100_cs_parse_packet0()
1405 reg = pkt->reg; in r100_cs_parse_packet0()
1410 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1412 return -EINVAL; in r100_cs_parse_packet0()
1415 if (((reg + (pkt->count << 2)) >> 7) > n) { in r100_cs_parse_packet0()
1416 return -EINVAL; in r100_cs_parse_packet0()
1419 for (i = 0; i <= pkt->count; i++, idx++) { in r100_cs_parse_packet0()
1428 if (pkt->one_reg_wr) { in r100_cs_parse_packet0()
1440 * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1444 * PACKET0 - VLINE_START_END + value
1445 * PACKET0 - WAIT_UNTIL +_value
1446 * RELOC (P3) - crtc_id in reloc.
1463 ib = p->ib.ptr; in r100_cs_packet_parse_vline()
1466 r = radeon_cs_packet_parse(p, &waitreloc, p->idx); in r100_cs_packet_parse_vline()
1474 return -EINVAL; in r100_cs_packet_parse_vline()
1479 return -EINVAL; in r100_cs_packet_parse_vline()
1483 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); in r100_cs_packet_parse_vline()
1487 h_idx = p->idx - 2; in r100_cs_packet_parse_vline()
1488 p->idx += waitreloc.count + 2; in r100_cs_packet_parse_vline()
1489 p->idx += p3reloc.count + 2; in r100_cs_packet_parse_vline()
1494 crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id); in r100_cs_packet_parse_vline()
1497 return -ENOENT; in r100_cs_packet_parse_vline()
1500 crtc_id = radeon_crtc->crtc_id; in r100_cs_packet_parse_vline()
1502 if (!crtc->enabled) { in r100_cs_packet_parse_vline()
1503 /* if the CRTC isn't enabled - we need to nop out the wait until */ in r100_cs_packet_parse_vline()
1518 return -EINVAL; in r100_cs_packet_parse_vline()
1593 ib = p->ib.ptr; in r100_packet0_check()
1594 track = (struct r100_cs_track *)p->track; in r100_packet0_check()
1624 track->zb.robj = reloc->robj; in r100_packet0_check()
1625 track->zb.offset = idx_value; in r100_packet0_check()
1626 track->zb_dirty = true; in r100_packet0_check()
1627 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1637 track->cb[0].robj = reloc->robj; in r100_packet0_check()
1638 track->cb[0].offset = idx_value; in r100_packet0_check()
1639 track->cb_dirty = true; in r100_packet0_check()
1640 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1645 i = (reg - RADEON_PP_TXOFFSET_0) / 24; in r100_packet0_check()
1653 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1654 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1656 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1661 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1663 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1664 track->textures[i].robj = reloc->robj; in r100_packet0_check()
1665 track->tex_dirty = true; in r100_packet0_check()
1672 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; in r100_packet0_check()
1680 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1681 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1682 track->textures[0].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1683 track->tex_dirty = true; in r100_packet0_check()
1690 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; in r100_packet0_check()
1698 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1699 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1700 track->textures[1].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1701 track->tex_dirty = true; in r100_packet0_check()
1708 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; in r100_packet0_check()
1716 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1717 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1718 track->textures[2].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1719 track->tex_dirty = true; in r100_packet0_check()
1722 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1723 track->cb_dirty = true; in r100_packet0_check()
1724 track->zb_dirty = true; in r100_packet0_check()
1734 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in r100_packet0_check()
1735 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1737 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1746 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1747 track->cb_dirty = true; in r100_packet0_check()
1750 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1751 track->zb_dirty = true; in r100_packet0_check()
1760 track->cb[0].cpp = 1; in r100_packet0_check()
1765 track->cb[0].cpp = 2; in r100_packet0_check()
1768 track->cb[0].cpp = 4; in r100_packet0_check()
1773 return -EINVAL; in r100_packet0_check()
1775 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1776 track->cb_dirty = true; in r100_packet0_check()
1777 track->zb_dirty = true; in r100_packet0_check()
1782 track->zb.cpp = 2; in r100_packet0_check()
1790 track->zb.cpp = 4; in r100_packet0_check()
1795 track->zb_dirty = true; in r100_packet0_check()
1805 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1810 for (i = 0; i < track->num_texture; i++) in r100_packet0_check()
1811 track->textures[i].enabled = !!(temp & (1 << i)); in r100_packet0_check()
1812 track->tex_dirty = true; in r100_packet0_check()
1816 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1819 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1824 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; in r100_packet0_check()
1825 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1826 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1827 track->tex_dirty = true; in r100_packet0_check()
1832 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; in r100_packet0_check()
1833 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1834 track->tex_dirty = true; in r100_packet0_check()
1839 i = (reg - RADEON_PP_TXFILTER_0) / 24; in r100_packet0_check()
1840 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1844 track->textures[i].roundup_w = false; in r100_packet0_check()
1847 track->textures[i].roundup_h = false; in r100_packet0_check()
1848 track->tex_dirty = true; in r100_packet0_check()
1853 i = (reg - RADEON_PP_TXFORMAT_0) / 24; in r100_packet0_check()
1855 track->textures[i].use_pitch = true; in r100_packet0_check()
1857 track->textures[i].use_pitch = false; in r100_packet0_check()
1858 …track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH… in r100_packet0_check()
1859 …track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEI… in r100_packet0_check()
1862 track->textures[i].tex_coord_type = 2; in r100_packet0_check()
1867 track->textures[i].cpp = 1; in r100_packet0_check()
1868 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1879 track->textures[i].cpp = 2; in r100_packet0_check()
1880 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1886 track->textures[i].cpp = 4; in r100_packet0_check()
1887 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_packet0_check()
1890 track->textures[i].cpp = 1; in r100_packet0_check()
1891 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; in r100_packet0_check()
1895 track->textures[i].cpp = 1; in r100_packet0_check()
1896 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; in r100_packet0_check()
1899 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1900 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1901 track->tex_dirty = true; in r100_packet0_check()
1907 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; in r100_packet0_check()
1909 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); in r100_packet0_check()
1910 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); in r100_packet0_check()
1912 track->tex_dirty = true; in r100_packet0_check()
1916 return -EINVAL; in r100_packet0_check()
1927 idx = pkt->idx + 1; in r100_cs_track_check_pkt3_indx_buffer()
1934 return -EINVAL; in r100_cs_track_check_pkt3_indx_buffer()
1948 ib = p->ib.ptr; in r100_packet3_check()
1949 idx = pkt->idx + 1; in r100_packet3_check()
1950 track = (struct r100_cs_track *)p->track; in r100_packet3_check()
1951 switch (pkt->opcode) { in r100_packet3_check()
1960 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1964 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1965 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); in r100_packet3_check()
1974 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); in r100_packet3_check()
1978 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1979 track->num_arrays = 1; in r100_packet3_check()
1980 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); in r100_packet3_check()
1982 track->arrays[0].robj = reloc->robj; in r100_packet3_check()
1983 track->arrays[0].esize = track->vtx_size; in r100_packet3_check()
1985 track->max_indx = radeon_get_ib_value(p, idx+1); in r100_packet3_check()
1987 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); in r100_packet3_check()
1988 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
1989 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
1996 return -EINVAL; in r100_packet3_check()
1998 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); in r100_packet3_check()
1999 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2000 track->immd_dwords = pkt->count - 1; in r100_packet3_check()
2001 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2005 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
2009 return -EINVAL; in r100_packet3_check()
2011 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
2012 track->immd_dwords = pkt->count; in r100_packet3_check()
2013 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2017 /* triggers drawing using in-packet vertex data */ in r100_packet3_check()
2019 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
2020 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2026 track->vap_vf_cntl = radeon_get_ib_value(p, idx); in r100_packet3_check()
2027 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2033 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2034 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2040 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); in r100_packet3_check()
2041 r = r100_cs_track_check(p->rdev, track); in r100_packet3_check()
2048 if (p->rdev->hyperz_filp != p->filp) in r100_packet3_check()
2049 return -EINVAL; in r100_packet3_check()
2054 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); in r100_packet3_check()
2055 return -EINVAL; in r100_packet3_check()
2068 return -ENOMEM; in r100_cs_parse()
2069 r100_cs_track_clear(p->rdev, track); in r100_cs_parse()
2070 p->track = track; in r100_cs_parse()
2072 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r100_cs_parse()
2076 p->idx += pkt.count + 2; in r100_cs_parse()
2079 if (p->rdev->family >= CHIP_R200) in r100_cs_parse()
2081 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2082 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2086 p->rdev->config.r100.reg_safe_bm, in r100_cs_parse()
2087 p->rdev->config.r100.reg_safe_bm_size, in r100_cs_parse()
2098 return -EINVAL; in r100_cs_parse()
2102 } while (p->idx < p->chunk_ib->length_dw); in r100_cs_parse()
2108 DRM_ERROR("pitch %d\n", t->pitch); in r100_cs_track_texture_print()
2109 DRM_ERROR("use_pitch %d\n", t->use_pitch); in r100_cs_track_texture_print()
2110 DRM_ERROR("width %d\n", t->width); in r100_cs_track_texture_print()
2111 DRM_ERROR("width_11 %d\n", t->width_11); in r100_cs_track_texture_print()
2112 DRM_ERROR("height %d\n", t->height); in r100_cs_track_texture_print()
2113 DRM_ERROR("height_11 %d\n", t->height_11); in r100_cs_track_texture_print()
2114 DRM_ERROR("num levels %d\n", t->num_levels); in r100_cs_track_texture_print()
2115 DRM_ERROR("depth %d\n", t->txdepth); in r100_cs_track_texture_print()
2116 DRM_ERROR("bpp %d\n", t->cpp); in r100_cs_track_texture_print()
2117 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); in r100_cs_track_texture_print()
2118 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); in r100_cs_track_texture_print()
2119 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); in r100_cs_track_texture_print()
2120 DRM_ERROR("compress format %d\n", t->compress_format); in r100_cs_track_texture_print()
2145 hblocks = (h + block_height - 1) / block_height; in r100_track_compress_size()
2146 wblocks = (w + block_width - 1) / block_width; in r100_track_compress_size()
2158 unsigned long size; in r100_cs_track_cube() local
2159 unsigned compress_format = track->textures[idx].compress_format; in r100_cs_track_cube()
2162 cube_robj = track->textures[idx].cube_info[face].robj; in r100_cs_track_cube()
2163 w = track->textures[idx].cube_info[face].width; in r100_cs_track_cube()
2164 h = track->textures[idx].cube_info[face].height; in r100_cs_track_cube()
2167 size = r100_track_compress_size(compress_format, w, h); in r100_cs_track_cube()
2169 size = w * h; in r100_cs_track_cube()
2170 size *= track->textures[idx].cpp; in r100_cs_track_cube()
2172 size += track->textures[idx].cube_info[face].offset; in r100_cs_track_cube()
2174 if (size > radeon_bo_size(cube_robj)) { in r100_cs_track_cube()
2175 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", in r100_cs_track_cube()
2176 size, radeon_bo_size(cube_robj)); in r100_cs_track_cube()
2177 r100_cs_track_texture_print(&track->textures[idx]); in r100_cs_track_cube()
2178 return -1; in r100_cs_track_cube()
2188 unsigned long size; in r100_cs_track_texture_check() local
2192 for (u = 0; u < track->num_texture; u++) { in r100_cs_track_texture_check()
2193 if (!track->textures[u].enabled) in r100_cs_track_texture_check()
2195 if (track->textures[u].lookup_disable) in r100_cs_track_texture_check()
2197 robj = track->textures[u].robj; in r100_cs_track_texture_check()
2200 return -EINVAL; in r100_cs_track_texture_check()
2202 size = 0; in r100_cs_track_texture_check()
2203 for (i = 0; i <= track->textures[u].num_levels; i++) { in r100_cs_track_texture_check()
2204 if (track->textures[u].use_pitch) { in r100_cs_track_texture_check()
2205 if (rdev->family < CHIP_R300) in r100_cs_track_texture_check()
2206 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); in r100_cs_track_texture_check()
2208 w = track->textures[u].pitch / (1 << i); in r100_cs_track_texture_check()
2210 w = track->textures[u].width; in r100_cs_track_texture_check()
2211 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2212 w |= track->textures[u].width_11; in r100_cs_track_texture_check()
2214 if (track->textures[u].roundup_w) in r100_cs_track_texture_check()
2217 h = track->textures[u].height; in r100_cs_track_texture_check()
2218 if (rdev->family >= CHIP_RV515) in r100_cs_track_texture_check()
2219 h |= track->textures[u].height_11; in r100_cs_track_texture_check()
2221 if (track->textures[u].roundup_h) in r100_cs_track_texture_check()
2223 if (track->textures[u].tex_coord_type == 1) { in r100_cs_track_texture_check()
2224 d = (1 << track->textures[u].txdepth) / (1 << i); in r100_cs_track_texture_check()
2230 if (track->textures[u].compress_format) { in r100_cs_track_texture_check()
2232 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; in r100_cs_track_texture_check()
2235 size += w * h * d; in r100_cs_track_texture_check()
2237 size *= track->textures[u].cpp; in r100_cs_track_texture_check()
2239 switch (track->textures[u].tex_coord_type) { in r100_cs_track_texture_check()
2244 if (track->separate_cube) { in r100_cs_track_texture_check()
2249 size *= 6; in r100_cs_track_texture_check()
2253 "%u\n", track->textures[u].tex_coord_type, u); in r100_cs_track_texture_check()
2254 return -EINVAL; in r100_cs_track_texture_check()
2256 if (size > radeon_bo_size(robj)) { in r100_cs_track_texture_check()
2258 "%lu\n", u, size, radeon_bo_size(robj)); in r100_cs_track_texture_check()
2259 r100_cs_track_texture_print(&track->textures[u]); in r100_cs_track_texture_check()
2260 return -EINVAL; in r100_cs_track_texture_check()
2269 unsigned long size; in r100_cs_track_check() local
2272 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; in r100_cs_track_check()
2274 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && in r100_cs_track_check()
2275 !track->blend_read_enable) in r100_cs_track_check()
2279 if (track->cb[i].robj == NULL) { in r100_cs_track_check()
2281 return -EINVAL; in r100_cs_track_check()
2283 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; in r100_cs_track_check()
2284 size += track->cb[i].offset; in r100_cs_track_check()
2285 if (size > radeon_bo_size(track->cb[i].robj)) { in r100_cs_track_check()
2287 "(need %lu have %lu) !\n", i, size, in r100_cs_track_check()
2288 radeon_bo_size(track->cb[i].robj)); in r100_cs_track_check()
2290 i, track->cb[i].pitch, track->cb[i].cpp, in r100_cs_track_check()
2291 track->cb[i].offset, track->maxy); in r100_cs_track_check()
2292 return -EINVAL; in r100_cs_track_check()
2295 track->cb_dirty = false; in r100_cs_track_check()
2297 if (track->zb_dirty && track->z_enabled) { in r100_cs_track_check()
2298 if (track->zb.robj == NULL) { in r100_cs_track_check()
2300 return -EINVAL; in r100_cs_track_check()
2302 size = track->zb.pitch * track->zb.cpp * track->maxy; in r100_cs_track_check()
2303 size += track->zb.offset; in r100_cs_track_check()
2304 if (size > radeon_bo_size(track->zb.robj)) { in r100_cs_track_check()
2306 "(need %lu have %lu) !\n", size, in r100_cs_track_check()
2307 radeon_bo_size(track->zb.robj)); in r100_cs_track_check()
2309 track->zb.pitch, track->zb.cpp, in r100_cs_track_check()
2310 track->zb.offset, track->maxy); in r100_cs_track_check()
2311 return -EINVAL; in r100_cs_track_check()
2314 track->zb_dirty = false; in r100_cs_track_check()
2316 if (track->aa_dirty && track->aaresolve) { in r100_cs_track_check()
2317 if (track->aa.robj == NULL) { in r100_cs_track_check()
2319 return -EINVAL; in r100_cs_track_check()
2322 size = track->aa.pitch * track->cb[0].cpp * track->maxy; in r100_cs_track_check()
2323 size += track->aa.offset; in r100_cs_track_check()
2324 if (size > radeon_bo_size(track->aa.robj)) { in r100_cs_track_check()
2326 "(need %lu have %lu) !\n", i, size, in r100_cs_track_check()
2327 radeon_bo_size(track->aa.robj)); in r100_cs_track_check()
2329 i, track->aa.pitch, track->cb[0].cpp, in r100_cs_track_check()
2330 track->aa.offset, track->maxy); in r100_cs_track_check()
2331 return -EINVAL; in r100_cs_track_check()
2334 track->aa_dirty = false; in r100_cs_track_check()
2336 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; in r100_cs_track_check()
2337 if (track->vap_vf_cntl & (1 << 14)) { in r100_cs_track_check()
2338 nverts = track->vap_alt_nverts; in r100_cs_track_check()
2340 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; in r100_cs_track_check()
2344 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2345 size = track->arrays[i].esize * track->max_indx * 4UL; in r100_cs_track_check()
2346 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2349 return -EINVAL; in r100_cs_track_check()
2351 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2352 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2354 prim_walk, i, size >> 2, in r100_cs_track_check()
2355 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2357 DRM_ERROR("Max indices %u\n", track->max_indx); in r100_cs_track_check()
2358 return -EINVAL; in r100_cs_track_check()
2363 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_check()
2364 size = track->arrays[i].esize * (nverts - 1) * 4UL; in r100_cs_track_check()
2365 if (track->arrays[i].robj == NULL) { in r100_cs_track_check()
2368 return -EINVAL; in r100_cs_track_check()
2370 if (size > radeon_bo_size(track->arrays[i].robj)) { in r100_cs_track_check()
2371 dev_err(rdev->dev, "(PW %u) Vertex array %u " in r100_cs_track_check()
2373 prim_walk, i, size >> 2, in r100_cs_track_check()
2374 radeon_bo_size(track->arrays[i].robj) in r100_cs_track_check()
2376 return -EINVAL; in r100_cs_track_check()
2381 size = track->vtx_size * nverts; in r100_cs_track_check()
2382 if (size != track->immd_dwords) { in r100_cs_track_check()
2384 track->immd_dwords, size); in r100_cs_track_check()
2386 nverts, track->vtx_size); in r100_cs_track_check()
2387 return -EINVAL; in r100_cs_track_check()
2393 return -EINVAL; in r100_cs_track_check()
2396 if (track->tex_dirty) { in r100_cs_track_check()
2397 track->tex_dirty = false; in r100_cs_track_check()
2407 track->cb_dirty = true; in r100_cs_track_clear()
2408 track->zb_dirty = true; in r100_cs_track_clear()
2409 track->tex_dirty = true; in r100_cs_track_clear()
2410 track->aa_dirty = true; in r100_cs_track_clear()
2412 if (rdev->family < CHIP_R300) { in r100_cs_track_clear()
2413 track->num_cb = 1; in r100_cs_track_clear()
2414 if (rdev->family <= CHIP_RS200) in r100_cs_track_clear()
2415 track->num_texture = 3; in r100_cs_track_clear()
2417 track->num_texture = 6; in r100_cs_track_clear()
2418 track->maxy = 2048; in r100_cs_track_clear()
2419 track->separate_cube = true; in r100_cs_track_clear()
2421 track->num_cb = 4; in r100_cs_track_clear()
2422 track->num_texture = 16; in r100_cs_track_clear()
2423 track->maxy = 4096; in r100_cs_track_clear()
2424 track->separate_cube = false; in r100_cs_track_clear()
2425 track->aaresolve = false; in r100_cs_track_clear()
2426 track->aa.robj = NULL; in r100_cs_track_clear()
2429 for (i = 0; i < track->num_cb; i++) { in r100_cs_track_clear()
2430 track->cb[i].robj = NULL; in r100_cs_track_clear()
2431 track->cb[i].pitch = 8192; in r100_cs_track_clear()
2432 track->cb[i].cpp = 16; in r100_cs_track_clear()
2433 track->cb[i].offset = 0; in r100_cs_track_clear()
2435 track->z_enabled = true; in r100_cs_track_clear()
2436 track->zb.robj = NULL; in r100_cs_track_clear()
2437 track->zb.pitch = 8192; in r100_cs_track_clear()
2438 track->zb.cpp = 4; in r100_cs_track_clear()
2439 track->zb.offset = 0; in r100_cs_track_clear()
2440 track->vtx_size = 0x7F; in r100_cs_track_clear()
2441 track->immd_dwords = 0xFFFFFFFFUL; in r100_cs_track_clear()
2442 track->num_arrays = 11; in r100_cs_track_clear()
2443 track->max_indx = 0x00FFFFFFUL; in r100_cs_track_clear()
2444 for (i = 0; i < track->num_arrays; i++) { in r100_cs_track_clear()
2445 track->arrays[i].robj = NULL; in r100_cs_track_clear()
2446 track->arrays[i].esize = 0x7F; in r100_cs_track_clear()
2448 for (i = 0; i < track->num_texture; i++) { in r100_cs_track_clear()
2449 track->textures[i].compress_format = R100_TRACK_COMP_NONE; in r100_cs_track_clear()
2450 track->textures[i].pitch = 16536; in r100_cs_track_clear()
2451 track->textures[i].width = 16536; in r100_cs_track_clear()
2452 track->textures[i].height = 16536; in r100_cs_track_clear()
2453 track->textures[i].width_11 = 1 << 11; in r100_cs_track_clear()
2454 track->textures[i].height_11 = 1 << 11; in r100_cs_track_clear()
2455 track->textures[i].num_levels = 12; in r100_cs_track_clear()
2456 if (rdev->family <= CHIP_RS200) { in r100_cs_track_clear()
2457 track->textures[i].tex_coord_type = 0; in r100_cs_track_clear()
2458 track->textures[i].txdepth = 0; in r100_cs_track_clear()
2460 track->textures[i].txdepth = 16; in r100_cs_track_clear()
2461 track->textures[i].tex_coord_type = 1; in r100_cs_track_clear()
2463 track->textures[i].cpp = 64; in r100_cs_track_clear()
2464 track->textures[i].robj = NULL; in r100_cs_track_clear()
2466 track->textures[i].enabled = false; in r100_cs_track_clear()
2467 track->textures[i].lookup_disable = false; in r100_cs_track_clear()
2468 track->textures[i].roundup_w = true; in r100_cs_track_clear()
2469 track->textures[i].roundup_h = true; in r100_cs_track_clear()
2470 if (track->separate_cube) in r100_cs_track_clear()
2472 track->textures[i].cube_info[face].robj = NULL; in r100_cs_track_clear()
2473 track->textures[i].cube_info[face].width = 16536; in r100_cs_track_clear()
2474 track->textures[i].cube_info[face].height = 16536; in r100_cs_track_clear()
2475 track->textures[i].cube_info[face].offset = 0; in r100_cs_track_clear()
2485 rdev->pll_errata = 0; in r100_errata()
2487 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { in r100_errata()
2488 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; in r100_errata()
2491 if (rdev->family == CHIP_RV100 || in r100_errata()
2492 rdev->family == CHIP_RS100 || in r100_errata()
2493 rdev->family == CHIP_RS200) { in r100_errata()
2494 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; in r100_errata()
2503 for (i = 0; i < rdev->usec_timeout; i++) { in r100_rbbm_fifo_wait_for_entry()
2510 return -1; in r100_rbbm_fifo_wait_for_entry()
2521 for (i = 0; i < rdev->usec_timeout; i++) { in r100_gui_wait_for_idle()
2528 return -1; in r100_gui_wait_for_idle()
2536 for (i = 0; i < rdev->usec_timeout; i++) { in r100_mc_wait_for_idle()
2544 return -1; in r100_mc_wait_for_idle()
2581 pci_clear_master(rdev->pdev); in r100_bm_disable()
2597 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2606 pci_save_state(rdev->pdev); in r100_asic_reset()
2618 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2626 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in r100_asic_reset()
2628 pci_restore_state(rdev->pdev); in r100_asic_reset()
2633 dev_err(rdev->dev, "failed to reset GPU\n"); in r100_asic_reset()
2634 ret = -1; in r100_asic_reset()
2636 dev_info(rdev->dev, "GPU reset succeed\n"); in r100_asic_reset()
2660 switch (rdev->pdev->device) { in r100_set_common_regs()
2670 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) && in r100_set_common_regs()
2671 ((rdev->pdev->subsystem_device == 0x016c) || in r100_set_common_regs()
2672 (rdev->pdev->subsystem_device == 0x016d) || in r100_set_common_regs()
2673 (rdev->pdev->subsystem_device == 0x016e) || in r100_set_common_regs()
2674 (rdev->pdev->subsystem_device == 0x016f) || in r100_set_common_regs()
2675 (rdev->pdev->subsystem_device == 0x0170) || in r100_set_common_regs()
2676 (rdev->pdev->subsystem_device == 0x017d) || in r100_set_common_regs()
2677 (rdev->pdev->subsystem_device == 0x017e) || in r100_set_common_regs()
2678 (rdev->pdev->subsystem_device == 0x0183) || in r100_set_common_regs()
2679 (rdev->pdev->subsystem_device == 0x018a) || in r100_set_common_regs()
2680 (rdev->pdev->subsystem_device == 0x019a))) in r100_set_common_regs()
2731 rdev->mc.vram_is_ddr = false; in r100_vram_get_type()
2732 if (rdev->flags & RADEON_IS_IGP) in r100_vram_get_type()
2733 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2735 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2736 if ((rdev->family == CHIP_RV100) || in r100_vram_get_type()
2737 (rdev->family == CHIP_RS100) || in r100_vram_get_type()
2738 (rdev->family == CHIP_RS200)) { in r100_vram_get_type()
2741 rdev->mc.vram_width = 32; in r100_vram_get_type()
2743 rdev->mc.vram_width = 64; in r100_vram_get_type()
2745 if (rdev->flags & RADEON_SINGLE_CRTC) { in r100_vram_get_type()
2746 rdev->mc.vram_width /= 4; in r100_vram_get_type()
2747 rdev->mc.vram_is_ddr = true; in r100_vram_get_type()
2749 } else if (rdev->family <= CHIP_RV280) { in r100_vram_get_type()
2752 rdev->mc.vram_width = 128; in r100_vram_get_type()
2754 rdev->mc.vram_width = 64; in r100_vram_get_type()
2758 rdev->mc.vram_width = 128; in r100_vram_get_type()
2772 if (rdev->family == CHIP_RV280 || in r100_get_accessible_vram()
2773 rdev->family >= CHIP_RV350) { in r100_get_accessible_vram()
2782 * header type... Limit those to one aperture size in r100_get_accessible_vram()
2784 pci_read_config_byte(rdev->pdev, 0xe, &byte); in r100_get_accessible_vram()
2805 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r100_vram_init_sizes()
2806 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r100_vram_init_sizes()
2807 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); in r100_vram_init_sizes()
2809 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) in r100_vram_init_sizes()
2810 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2812 if (rdev->flags & RADEON_IS_IGP) { in r100_vram_init_sizes()
2816 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); in r100_vram_init_sizes()
2817 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2818 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2820 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2824 if (rdev->mc.real_vram_size == 0) { in r100_vram_init_sizes()
2825 rdev->mc.real_vram_size = 8192 * 1024; in r100_vram_init_sizes()
2826 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r100_vram_init_sizes()
2828 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - in r100_vram_init_sizes()
2831 if (rdev->mc.aper_size > config_aper_size) in r100_vram_init_sizes()
2832 config_aper_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2834 if (config_aper_size > rdev->mc.real_vram_size) in r100_vram_init_sizes()
2835 rdev->mc.mc_vram_size = config_aper_size; in r100_vram_init_sizes()
2837 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2861 base = rdev->mc.aper_base; in r100_mc_init()
2862 if (rdev->flags & RADEON_IS_IGP) in r100_mc_init()
2864 radeon_vram_location(rdev, &rdev->mc, base); in r100_mc_init()
2865 rdev->mc.gtt_base_align = 0; in r100_mc_init()
2866 if (!(rdev->flags & RADEON_IS_AGP)) in r100_mc_init()
2867 radeon_gtt_location(rdev, &rdev->mc); in r100_mc_init()
2877 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { in r100_pll_errata_after_index()
2888 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { in r100_pll_errata_after_data()
2897 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { in r100_pll_errata_after_data()
2913 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2918 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_rreg()
2926 spin_lock_irqsave(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2931 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags); in r100_pll_wreg()
2937 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; in r100_set_safe_registers()
2938 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); in r100_set_safe_registers()
2939 } else if (rdev->family < CHIP_R200) { in r100_set_safe_registers()
2940 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; in r100_set_safe_registers()
2941 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); in r100_set_safe_registers()
2953 struct radeon_device *rdev = m->private; in r100_debugfs_rbbm_info_show()
2962 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info_show()
2972 struct radeon_device *rdev = m->private; in r100_debugfs_cp_ring_info_show()
2973 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_debugfs_cp_ring_info_show()
2980 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; in r100_debugfs_cp_ring_info_show()
2984 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); in r100_debugfs_cp_ring_info_show()
2986 if (ring->ready) { in r100_debugfs_cp_ring_info_show()
2988 i = (rdp + j) & ring->ptr_mask; in r100_debugfs_cp_ring_info_show()
2989 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); in r100_debugfs_cp_ring_info_show()
2998 struct radeon_device *rdev = m->private; in r100_debugfs_cp_csq_fifo_show()
3046 struct radeon_device *rdev = m->private; in r100_debugfs_mc_info_show()
3082 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; in r100_debugfs_rbbm_init()
3092 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; in r100_debugfs_cp_init()
3104 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; in r100_debugfs_mc_info_init()
3118 if (rdev->family <= CHIP_RS200) { in r100_set_surface_reg()
3128 } else if (rdev->family <= CHIP_RV280) { in r100_set_surface_reg()
3146 if (rdev->family < CHIP_R300) in r100_set_surface_reg()
3152 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); in r100_set_surface_reg()
3155 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); in r100_set_surface_reg()
3237 /* Guess line buffer size to be 8192 pixels */ in r100_bandwidth_update()
3240 if (!rdev->mode_info.mode_config_initialized) in r100_bandwidth_update()
3245 if (rdev->mode_info.crtcs[0]->base.enabled) { in r100_bandwidth_update()
3247 rdev->mode_info.crtcs[0]->base.primary->fb; in r100_bandwidth_update()
3249 mode1 = &rdev->mode_info.crtcs[0]->base.mode; in r100_bandwidth_update()
3250 pixel_bytes1 = fb->format->cpp[0]; in r100_bandwidth_update()
3252 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_bandwidth_update()
3253 if (rdev->mode_info.crtcs[1]->base.enabled) { in r100_bandwidth_update()
3255 rdev->mode_info.crtcs[1]->base.primary->fb; in r100_bandwidth_update()
3257 mode2 = &rdev->mode_info.crtcs[1]->base.mode; in r100_bandwidth_update()
3258 pixel_bytes2 = fb->format->cpp[0]; in r100_bandwidth_update()
3262 min_mem_eff.full = dfixed_const_8(0); in r100_bandwidth_update()
3264 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { in r100_bandwidth_update()
3279 sclk_ff = rdev->pm.sclk; in r100_bandwidth_update()
3280 mclk_ff = rdev->pm.mclk; in r100_bandwidth_update()
3282 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); in r100_bandwidth_update()
3283 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()
3284 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); in r100_bandwidth_update()
3286 pix_clk.full = 0; in r100_bandwidth_update()
3287 pix_clk2.full = 0; in r100_bandwidth_update()
3288 peak_disp_bw.full = 0; in r100_bandwidth_update()
3290 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3291 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3292 pix_clk.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3293 temp_ff.full = dfixed_const(pixel_bytes1); in r100_bandwidth_update()
3294 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3297 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3298 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()
3299 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); in r100_bandwidth_update()
3300 temp_ff.full = dfixed_const(pixel_bytes2); in r100_bandwidth_update()
3301 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); in r100_bandwidth_update()
3304 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); in r100_bandwidth_update()
3305 if (peak_disp_bw.full >= mem_bw.full) { in r100_bandwidth_update()
3312 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ in r100_bandwidth_update()
3316 } else if (rdev->family == CHIP_R300 || in r100_bandwidth_update()
3317 rdev->family == CHIP_R350) { /* r300, r350 */ in r100_bandwidth_update()
3321 } else if (rdev->family == CHIP_RV350 || in r100_bandwidth_update()
3322 rdev->family == CHIP_RV380) { in r100_bandwidth_update()
3327 } else if (rdev->family == CHIP_R420 || in r100_bandwidth_update()
3328 rdev->family == CHIP_R423 || in r100_bandwidth_update()
3329 rdev->family == CHIP_RV410) { in r100_bandwidth_update()
3346 trcd_ff.full = dfixed_const(mem_trcd); in r100_bandwidth_update()
3347 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()
3348 tras_ff.full = dfixed_const(mem_tras); in r100_bandwidth_update()
3353 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3354 if (rdev->family == CHIP_RS480) /* don't think rs400 */ in r100_bandwidth_update()
3361 if (rdev->family == CHIP_RS400 || in r100_bandwidth_update()
3362 rdev->family == CHIP_RS480) { in r100_bandwidth_update()
3363 /* extra cas latency stored in bits 23-25 0-4 clocks */ in r100_bandwidth_update()
3366 tcas_ff.full += dfixed_const(data); in r100_bandwidth_update()
3369 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { in r100_bandwidth_update()
3390 if (rdev->family == CHIP_RV410 || in r100_bandwidth_update()
3391 rdev->family == CHIP_R420 || in r100_bandwidth_update()
3392 rdev->family == CHIP_R423) in r100_bandwidth_update()
3396 tcas_ff.full += trbs_ff.full; in r100_bandwidth_update()
3399 sclk_eff_ff.full = sclk_ff.full; in r100_bandwidth_update()
3401 if (rdev->flags & RADEON_IS_AGP) { in r100_bandwidth_update()
3403 agpmode_ff.full = dfixed_const(radeon_agpmode); in r100_bandwidth_update()
3404 temp_ff.full = dfixed_const_666(16); in r100_bandwidth_update()
3405 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); in r100_bandwidth_update()
3407 /* TODO PCIE lanes may affect this - agpmode == 16?? */ in r100_bandwidth_update()
3410 sclk_delay_ff.full = dfixed_const(250); in r100_bandwidth_update()
3412 if ((rdev->family == CHIP_RV100) || in r100_bandwidth_update()
3413 rdev->flags & RADEON_IS_IGP) { in r100_bandwidth_update()
3414 if (rdev->mc.vram_is_ddr) in r100_bandwidth_update()
3415 sclk_delay_ff.full = dfixed_const(41); in r100_bandwidth_update()
3417 sclk_delay_ff.full = dfixed_const(33); in r100_bandwidth_update()
3419 if (rdev->mc.vram_width == 128) in r100_bandwidth_update()
3420 sclk_delay_ff.full = dfixed_const(57); in r100_bandwidth_update()
3422 sclk_delay_ff.full = dfixed_const(41); in r100_bandwidth_update()
3426 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); in r100_bandwidth_update()
3428 if (rdev->mc.vram_is_ddr) { in r100_bandwidth_update()
3429 if (rdev->mc.vram_width == 32) { in r100_bandwidth_update()
3430 k1.full = dfixed_const(40); in r100_bandwidth_update()
3433 k1.full = dfixed_const(20); in r100_bandwidth_update()
3437 k1.full = dfixed_const(40); in r100_bandwidth_update()
3441 temp_ff.full = dfixed_const(2); in r100_bandwidth_update()
3442 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); in r100_bandwidth_update()
3443 temp_ff.full = dfixed_const(c); in r100_bandwidth_update()
3444 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); in r100_bandwidth_update()
3445 temp_ff.full = dfixed_const(4); in r100_bandwidth_update()
3446 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); in r100_bandwidth_update()
3447 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); in r100_bandwidth_update()
3448 mc_latency_mclk.full += k1.full; in r100_bandwidth_update()
3450 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); in r100_bandwidth_update()
3451 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); in r100_bandwidth_update()
3454 HW cursor time assuming worst case of full size colour cursor. in r100_bandwidth_update()
3456 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); in r100_bandwidth_update()
3457 temp_ff.full += trcd_ff.full; in r100_bandwidth_update()
3458 if (temp_ff.full < tras_ff.full) in r100_bandwidth_update()
3459 temp_ff.full = tras_ff.full; in r100_bandwidth_update()
3460 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); in r100_bandwidth_update()
3462 temp_ff.full = dfixed_const(cur_size); in r100_bandwidth_update()
3463 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); in r100_bandwidth_update()
3467 disp_latency_overhead.full = dfixed_const(8); in r100_bandwidth_update()
3468 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); in r100_bandwidth_update()
3469 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; in r100_bandwidth_update()
3470 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; in r100_bandwidth_update()
3472 if (mc_latency_mclk.full > mc_latency_sclk.full) in r100_bandwidth_update()
3473 disp_latency.full = mc_latency_mclk.full; in r100_bandwidth_update()
3475 disp_latency.full = mc_latency_sclk.full; in r100_bandwidth_update()
3488 stop_req = mode1->hdisplay * pixel_bytes1 / 16; in r100_bandwidth_update()
3496 temp_ff.full = dfixed_const((16/pixel_bytes1)); in r100_bandwidth_update()
3497 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3502 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); in r100_bandwidth_update()
3503 crit_point_ff.full += dfixed_const_half(0); in r100_bandwidth_update()
3507 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3512 The critical point should never be above max_stop_req-4. Setting in r100_bandwidth_update()
3515 if (max_stop_req - critical_point < 4) in r100_bandwidth_update()
3518 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3527 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3529 stop_req -= 0x10; in r100_bandwidth_update()
3543 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3544 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3562 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ in r100_bandwidth_update()
3568 stop_req = mode2->hdisplay * pixel_bytes2 / 16; in r100_bandwidth_update()
3576 temp_ff.full = dfixed_const((16/pixel_bytes2)); in r100_bandwidth_update()
3577 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); in r100_bandwidth_update()
3583 if ((rdev->family == CHIP_R350) && in r100_bandwidth_update()
3585 stop_req -= 0x10; in r100_bandwidth_update()
3593 if ((rdev->family == CHIP_RS100) || in r100_bandwidth_update()
3594 (rdev->family == CHIP_RS200)) in r100_bandwidth_update()
3597 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; in r100_bandwidth_update()
3598 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()
3599 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); in r100_bandwidth_update()
3600 if (sclk_ff.full < temp_ff.full) in r100_bandwidth_update()
3601 temp_ff.full = sclk_ff.full; in r100_bandwidth_update()
3603 read_return_rate.full = temp_ff.full; in r100_bandwidth_update()
3606 temp_ff.full = read_return_rate.full - disp_drain_rate.full; in r100_bandwidth_update()
3607 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); in r100_bandwidth_update()
3609 time_disp1_drop_priority.full = 0; in r100_bandwidth_update()
3611 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; in r100_bandwidth_update()
3612 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); in r100_bandwidth_update()
3613 crit_point_ff.full += dfixed_const_half(0); in r100_bandwidth_update()
3617 if (rdev->disp_priority == 2) { in r100_bandwidth_update()
3621 if (max_stop_req - critical_point2 < 4) in r100_bandwidth_update()
3626 if (critical_point2 == 0 && rdev->family == CHIP_R300) { in r100_bandwidth_update()
3634 if ((rdev->family == CHIP_RS400) || in r100_bandwidth_update()
3635 (rdev->family == CHIP_RS480)) { in r100_bandwidth_update()
3663 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in r100_bandwidth_update()
3666 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in r100_bandwidth_update()
3691 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ring_test()
3698 if (i < rdev->usec_timeout) { in r100_ring_test()
3703 r = -EINVAL; in r100_ring_test()
3711 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_ring_ib_execute()
3713 if (ring->rptr_save_reg) { in r100_ring_ib_execute()
3714 u32 next_rptr = ring->wptr + 2 + 3; in r100_ring_ib_execute()
3715 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); in r100_ring_ib_execute()
3720 radeon_ring_write(ring, ib->gpu_addr); in r100_ring_ib_execute()
3721 radeon_ring_write(ring, ib->length_dw); in r100_ring_ib_execute()
3764 r = -ETIMEDOUT; in r100_ib_test()
3768 for (i = 0; i < rdev->usec_timeout; i++) { in r100_ib_test()
3775 if (i < rdev->usec_timeout) { in r100_ib_test()
3780 r = -EINVAL; in r100_ib_test()
3794 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_mc_stop()
3798 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3799 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3800 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3801 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3802 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3803 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3804 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3808 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3810 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); in r100_mc_stop()
3811 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | in r100_mc_stop()
3814 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | in r100_mc_stop()
3818 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); in r100_mc_stop()
3819 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_stop()
3820 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | in r100_mc_stop()
3823 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | in r100_mc_stop()
3827 C_000360_CUR2_LOCK & save->CUR2_OFFSET); in r100_mc_stop()
3834 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3835 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3836 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); in r100_mc_resume()
3839 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3840 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); in r100_mc_resume()
3841 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); in r100_mc_resume()
3842 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { in r100_mc_resume()
3843 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); in r100_mc_resume()
3861 if (rdev->flags & RADEON_IS_AGP) { in r100_mc_program()
3863 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r100_mc_program()
3864 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r100_mc_program()
3865 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r100_mc_program()
3866 if (rdev->family > CHIP_RV200) in r100_mc_program()
3868 upper_32_bits(rdev->mc.agp_base) & 0xff); in r100_mc_program()
3872 if (rdev->family > CHIP_RV200) in r100_mc_program()
3877 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); in r100_mc_program()
3880 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r100_mc_program()
3881 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r100_mc_program()
3889 if (radeon_dynclks != -1 && radeon_dynclks) in r100_clock_startup()
3894 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) in r100_clock_startup()
3912 if (rdev->flags & RADEON_IS_PCI) { in r100_startup()
3925 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r100_startup()
3930 if (!rdev->irq.installed) { in r100_startup()
3937 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3941 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r100_startup()
3947 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r100_startup()
3959 if (rdev->flags & RADEON_IS_PCI) in r100_resume()
3965 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r100_resume()
3976 rdev->accel_working = true; in r100_resume()
3979 rdev->accel_working = false; in r100_resume()
3990 if (rdev->flags & RADEON_IS_PCI) in r100_suspend()
4002 if (rdev->flags & RADEON_IS_PCI) in r100_fini()
4009 kfree(rdev->bios); in r100_fini()
4010 rdev->bios = NULL; in r100_fini()
4056 return -EINVAL; in r100_init()
4058 if (rdev->is_atom_bios) { in r100_init()
4059 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in r100_init()
4060 return -EINVAL; in r100_init()
4068 dev_warn(rdev->dev, in r100_init()
4075 return -EINVAL; in r100_init()
4081 if (rdev->flags & RADEON_IS_AGP) { in r100_init()
4095 if (rdev->flags & RADEON_IS_PCI) { in r100_init()
4105 rdev->accel_working = true; in r100_init()
4109 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r100_init()
4114 if (rdev->flags & RADEON_IS_PCI) in r100_init()
4116 rdev->accel_working = false; in r100_init()
4126 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4127 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_rreg_slow()
4128 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_rreg_slow()
4129 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_rreg_slow()
4137 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4138 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); in r100_mm_wreg_slow()
4139 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); in r100_mm_wreg_slow()
4140 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); in r100_mm_wreg_slow()
4145 if (reg < rdev->rio_mem_size) in r100_io_rreg()
4146 return ioread32(rdev->rio_mem + reg); in r100_io_rreg()
4148 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_rreg()
4149 return ioread32(rdev->rio_mem + RADEON_MM_DATA); in r100_io_rreg()
4155 if (reg < rdev->rio_mem_size) in r100_io_wreg()
4156 iowrite32(v, rdev->rio_mem + reg); in r100_io_wreg()
4158 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); in r100_io_wreg()
4159 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); in r100_io_wreg()