Lines Matching +full:0 +full:x01ffffff
119 #define NISLANDS_SMC_STROBE_RATIO 0x0F
120 #define NISLANDS_SMC_STROBE_ENABLE 0x10
122 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
123 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
124 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
125 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
147 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
179 #define NI_SMC_SOFT_REGISTERS_START 0x108
181 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
182 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
183 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10
184 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C
185 #define NI_SMC_SOFT_REGISTER_seq_index 0x64
186 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
187 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
188 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80
189 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84
190 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98
294 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff
295 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
296 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000
298 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff
299 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0
300 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000
305 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100
307 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0
308 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4
309 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8
310 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC
311 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10
312 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14
313 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20
314 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C
315 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30