Lines Matching refs:rdev
47 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) in tn_smc_rreg() argument
52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
59 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in tn_smc_wreg() argument
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
437 static void ni_init_golden_registers(struct radeon_device *rdev) in ni_init_golden_registers() argument
439 switch (rdev->family) { in ni_init_golden_registers()
441 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
444 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
449 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
450 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
451 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
452 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
453 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
454 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
455 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
456 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
457 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
458 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
459 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
460 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
461 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
462 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
463 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
464 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
465 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
466 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
467 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
468 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
471 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
475 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
478 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
618 int ni_mc_load_microcode(struct radeon_device *rdev) in ni_mc_load_microcode() argument
625 if (!rdev->mc_fw) in ni_mc_load_microcode()
628 switch (rdev->family) { in ni_mc_load_microcode()
666 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
676 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
686 int ni_init_microcode(struct radeon_device *rdev) in ni_init_microcode() argument
697 switch (rdev->family) { in ni_init_microcode()
750 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
753 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
755 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
761 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
764 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
766 rdev->me_fw->size, fw_name); in ni_init_microcode()
771 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
774 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
776 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
781 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
786 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
788 rdev->mc_fw->size, fw_name); in ni_init_microcode()
793 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
795 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
798 release_firmware(rdev->smc_fw); in ni_init_microcode()
799 rdev->smc_fw = NULL; in ni_init_microcode()
801 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
803 rdev->smc_fw->size, fw_name); in ni_init_microcode()
813 release_firmware(rdev->pfp_fw); in ni_init_microcode()
814 rdev->pfp_fw = NULL; in ni_init_microcode()
815 release_firmware(rdev->me_fw); in ni_init_microcode()
816 rdev->me_fw = NULL; in ni_init_microcode()
817 release_firmware(rdev->rlc_fw); in ni_init_microcode()
818 rdev->rlc_fw = NULL; in ni_init_microcode()
819 release_firmware(rdev->mc_fw); in ni_init_microcode()
820 rdev->mc_fw = NULL; in ni_init_microcode()
835 int cayman_get_allowed_info_register(struct radeon_device *rdev, in cayman_get_allowed_info_register() argument
854 int tn_get_temp(struct radeon_device *rdev) in tn_get_temp() argument
865 static void cayman_gpu_init(struct radeon_device *rdev) in cayman_gpu_init() argument
878 switch (rdev->family) { in cayman_gpu_init()
880 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
881 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
882 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
883 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
884 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
885 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
886 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
887 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
888 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
889 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
890 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
891 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
892 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
893 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
894 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
895 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
897 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
898 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
899 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
904 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
905 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
906 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
907 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
908 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
909 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
910 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
911 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
912 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
913 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
914 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
915 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
916 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
917 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
918 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
919 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
920 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
921 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
922 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
923 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
924 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
925 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
926 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
927 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
928 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
929 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
930 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
931 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
932 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
933 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
934 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
935 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
936 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
937 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
938 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
939 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
940 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
941 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
944 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
945 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
946 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
947 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
948 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
949 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
950 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
951 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
952 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
953 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
954 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
956 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
957 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
958 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
959 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
960 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
961 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
963 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
964 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
965 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
966 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
967 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
968 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
969 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
971 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
972 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
973 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
991 evergreen_fix_pci_max_read_req_size(rdev); in cayman_gpu_init()
997 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
998 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
999 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1001 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1002 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1003 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1006 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1008 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1010 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1012 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1014 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1016 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1026 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1027 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1030 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1033 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1036 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1039 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1044 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1045 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1049 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1052 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1056 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1060 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1062 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1066 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1078 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1082 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1086 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1092 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1096 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1103 if (ASIC_IS_DCE6(rdev)) in cayman_gpu_init()
1112 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1113 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1123 tmp = r6xx_remap_render_backend(rdev, tmp, in cayman_gpu_init()
1124 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1125 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1128 rdev->config.cayman.backend_map = tmp; in cayman_gpu_init()
1132 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1154 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1170 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1171 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1172 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1174 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1175 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1176 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1183 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1226 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1239 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) in cayman_pcie_gart_tlb_flush() argument
1248 static int cayman_pcie_gart_enable(struct radeon_device *rdev) in cayman_pcie_gart_enable() argument
1252 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1253 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1256 r = radeon_gart_table_vram_pin(rdev); in cayman_pcie_gart_enable()
1279 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1283 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1300 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1302 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1307 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1324 cayman_pcie_gart_tlb_flush(rdev); in cayman_pcie_gart_enable()
1326 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1327 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1328 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1332 static void cayman_pcie_gart_disable(struct radeon_device *rdev) in cayman_pcie_gart_disable() argument
1337 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1356 radeon_gart_table_vram_unpin(rdev); in cayman_pcie_gart_disable()
1359 static void cayman_pcie_gart_fini(struct radeon_device *rdev) in cayman_pcie_gart_fini() argument
1361 cayman_pcie_gart_disable(rdev); in cayman_pcie_gart_fini()
1362 radeon_gart_table_vram_free(rdev); in cayman_pcie_gart_fini()
1363 radeon_gart_fini(rdev); in cayman_pcie_gart_fini()
1366 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, in cayman_cp_int_cntl_setup() argument
1376 void cayman_fence_ring_emit(struct radeon_device *rdev, in cayman_fence_ring_emit() argument
1379 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit()
1380 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1399 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in cayman_ring_ib_execute() argument
1401 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute()
1435 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) in cayman_cp_enable() argument
1440 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1441 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1444 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1448 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, in cayman_gfx_get_rptr() argument
1453 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1454 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1467 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, in cayman_gfx_get_wptr() argument
1482 void cayman_gfx_set_wptr(struct radeon_device *rdev, in cayman_gfx_set_wptr() argument
1497 static int cayman_cp_load_microcode(struct radeon_device *rdev) in cayman_cp_load_microcode() argument
1502 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1505 cayman_cp_enable(rdev, false); in cayman_cp_load_microcode()
1507 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1513 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1524 static int cayman_cp_start(struct radeon_device *rdev) in cayman_cp_start() argument
1526 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1529 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1537 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1541 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1543 cayman_cp_enable(rdev, true); in cayman_cp_start()
1545 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1583 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1590 static void cayman_cp_fini(struct radeon_device *rdev) in cayman_cp_fini() argument
1592 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1593 cayman_cp_enable(rdev, false); in cayman_cp_fini()
1594 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1595 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1598 static int cayman_cp_resume(struct radeon_device *rdev) in cayman_cp_resume() argument
1659 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1667 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1676 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1683 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1689 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1701 cayman_cp_start(rdev); in cayman_cp_resume()
1702 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1703 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1704 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1706 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1708 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1709 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1710 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1714 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1715 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1720 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) in cayman_gpu_check_soft_reset() argument
1781 if (evergreen_is_display_hung(rdev)) in cayman_gpu_check_soft_reset()
1798 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in cayman_gpu_soft_reset() argument
1807 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1809 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1810 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1812 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1814 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1816 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1838 evergreen_mc_stop(rdev, &save); in cayman_gpu_soft_reset()
1839 if (evergreen_mc_wait_for_idle(rdev)) { in cayman_gpu_soft_reset()
1840 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1888 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1896 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1910 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1924 evergreen_mc_resume(rdev, &save); in cayman_gpu_soft_reset()
1927 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1930 int cayman_asic_reset(struct radeon_device *rdev, bool hard) in cayman_asic_reset() argument
1935 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1939 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1942 r600_set_bios_scratch_engine_hung(rdev, true); in cayman_asic_reset()
1944 cayman_gpu_soft_reset(rdev, reset_mask); in cayman_asic_reset()
1946 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1949 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1951 r600_set_bios_scratch_engine_hung(rdev, false); in cayman_asic_reset()
1965 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1967 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_gfx_is_lockup()
1972 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
1975 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
1978 static void cayman_uvd_init(struct radeon_device *rdev) in cayman_uvd_init() argument
1982 if (!rdev->has_uvd) in cayman_uvd_init()
1985 r = radeon_uvd_init(rdev); in cayman_uvd_init()
1987 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in cayman_uvd_init()
1994 rdev->has_uvd = false; in cayman_uvd_init()
1997 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in cayman_uvd_init()
1998 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in cayman_uvd_init()
2001 static void cayman_uvd_start(struct radeon_device *rdev) in cayman_uvd_start() argument
2005 if (!rdev->has_uvd) in cayman_uvd_start()
2008 r = uvd_v2_2_resume(rdev); in cayman_uvd_start()
2010 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in cayman_uvd_start()
2013 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in cayman_uvd_start()
2015 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in cayman_uvd_start()
2021 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2024 static void cayman_uvd_resume(struct radeon_device *rdev) in cayman_uvd_resume() argument
2029 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2032 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_uvd_resume()
2033 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2035 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in cayman_uvd_resume()
2038 r = uvd_v1_0_init(rdev); in cayman_uvd_resume()
2040 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in cayman_uvd_resume()
2045 static void cayman_vce_init(struct radeon_device *rdev) in cayman_vce_init() argument
2050 if (!rdev->has_vce) in cayman_vce_init()
2053 r = radeon_vce_init(rdev); in cayman_vce_init()
2055 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in cayman_vce_init()
2062 rdev->has_vce = false; in cayman_vce_init()
2065 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in cayman_vce_init()
2066 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in cayman_vce_init()
2067 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in cayman_vce_init()
2068 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in cayman_vce_init()
2071 static void cayman_vce_start(struct radeon_device *rdev) in cayman_vce_start() argument
2075 if (!rdev->has_vce) in cayman_vce_start()
2078 r = radeon_vce_resume(rdev); in cayman_vce_start()
2080 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2083 r = vce_v1_0_resume(rdev); in cayman_vce_start()
2085 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2088 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX); in cayman_vce_start()
2090 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in cayman_vce_start()
2093 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX); in cayman_vce_start()
2095 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in cayman_vce_start()
2101 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2102 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2105 static void cayman_vce_resume(struct radeon_device *rdev) in cayman_vce_resume() argument
2110 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2113 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_vce_resume()
2114 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2116 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2119 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_vce_resume()
2120 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2122 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2125 r = vce_v1_0_init(rdev); in cayman_vce_resume()
2127 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in cayman_vce_resume()
2132 static int cayman_startup(struct radeon_device *rdev) in cayman_startup() argument
2134 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup()
2138 evergreen_pcie_gen2_enable(rdev); in cayman_startup()
2140 evergreen_program_aspm(rdev); in cayman_startup()
2143 r = r600_vram_scratch_init(rdev); in cayman_startup()
2147 evergreen_mc_program(rdev); in cayman_startup()
2149 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2150 r = ni_mc_load_microcode(rdev); in cayman_startup()
2157 r = cayman_pcie_gart_enable(rdev); in cayman_startup()
2160 cayman_gpu_init(rdev); in cayman_startup()
2163 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2164 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2165 rdev->rlc.reg_list_size = in cayman_startup()
2167 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2168 r = sumo_rlc_init(rdev); in cayman_startup()
2176 r = radeon_wb_init(rdev); in cayman_startup()
2180 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in cayman_startup()
2182 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2186 cayman_uvd_start(rdev); in cayman_startup()
2187 cayman_vce_start(rdev); in cayman_startup()
2189 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cayman_startup()
2191 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2195 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in cayman_startup()
2197 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2201 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in cayman_startup()
2203 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2207 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in cayman_startup()
2209 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2214 if (!rdev->irq.installed) { in cayman_startup()
2215 r = radeon_irq_kms_init(rdev); in cayman_startup()
2220 r = r600_irq_init(rdev); in cayman_startup()
2223 radeon_irq_kms_fini(rdev); in cayman_startup()
2226 evergreen_irq_set(rdev); in cayman_startup()
2228 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2233 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2234 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2239 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2240 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2245 r = cayman_cp_load_microcode(rdev); in cayman_startup()
2248 r = cayman_cp_resume(rdev); in cayman_startup()
2252 r = cayman_dma_resume(rdev); in cayman_startup()
2256 cayman_uvd_resume(rdev); in cayman_startup()
2257 cayman_vce_resume(rdev); in cayman_startup()
2259 r = radeon_ib_pool_init(rdev); in cayman_startup()
2261 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2265 r = radeon_vm_manager_init(rdev); in cayman_startup()
2267 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2271 r = radeon_audio_init(rdev); in cayman_startup()
2278 int cayman_resume(struct radeon_device *rdev) in cayman_resume() argument
2287 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2290 ni_init_golden_registers(rdev); in cayman_resume()
2292 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2293 radeon_pm_resume(rdev); in cayman_resume()
2295 rdev->accel_working = true; in cayman_resume()
2296 r = cayman_startup(rdev); in cayman_resume()
2299 rdev->accel_working = false; in cayman_resume()
2305 int cayman_suspend(struct radeon_device *rdev) in cayman_suspend() argument
2307 radeon_pm_suspend(rdev); in cayman_suspend()
2308 radeon_audio_fini(rdev); in cayman_suspend()
2309 radeon_vm_manager_fini(rdev); in cayman_suspend()
2310 cayman_cp_enable(rdev, false); in cayman_suspend()
2311 cayman_dma_stop(rdev); in cayman_suspend()
2312 if (rdev->has_uvd) { in cayman_suspend()
2313 radeon_uvd_suspend(rdev); in cayman_suspend()
2314 uvd_v1_0_fini(rdev); in cayman_suspend()
2316 evergreen_irq_suspend(rdev); in cayman_suspend()
2317 radeon_wb_disable(rdev); in cayman_suspend()
2318 cayman_pcie_gart_disable(rdev); in cayman_suspend()
2328 int cayman_init(struct radeon_device *rdev) in cayman_init() argument
2330 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init()
2334 if (!radeon_get_bios(rdev)) { in cayman_init()
2335 if (ASIC_IS_AVIVO(rdev)) in cayman_init()
2339 if (!rdev->is_atom_bios) { in cayman_init()
2340 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2343 r = radeon_atombios_init(rdev); in cayman_init()
2348 if (!radeon_card_posted(rdev)) { in cayman_init()
2349 if (!rdev->bios) { in cayman_init()
2350 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2354 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2357 ni_init_golden_registers(rdev); in cayman_init()
2359 r600_scratch_init(rdev); in cayman_init()
2361 radeon_surface_init(rdev); in cayman_init()
2363 radeon_get_clock_info(rdev_to_drm(rdev)); in cayman_init()
2365 radeon_fence_driver_init(rdev); in cayman_init()
2367 r = evergreen_mc_init(rdev); in cayman_init()
2371 r = radeon_bo_init(rdev); in cayman_init()
2375 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2376 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2377 r = ni_init_microcode(rdev); in cayman_init()
2384 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2385 r = ni_init_microcode(rdev); in cayman_init()
2394 radeon_pm_init(rdev); in cayman_init()
2397 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2399 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2401 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2403 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2405 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2407 cayman_uvd_init(rdev); in cayman_init()
2408 cayman_vce_init(rdev); in cayman_init()
2410 rdev->ih.ring_obj = NULL; in cayman_init()
2411 r600_ih_ring_init(rdev, 64 * 1024); in cayman_init()
2413 r = r600_pcie_gart_init(rdev); in cayman_init()
2417 rdev->accel_working = true; in cayman_init()
2418 r = cayman_startup(rdev); in cayman_init()
2420 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2421 cayman_cp_fini(rdev); in cayman_init()
2422 cayman_dma_fini(rdev); in cayman_init()
2423 r600_irq_fini(rdev); in cayman_init()
2424 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2425 sumo_rlc_fini(rdev); in cayman_init()
2426 radeon_wb_fini(rdev); in cayman_init()
2427 radeon_ib_pool_fini(rdev); in cayman_init()
2428 radeon_vm_manager_fini(rdev); in cayman_init()
2429 radeon_irq_kms_fini(rdev); in cayman_init()
2430 cayman_pcie_gart_fini(rdev); in cayman_init()
2431 rdev->accel_working = false; in cayman_init()
2441 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2449 void cayman_fini(struct radeon_device *rdev) in cayman_fini() argument
2451 radeon_pm_fini(rdev); in cayman_fini()
2452 cayman_cp_fini(rdev); in cayman_fini()
2453 cayman_dma_fini(rdev); in cayman_fini()
2454 r600_irq_fini(rdev); in cayman_fini()
2455 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2456 sumo_rlc_fini(rdev); in cayman_fini()
2457 radeon_wb_fini(rdev); in cayman_fini()
2458 radeon_vm_manager_fini(rdev); in cayman_fini()
2459 radeon_ib_pool_fini(rdev); in cayman_fini()
2460 radeon_irq_kms_fini(rdev); in cayman_fini()
2461 uvd_v1_0_fini(rdev); in cayman_fini()
2462 radeon_uvd_fini(rdev); in cayman_fini()
2463 if (rdev->has_vce) in cayman_fini()
2464 radeon_vce_fini(rdev); in cayman_fini()
2465 cayman_pcie_gart_fini(rdev); in cayman_fini()
2466 r600_vram_scratch_fini(rdev); in cayman_fini()
2467 radeon_gem_fini(rdev); in cayman_fini()
2468 radeon_fence_driver_fini(rdev); in cayman_fini()
2469 radeon_bo_fini(rdev); in cayman_fini()
2470 radeon_atombios_fini(rdev); in cayman_fini()
2471 kfree(rdev->bios); in cayman_fini()
2472 rdev->bios = NULL; in cayman_fini()
2478 int cayman_vm_init(struct radeon_device *rdev) in cayman_vm_init() argument
2481 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2483 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2486 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2488 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2492 void cayman_vm_fini(struct radeon_device *rdev) in cayman_vm_fini() argument
2505 void cayman_vm_decode_fault(struct radeon_device *rdev, in cayman_vm_decode_fault() argument
2663 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2692 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2697 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in tn_set_vce_clocks()