Lines Matching full:track
48 /* value we track */
119 static void evergreen_cs_track_init(struct evergreen_cs_track *track) in evergreen_cs_track_init() argument
124 track->cb_color_fmask_bo[i] = NULL; in evergreen_cs_track_init()
125 track->cb_color_cmask_bo[i] = NULL; in evergreen_cs_track_init()
126 track->cb_color_cmask_slice[i] = 0; in evergreen_cs_track_init()
127 track->cb_color_fmask_slice[i] = 0; in evergreen_cs_track_init()
131 track->cb_color_bo[i] = NULL; in evergreen_cs_track_init()
132 track->cb_color_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
133 track->cb_color_info[i] = 0; in evergreen_cs_track_init()
134 track->cb_color_view[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
135 track->cb_color_pitch[i] = 0; in evergreen_cs_track_init()
136 track->cb_color_slice[i] = 0xfffffff; in evergreen_cs_track_init()
137 track->cb_color_slice_idx[i] = 0; in evergreen_cs_track_init()
139 track->cb_target_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
140 track->cb_shader_mask = 0xFFFFFFFF; in evergreen_cs_track_init()
141 track->cb_dirty = true; in evergreen_cs_track_init()
143 track->db_depth_slice = 0xffffffff; in evergreen_cs_track_init()
144 track->db_depth_view = 0xFFFFC000; in evergreen_cs_track_init()
145 track->db_depth_size = 0xFFFFFFFF; in evergreen_cs_track_init()
146 track->db_depth_control = 0xFFFFFFFF; in evergreen_cs_track_init()
147 track->db_z_info = 0xFFFFFFFF; in evergreen_cs_track_init()
148 track->db_z_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
149 track->db_z_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
150 track->db_z_read_bo = NULL; in evergreen_cs_track_init()
151 track->db_z_write_bo = NULL; in evergreen_cs_track_init()
152 track->db_s_info = 0xFFFFFFFF; in evergreen_cs_track_init()
153 track->db_s_read_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
154 track->db_s_write_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
155 track->db_s_read_bo = NULL; in evergreen_cs_track_init()
156 track->db_s_write_bo = NULL; in evergreen_cs_track_init()
157 track->db_dirty = true; in evergreen_cs_track_init()
158 track->htile_bo = NULL; in evergreen_cs_track_init()
159 track->htile_offset = 0xFFFFFFFF; in evergreen_cs_track_init()
160 track->htile_surface = 0; in evergreen_cs_track_init()
163 track->vgt_strmout_size[i] = 0; in evergreen_cs_track_init()
164 track->vgt_strmout_bo[i] = NULL; in evergreen_cs_track_init()
165 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; in evergreen_cs_track_init()
167 track->streamout_dirty = true; in evergreen_cs_track_init()
168 track->sx_misc_kill_all_prims = false; in evergreen_cs_track_init()
206 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned() local
209 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
211 surf->base_align = track->group_size; in evergreen_surface_check_linear_aligned()
228 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d() local
231 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
234 surf->base_align = track->group_size; in evergreen_surface_check_1d()
241 track->group_size, surf->bpe, surf->nsamples); in evergreen_surface_check_1d()
259 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d() local
270 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
397 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb() local
403 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; in evergreen_cs_track_validate_cb()
404 pitch = track->cb_color_pitch[id]; in evergreen_cs_track_validate_cb()
405 slice = track->cb_color_slice[id]; in evergreen_cs_track_validate_cb()
408 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
409 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
410 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
411 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
412 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
413 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
414 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
420 id, track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
432 __func__, __LINE__, id, track->cb_color_pitch[id], in evergreen_cs_track_validate_cb()
433 track->cb_color_slice[id], track->cb_color_attrib[id], in evergreen_cs_track_validate_cb()
434 track->cb_color_info[id]); in evergreen_cs_track_validate_cb()
438 offset = (u64)track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
446 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
459 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
460 tmp = (u64)track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
474 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
483 (u64)track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()
484 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
500 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile() local
503 if (track->htile_bo == NULL) { in evergreen_cs_track_validate_htile()
505 __func__, __LINE__, track->db_z_info); in evergreen_cs_track_validate_htile()
509 if (G_028ABC_LINEAR(track->htile_surface)) { in evergreen_cs_track_validate_htile()
513 nby = round_up(nby, track->npipes * 8); in evergreen_cs_track_validate_htile()
519 switch (track->npipes) { in evergreen_cs_track_validate_htile()
542 __func__, __LINE__, track->npipes); in evergreen_cs_track_validate_htile()
550 size = roundup(nbx * nby * 4, track->npipes * (2 << 10)); in evergreen_cs_track_validate_htile()
551 size += track->htile_offset; in evergreen_cs_track_validate_htile()
553 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
555 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
564 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil() local
570 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_stencil()
571 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_stencil()
572 slice = track->db_depth_slice; in evergreen_cs_track_validate_stencil()
575 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_stencil()
576 surf.format = G_028044_FORMAT(track->db_s_info); in evergreen_cs_track_validate_stencil()
577 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); in evergreen_cs_track_validate_stencil()
578 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_stencil()
579 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_stencil()
580 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_stencil()
581 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_stencil()
607 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
608 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
613 offset = (u64)track->db_s_read_offset << 8; in evergreen_cs_track_validate_stencil()
620 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
624 (u64)track->db_s_read_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
625 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
627 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_stencil()
628 track->db_depth_slice, track->db_s_info, track->db_z_info); in evergreen_cs_track_validate_stencil()
632 offset = (u64)track->db_s_write_offset << 8; in evergreen_cs_track_validate_stencil()
639 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
643 (u64)track->db_s_write_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
644 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
649 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_stencil()
661 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth() local
667 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; in evergreen_cs_track_validate_depth()
668 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_depth()
669 slice = track->db_depth_slice; in evergreen_cs_track_validate_depth()
672 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); in evergreen_cs_track_validate_depth()
673 surf.format = G_028040_FORMAT(track->db_z_info); in evergreen_cs_track_validate_depth()
674 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); in evergreen_cs_track_validate_depth()
675 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); in evergreen_cs_track_validate_depth()
676 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); in evergreen_cs_track_validate_depth()
677 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); in evergreen_cs_track_validate_depth()
678 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); in evergreen_cs_track_validate_depth()
698 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
699 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
706 __func__, __LINE__, track->db_depth_size, in evergreen_cs_track_validate_depth()
707 track->db_depth_slice, track->db_z_info); in evergreen_cs_track_validate_depth()
711 offset = (u64)track->db_z_read_offset << 8; in evergreen_cs_track_validate_depth()
718 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
722 (u64)track->db_z_read_offset << 8, mslice, in evergreen_cs_track_validate_depth()
723 radeon_bo_size(track->db_z_read_bo)); in evergreen_cs_track_validate_depth()
727 offset = (u64)track->db_z_write_offset << 8; in evergreen_cs_track_validate_depth()
734 if (offset > radeon_bo_size(track->db_z_write_bo)) { in evergreen_cs_track_validate_depth()
738 (u64)track->db_z_write_offset << 8, mslice, in evergreen_cs_track_validate_depth()
739 radeon_bo_size(track->db_z_write_bo)); in evergreen_cs_track_validate_depth()
744 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { in evergreen_cs_track_validate_depth()
935 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check() local
941 if (track->streamout_dirty && track->vgt_strmout_config) { in evergreen_cs_track_check()
943 if (track->vgt_strmout_config & (1 << i)) { in evergreen_cs_track_check()
944 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; in evergreen_cs_track_check()
950 if (track->vgt_strmout_bo[i]) { in evergreen_cs_track_check()
951 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + in evergreen_cs_track_check()
952 (u64)track->vgt_strmout_size[i]; in evergreen_cs_track_check()
953 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { in evergreen_cs_track_check()
956 radeon_bo_size(track->vgt_strmout_bo[i])); in evergreen_cs_track_check()
965 track->streamout_dirty = false; in evergreen_cs_track_check()
968 if (track->sx_misc_kill_all_prims) in evergreen_cs_track_check()
973 if (track->cb_dirty) { in evergreen_cs_track_check()
974 tmp = track->cb_target_mask; in evergreen_cs_track_check()
976 u32 format = G_028C70_FORMAT(track->cb_color_info[i]); in evergreen_cs_track_check()
981 if (track->cb_color_bo[i] == NULL) { in evergreen_cs_track_check()
983 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); in evergreen_cs_track_check()
993 track->cb_dirty = false; in evergreen_cs_track_check()
996 if (track->db_dirty) { in evergreen_cs_track_check()
998 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID && in evergreen_cs_track_check()
999 G_028800_STENCIL_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1005 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID && in evergreen_cs_track_check()
1006 G_028800_Z_ENABLE(track->db_depth_control)) { in evergreen_cs_track_check()
1011 track->db_dirty = false; in evergreen_cs_track_check()
1097 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_handle_reg() local
1153 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1154 track->db_dirty = true; in evergreen_cs_handle_reg()
1171 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1180 track->db_z_info &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1182 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1196 track->db_dirty = true; in evergreen_cs_handle_reg()
1199 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1200 track->db_dirty = true; in evergreen_cs_handle_reg()
1203 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1204 track->db_dirty = true; in evergreen_cs_handle_reg()
1207 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1208 track->db_dirty = true; in evergreen_cs_handle_reg()
1211 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1212 track->db_dirty = true; in evergreen_cs_handle_reg()
1221 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1223 track->db_z_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1224 track->db_dirty = true; in evergreen_cs_handle_reg()
1233 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1235 track->db_z_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1236 track->db_dirty = true; in evergreen_cs_handle_reg()
1245 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1247 track->db_s_read_bo = reloc->robj; in evergreen_cs_handle_reg()
1248 track->db_dirty = true; in evergreen_cs_handle_reg()
1257 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1259 track->db_s_write_bo = reloc->robj; in evergreen_cs_handle_reg()
1260 track->db_dirty = true; in evergreen_cs_handle_reg()
1263 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1264 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1267 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1268 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1281 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1283 track->vgt_strmout_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1284 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1292 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1293 track->streamout_dirty = true; in evergreen_cs_handle_reg()
1305 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1306 track->cb_dirty = true; in evergreen_cs_handle_reg()
1309 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1310 track->cb_dirty = true; in evergreen_cs_handle_reg()
1319 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1328 track->nsamples = 1 << tmp; in evergreen_cs_handle_reg()
1339 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1340 track->cb_dirty = true; in evergreen_cs_handle_reg()
1347 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1348 track->cb_dirty = true; in evergreen_cs_handle_reg()
1359 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1368 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1370 track->cb_dirty = true; in evergreen_cs_handle_reg()
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1386 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1388 track->cb_dirty = true; in evergreen_cs_handle_reg()
1399 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1400 track->cb_dirty = true; in evergreen_cs_handle_reg()
1407 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1408 track->cb_dirty = true; in evergreen_cs_handle_reg()
1419 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1420 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1421 track->cb_dirty = true; in evergreen_cs_handle_reg()
1428 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1429 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1430 track->cb_dirty = true; in evergreen_cs_handle_reg()
1453 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1461 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1462 track->cb_dirty = true; in evergreen_cs_handle_reg()
1481 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1489 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1490 track->cb_dirty = true; in evergreen_cs_handle_reg()
1507 track->cb_color_fmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1524 track->cb_color_cmask_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1535 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1546 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1563 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1565 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1566 track->cb_dirty = true; in evergreen_cs_handle_reg()
1579 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1581 track->cb_color_bo[tmp] = reloc->robj; in evergreen_cs_handle_reg()
1582 track->cb_dirty = true; in evergreen_cs_handle_reg()
1591 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1593 track->htile_bo = reloc->robj; in evergreen_cs_handle_reg()
1594 track->db_dirty = true; in evergreen_cs_handle_reg()
1598 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1601 track->db_dirty = true; in evergreen_cs_handle_reg()
1740 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1759 struct evergreen_cs_track *track = p->track; in evergreen_is_safe_reg() local
1767 if (!(track->reg_safe_bm[i] & m)) in evergreen_is_safe_reg()
1777 struct evergreen_cs_track *track; in evergreen_packet3_check() local
1785 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
2024 track->indirect_draw_buffer_size = radeon_bo_size(reloc->robj); in evergreen_packet3_check()
2046 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2048 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2375 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_packet3_check()
2676 struct evergreen_cs_track *track; in evergreen_cs_parse() local
2680 if (p->track == NULL) { in evergreen_cs_parse()
2682 track = kzalloc(sizeof(*track), GFP_KERNEL); in evergreen_cs_parse()
2683 if (track == NULL) in evergreen_cs_parse()
2685 evergreen_cs_track_init(track); in evergreen_cs_parse()
2688 track->reg_safe_bm = cayman_reg_safe_bm; in evergreen_cs_parse()
2691 track->reg_safe_bm = evergreen_reg_safe_bm; in evergreen_cs_parse()
2697 track->npipes = 1; in evergreen_cs_parse()
2701 track->npipes = 2; in evergreen_cs_parse()
2704 track->npipes = 4; in evergreen_cs_parse()
2707 track->npipes = 8; in evergreen_cs_parse()
2713 track->nbanks = 4; in evergreen_cs_parse()
2717 track->nbanks = 8; in evergreen_cs_parse()
2720 track->nbanks = 16; in evergreen_cs_parse()
2726 track->group_size = 256; in evergreen_cs_parse()
2730 track->group_size = 512; in evergreen_cs_parse()
2736 track->row_size = 1; in evergreen_cs_parse()
2740 track->row_size = 2; in evergreen_cs_parse()
2743 track->row_size = 4; in evergreen_cs_parse()
2747 p->track = track; in evergreen_cs_parse()
2752 kfree(p->track); in evergreen_cs_parse()
2753 p->track = NULL; in evergreen_cs_parse()
2768 kfree(p->track); in evergreen_cs_parse()
2769 p->track = NULL; in evergreen_cs_parse()
2773 kfree(p->track); in evergreen_cs_parse()
2774 p->track = NULL; in evergreen_cs_parse()
2784 kfree(p->track); in evergreen_cs_parse()
2785 p->track = NULL; in evergreen_cs_parse()