Lines Matching refs:rdev
57 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) in eg_cg_rreg() argument
62 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
65 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
69 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_cg_wreg() argument
73 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
76 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
79 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) in eg_pif_phy0_rreg() argument
84 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
87 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
91 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_pif_phy0_wreg() argument
95 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
98 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
101 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) in eg_pif_phy1_rreg() argument
106 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
109 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
113 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_pif_phy1_wreg() argument
117 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_wreg()
120 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_wreg()
220 static void evergreen_gpu_init(struct radeon_device *rdev);
221 void evergreen_fini(struct radeon_device *rdev);
222 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
223 void evergreen_program_aspm(struct radeon_device *rdev);
997 static void evergreen_init_golden_registers(struct radeon_device *rdev) in evergreen_init_golden_registers() argument
999 switch (rdev->family) { in evergreen_init_golden_registers()
1002 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1005 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1008 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1013 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1016 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1019 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1024 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1027 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1030 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1035 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1038 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1041 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1046 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1051 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1056 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1059 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1064 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1069 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1074 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1093 int evergreen_get_allowed_info_register(struct radeon_device *rdev, in evergreen_get_allowed_info_register() argument
1142 static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, in sumo_set_uvd_clock() argument
1148 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in sumo_set_uvd_clock()
1166 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in sumo_set_uvd_clocks() argument
1171 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); in sumo_set_uvd_clocks()
1177 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); in sumo_set_uvd_clocks()
1189 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in evergreen_set_uvd_clocks() argument
1209 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in evergreen_set_uvd_clocks()
1227 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1264 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1278 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) in evergreen_fix_pci_max_read_req_size() argument
1283 readrq = pcie_get_readrq(rdev->pdev); in evergreen_fix_pci_max_read_req_size()
1289 pcie_set_readrq(rdev->pdev, 512); in evergreen_fix_pci_max_read_req_size()
1295 struct radeon_device *rdev = dev->dev_private; in dce4_program_fmt() local
1348 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc) in dce4_is_in_vblank() argument
1356 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc) in dce4_is_counter_moving() argument
1377 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) in dce4_wait_for_vblank() argument
1381 if (crtc >= rdev->num_crtc) in dce4_wait_for_vblank()
1390 while (dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1392 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1397 while (!dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1399 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1416 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, in evergreen_page_flip() argument
1419 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip()
1445 bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id) in evergreen_page_flip_pending() argument
1447 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending()
1455 int evergreen_get_temp(struct radeon_device *rdev) in evergreen_get_temp() argument
1460 if (rdev->family == CHIP_JUNIPER) { in evergreen_get_temp()
1493 int sumo_get_temp(struct radeon_device *rdev) in sumo_get_temp() argument
1510 void sumo_pm_init_profile(struct radeon_device *rdev) in sumo_pm_init_profile() argument
1515 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1516 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1517 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1518 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1521 if (rdev->flags & RADEON_IS_MOBILITY) in sumo_pm_init_profile()
1522 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in sumo_pm_init_profile()
1524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1526 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1527 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1531 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1532 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1538 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1539 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1543 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1547 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1550 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1551 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1552 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1558 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1570 void btc_pm_init_profile(struct radeon_device *rdev) in btc_pm_init_profile() argument
1575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1583 if (rdev->flags & RADEON_IS_MOBILITY) in btc_pm_init_profile()
1584 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in btc_pm_init_profile()
1586 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in btc_pm_init_profile()
1588 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1589 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1590 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1591 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1593 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1594 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1595 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1596 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1598 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1599 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1600 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1601 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1603 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1604 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1605 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1606 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1608 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1609 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1610 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1611 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1613 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1614 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1615 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1616 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1627 void evergreen_pm_misc(struct radeon_device *rdev) in evergreen_pm_misc() argument
1629 int req_ps_idx = rdev->pm.requested_power_state_index; in evergreen_pm_misc()
1630 int req_cm_idx = rdev->pm.requested_clock_mode_index; in evergreen_pm_misc()
1631 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in evergreen_pm_misc()
1638 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { in evergreen_pm_misc()
1639 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in evergreen_pm_misc()
1640 rdev->pm.current_vddc = voltage->voltage; in evergreen_pm_misc()
1648 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && in evergreen_pm_misc()
1649 (rdev->family >= CHIP_BARTS) && in evergreen_pm_misc()
1650 rdev->pm.active_crtc_count && in evergreen_pm_misc()
1651 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || in evergreen_pm_misc()
1652 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) in evergreen_pm_misc()
1653 voltage = &rdev->pm.power_state[req_ps_idx]. in evergreen_pm_misc()
1654 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; in evergreen_pm_misc()
1659 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { in evergreen_pm_misc()
1660 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); in evergreen_pm_misc()
1661 rdev->pm.current_vddci = voltage->vddci; in evergreen_pm_misc()
1674 void evergreen_pm_prepare(struct radeon_device *rdev) in evergreen_pm_prepare() argument
1676 struct drm_device *ddev = rdev_to_drm(rdev); in evergreen_pm_prepare()
1699 void evergreen_pm_finish(struct radeon_device *rdev) in evergreen_pm_finish() argument
1701 struct drm_device *ddev = rdev_to_drm(rdev); in evergreen_pm_finish()
1726 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in evergreen_hpd_sense() argument
1742 void evergreen_hpd_set_polarity(struct radeon_device *rdev, in evergreen_hpd_set_polarity() argument
1745 bool connected = evergreen_hpd_sense(rdev, hpd); in evergreen_hpd_set_polarity()
1764 void evergreen_hpd_init(struct radeon_device *rdev) in evergreen_hpd_init() argument
1766 struct drm_device *dev = rdev_to_drm(rdev); in evergreen_hpd_init()
1792 radeon_hpd_set_polarity(rdev, hpd); in evergreen_hpd_init()
1794 radeon_irq_kms_enable_hpd(rdev, enabled); in evergreen_hpd_init()
1805 void evergreen_hpd_fini(struct radeon_device *rdev) in evergreen_hpd_fini() argument
1807 struct drm_device *dev = rdev_to_drm(rdev); in evergreen_hpd_fini()
1821 radeon_irq_kms_disable_hpd(rdev, disabled); in evergreen_hpd_fini()
1826 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, in evergreen_line_buffer_adjust() argument
1872 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { in evergreen_line_buffer_adjust()
1875 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_line_buffer_adjust()
1888 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1894 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1900 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1906 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1917 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) in evergreen_get_number_of_dram_channels() argument
2155 static void evergreen_program_watermarks(struct radeon_device *rdev, in evergreen_program_watermarks() argument
2180 dram_channels = evergreen_get_number_of_dram_channels(rdev); in evergreen_program_watermarks()
2183 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2185 radeon_dpm_get_mclk(rdev, false) * 10; in evergreen_program_watermarks()
2187 radeon_dpm_get_sclk(rdev, false) * 10; in evergreen_program_watermarks()
2189 wm_high.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2190 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2210 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2212 radeon_dpm_get_mclk(rdev, true) * 10; in evergreen_program_watermarks()
2214 radeon_dpm_get_sclk(rdev, true) * 10; in evergreen_program_watermarks()
2216 wm_low.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2217 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2246 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2253 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2324 void evergreen_bandwidth_update(struct radeon_device *rdev) in evergreen_bandwidth_update() argument
2331 if (!rdev->mode_info.mode_config_initialized) in evergreen_bandwidth_update()
2334 radeon_update_display_priority(rdev); in evergreen_bandwidth_update()
2336 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_bandwidth_update()
2337 if (rdev->mode_info.crtcs[i]->base.enabled) in evergreen_bandwidth_update()
2340 for (i = 0; i < rdev->num_crtc; i += 2) { in evergreen_bandwidth_update()
2341 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update()
2342 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in evergreen_bandwidth_update()
2343 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2344 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2345 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
2346 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in evergreen_bandwidth_update()
2359 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) in evergreen_mc_wait_for_idle() argument
2364 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_mc_wait_for_idle()
2377 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) in evergreen_pcie_gart_tlb_flush() argument
2385 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_pcie_gart_tlb_flush()
2400 static int evergreen_pcie_gart_enable(struct radeon_device *rdev) in evergreen_pcie_gart_enable() argument
2405 if (rdev->gart.robj == NULL) { in evergreen_pcie_gart_enable()
2406 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in evergreen_pcie_gart_enable()
2409 r = radeon_gart_table_vram_pin(rdev); in evergreen_pcie_gart_enable()
2423 if (rdev->flags & RADEON_IS_IGP) { in evergreen_pcie_gart_enable()
2431 if ((rdev->family == CHIP_JUNIPER) || in evergreen_pcie_gart_enable()
2432 (rdev->family == CHIP_CYPRESS) || in evergreen_pcie_gart_enable()
2433 (rdev->family == CHIP_HEMLOCK) || in evergreen_pcie_gart_enable()
2434 (rdev->family == CHIP_BARTS)) in evergreen_pcie_gart_enable()
2441 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2442 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2443 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2447 (u32)(rdev->dummy_page.addr >> 12)); in evergreen_pcie_gart_enable()
2450 evergreen_pcie_gart_tlb_flush(rdev); in evergreen_pcie_gart_enable()
2452 (unsigned)(rdev->mc.gtt_size >> 20), in evergreen_pcie_gart_enable()
2453 (unsigned long long)rdev->gart.table_addr); in evergreen_pcie_gart_enable()
2454 rdev->gart.ready = true; in evergreen_pcie_gart_enable()
2458 static void evergreen_pcie_gart_disable(struct radeon_device *rdev) in evergreen_pcie_gart_disable() argument
2480 radeon_gart_table_vram_unpin(rdev); in evergreen_pcie_gart_disable()
2483 static void evergreen_pcie_gart_fini(struct radeon_device *rdev) in evergreen_pcie_gart_fini() argument
2485 evergreen_pcie_gart_disable(rdev); in evergreen_pcie_gart_fini()
2486 radeon_gart_table_vram_free(rdev); in evergreen_pcie_gart_fini()
2487 radeon_gart_fini(rdev); in evergreen_pcie_gart_fini()
2491 static void evergreen_agp_enable(struct radeon_device *rdev) in evergreen_agp_enable() argument
2563 static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev, in evergreen_is_dp_sst_stream_enabled() argument
2623 static void evergreen_blank_dp_output(struct radeon_device *rdev, in evergreen_blank_dp_output() argument
2663 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_stop() argument
2669 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_stop()
2677 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2681 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_stop()
2684 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2693 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2701 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_stop()
2702 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_stop()
2703 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_stop()
2714 if (ASIC_IS_DCE5(rdev) && in evergreen_mc_stop()
2715 evergreen_is_dp_sst_stream_enabled(rdev, i, &dig_fe)) in evergreen_mc_stop()
2716 evergreen_blank_dp_output(rdev, dig_fe); in evergreen_mc_stop()
2731 radeon_mc_wait_for_idle(rdev); in evergreen_mc_stop()
2745 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2761 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_resume() argument
2767 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2769 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2771 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2773 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2775 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2778 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2779 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2780 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2784 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2801 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2817 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2819 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_resume()
2833 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_resume()
2834 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2835 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_resume()
2841 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2849 void evergreen_mc_program(struct radeon_device *rdev) in evergreen_mc_program() argument
2865 evergreen_mc_stop(rdev, &save); in evergreen_mc_program()
2866 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2867 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2872 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2873 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
2876 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2878 rdev->mc.gtt_end >> 12); in evergreen_mc_program()
2882 rdev->mc.gtt_start >> 12); in evergreen_mc_program()
2884 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2888 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2890 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2892 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2894 if ((rdev->family == CHIP_PALM) || in evergreen_mc_program()
2895 (rdev->family == CHIP_SUMO) || in evergreen_mc_program()
2896 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_program()
2898 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; in evergreen_mc_program()
2899 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
2902 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in evergreen_mc_program()
2903 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in evergreen_mc_program()
2905 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2908 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2909 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
2910 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
2911 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
2917 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2918 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2920 evergreen_mc_resume(rdev, &save); in evergreen_mc_program()
2923 rv515_vga_render_disable(rdev); in evergreen_mc_program()
2929 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ring_ib_execute() argument
2931 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_ring_ib_execute()
2944 } else if (rdev->wb.enabled) { in evergreen_ring_ib_execute()
2964 static int evergreen_cp_load_microcode(struct radeon_device *rdev) in evergreen_cp_load_microcode() argument
2969 if (!rdev->me_fw || !rdev->pfp_fw) in evergreen_cp_load_microcode()
2972 r700_cp_stop(rdev); in evergreen_cp_load_microcode()
2979 fw_data = (const __be32 *)rdev->pfp_fw->data; in evergreen_cp_load_microcode()
2985 fw_data = (const __be32 *)rdev->me_fw->data; in evergreen_cp_load_microcode()
2996 static int evergreen_cp_start(struct radeon_device *rdev) in evergreen_cp_start() argument
2998 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_start()
3002 r = radeon_ring_lock(rdev, ring, 7); in evergreen_cp_start()
3010 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); in evergreen_cp_start()
3014 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3019 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); in evergreen_cp_start()
3057 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3062 static int evergreen_cp_resume(struct radeon_device *rdev) in evergreen_cp_resume() argument
3064 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_resume()
3102 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in evergreen_cp_resume()
3103 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3104 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3106 if (rdev->wb.enabled) in evergreen_cp_resume()
3119 evergreen_cp_start(rdev); in evergreen_cp_resume()
3121 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in evergreen_cp_resume()
3132 static void evergreen_gpu_init(struct radeon_device *rdev) in evergreen_gpu_init() argument
3153 switch (rdev->family) { in evergreen_gpu_init()
3156 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3157 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3158 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3159 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3160 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3161 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3162 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3163 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3164 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3165 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3166 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3167 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3168 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3169 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3170 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3172 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3173 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3174 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3178 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3179 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3180 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3181 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3182 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3183 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3184 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3185 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3186 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3187 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3188 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3189 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3190 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3191 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3192 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3194 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3195 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3196 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3200 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3201 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3202 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3203 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3204 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3205 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3206 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3207 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3208 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3209 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3210 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3211 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3212 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3213 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3214 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3216 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3217 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3218 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3223 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3224 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3225 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3226 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3227 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3228 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3229 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3230 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3231 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3232 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3233 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3234 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3235 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3236 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3237 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3239 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3240 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3241 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3245 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3246 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3247 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3248 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3249 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3250 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3251 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3252 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3253 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3254 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3255 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3256 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3257 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3258 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3259 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3261 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3262 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3263 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3267 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3268 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3269 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3270 if (rdev->pdev->device == 0x9648) in evergreen_gpu_init()
3271 rdev->config.evergreen.max_simds = 3; in evergreen_gpu_init()
3272 else if ((rdev->pdev->device == 0x9647) || in evergreen_gpu_init()
3273 (rdev->pdev->device == 0x964a)) in evergreen_gpu_init()
3274 rdev->config.evergreen.max_simds = 4; in evergreen_gpu_init()
3276 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3277 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3278 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3279 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3280 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3281 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3282 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3283 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3284 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3285 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3286 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3287 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3289 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3290 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3291 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3295 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3296 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3297 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3298 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3299 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3300 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3301 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3302 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3303 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3304 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3305 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3306 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3307 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3308 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3309 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3311 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3312 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3313 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3317 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3318 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3319 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3320 rdev->config.evergreen.max_simds = 7; in evergreen_gpu_init()
3321 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3322 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3323 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3324 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3325 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3326 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3327 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3328 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3329 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3330 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3331 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3333 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3334 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3335 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3339 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3340 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3341 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3342 rdev->config.evergreen.max_simds = 6; in evergreen_gpu_init()
3343 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3344 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3345 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3346 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3347 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3348 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3349 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3350 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3351 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3352 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3353 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3355 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3356 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3357 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3361 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3362 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3363 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3364 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3365 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3366 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3367 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3368 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3369 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3370 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3371 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3372 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3373 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3374 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3375 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3377 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3378 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3379 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3397 evergreen_fix_pci_max_read_req_size(rdev); in evergreen_gpu_init()
3400 if ((rdev->family == CHIP_PALM) || in evergreen_gpu_init()
3401 (rdev->family == CHIP_SUMO) || in evergreen_gpu_init()
3402 (rdev->family == CHIP_SUMO2)) in evergreen_gpu_init()
3414 rdev->config.evergreen.tile_config = 0; in evergreen_gpu_init()
3415 switch (rdev->config.evergreen.max_tile_pipes) { in evergreen_gpu_init()
3418 rdev->config.evergreen.tile_config |= (0 << 0); in evergreen_gpu_init()
3421 rdev->config.evergreen.tile_config |= (1 << 0); in evergreen_gpu_init()
3424 rdev->config.evergreen.tile_config |= (2 << 0); in evergreen_gpu_init()
3427 rdev->config.evergreen.tile_config |= (3 << 0); in evergreen_gpu_init()
3431 if (rdev->flags & RADEON_IS_IGP) in evergreen_gpu_init()
3432 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3436 rdev->config.evergreen.tile_config |= 0 << 4; in evergreen_gpu_init()
3439 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3443 rdev->config.evergreen.tile_config |= 2 << 4; in evergreen_gpu_init()
3447 rdev->config.evergreen.tile_config |= 0 << 8; in evergreen_gpu_init()
3448 rdev->config.evergreen.tile_config |= in evergreen_gpu_init()
3451 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { in evergreen_gpu_init()
3461 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { in evergreen_gpu_init()
3474 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3478 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3482 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { in evergreen_gpu_init()
3488 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds; in evergreen_gpu_init()
3492 rdev->config.evergreen.active_simds = hweight32(~tmp); in evergreen_gpu_init()
3505 if ((rdev->config.evergreen.max_backends == 1) && in evergreen_gpu_init()
3506 (rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_init()
3516 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, in evergreen_gpu_init()
3519 rdev->config.evergreen.backend_map = tmp; in evergreen_gpu_init()
3545 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); in evergreen_gpu_init()
3548 if (rdev->family <= CHIP_SUMO2) in evergreen_gpu_init()
3551 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3552 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | in evergreen_gpu_init()
3553 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); in evergreen_gpu_init()
3555 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3556 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | in evergreen_gpu_init()
3557 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); in evergreen_gpu_init()
3564 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3581 switch (rdev->family) { in evergreen_gpu_init()
3596 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 12 / 32); in evergreen_gpu_init()
3597 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); in evergreen_gpu_init()
3599 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3600 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3601 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3602 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3604 switch (rdev->family) { in evergreen_gpu_init()
3617 …sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3618 …sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3619 …sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3620 …sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count… in evergreen_gpu_init()
3621 …sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_coun… in evergreen_gpu_init()
3623 …sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3624 …sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3625 …sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3626 …sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3627 …sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3628 …sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3645 switch (rdev->family) { in evergreen_gpu_init()
3709 int evergreen_mc_init(struct radeon_device *rdev) in evergreen_mc_init() argument
3715 rdev->mc.vram_is_ddr = true; in evergreen_mc_init()
3716 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3717 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3718 (rdev->family == CHIP_SUMO2)) in evergreen_mc_init()
3745 rdev->mc.vram_width = numchan * chansize; in evergreen_mc_init()
3747 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in evergreen_mc_init()
3748 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in evergreen_mc_init()
3750 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3751 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3752 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_init()
3754 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3755 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3758 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3759 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3761 rdev->mc.visible_vram_size = rdev->mc.aper_size; in evergreen_mc_init()
3762 r700_vram_gtt_location(rdev, &rdev->mc); in evergreen_mc_init()
3763 radeon_update_bandwidth_info(rdev); in evergreen_mc_init()
3768 void evergreen_print_gpu_status_regs(struct radeon_device *rdev) in evergreen_print_gpu_status_regs() argument
3770 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3772 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3774 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3776 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3778 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3780 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3782 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3784 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3786 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3788 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3790 if (rdev->family >= CHIP_CAYMAN) { in evergreen_print_gpu_status_regs()
3791 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3796 bool evergreen_is_display_hung(struct radeon_device *rdev) in evergreen_is_display_hung() argument
3802 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3810 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3825 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev) in evergreen_gpu_check_soft_reset() argument
3877 if (evergreen_is_display_hung(rdev)) in evergreen_gpu_check_soft_reset()
3894 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in evergreen_gpu_soft_reset() argument
3903 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in evergreen_gpu_soft_reset()
3905 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
3919 evergreen_mc_stop(rdev, &save); in evergreen_gpu_soft_reset()
3920 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_soft_reset()
3921 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_gpu_soft_reset()
3966 if (!(rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_soft_reset()
3974 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
3988 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4002 evergreen_mc_resume(rdev, &save); in evergreen_gpu_soft_reset()
4005 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
4008 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev) in evergreen_gpu_pci_config_reset() argument
4013 dev_info(rdev->dev, "GPU pci config reset\n"); in evergreen_gpu_pci_config_reset()
4027 r600_rlc_stop(rdev); in evergreen_gpu_pci_config_reset()
4032 rv770_set_clk_bypass_mode(rdev); in evergreen_gpu_pci_config_reset()
4034 pci_clear_master(rdev->pdev); in evergreen_gpu_pci_config_reset()
4036 evergreen_mc_stop(rdev, &save); in evergreen_gpu_pci_config_reset()
4037 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_pci_config_reset()
4038 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in evergreen_gpu_pci_config_reset()
4041 radeon_pci_config_reset(rdev); in evergreen_gpu_pci_config_reset()
4043 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_gpu_pci_config_reset()
4050 int evergreen_asic_reset(struct radeon_device *rdev, bool hard) in evergreen_asic_reset() argument
4055 evergreen_gpu_pci_config_reset(rdev); in evergreen_asic_reset()
4059 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4062 r600_set_bios_scratch_engine_hung(rdev, true); in evergreen_asic_reset()
4065 evergreen_gpu_soft_reset(rdev, reset_mask); in evergreen_asic_reset()
4067 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4071 evergreen_gpu_pci_config_reset(rdev); in evergreen_asic_reset()
4073 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4076 r600_set_bios_scratch_engine_hung(rdev, false); in evergreen_asic_reset()
4090 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in evergreen_gfx_is_lockup() argument
4092 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_gfx_is_lockup()
4097 radeon_ring_lockup_update(rdev, ring); in evergreen_gfx_is_lockup()
4100 return radeon_ring_test_lockup(rdev, ring); in evergreen_gfx_is_lockup()
4109 void sumo_rlc_fini(struct radeon_device *rdev) in sumo_rlc_fini() argument
4114 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4115 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4117 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); in sumo_rlc_fini()
4118 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4119 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4121 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4126 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4127 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4129 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); in sumo_rlc_fini()
4130 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4131 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4133 radeon_bo_unref(&rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4134 rdev->rlc.clear_state_obj = NULL; in sumo_rlc_fini()
4138 if (rdev->rlc.cp_table_obj) { in sumo_rlc_fini()
4139 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_fini()
4141 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_fini()
4142 radeon_bo_unpin(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4143 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4145 radeon_bo_unref(&rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4146 rdev->rlc.cp_table_obj = NULL; in sumo_rlc_fini()
4152 int sumo_rlc_init(struct radeon_device *rdev) in sumo_rlc_init() argument
4162 src_ptr = rdev->rlc.reg_list; in sumo_rlc_init()
4163 dws = rdev->rlc.reg_list_size; in sumo_rlc_init()
4164 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4167 cs_data = rdev->rlc.cs_data; in sumo_rlc_init()
4171 if (rdev->rlc.save_restore_obj == NULL) { in sumo_rlc_init()
4172 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4174 NULL, &rdev->rlc.save_restore_obj); in sumo_rlc_init()
4176 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); in sumo_rlc_init()
4181 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_init()
4183 sumo_rlc_fini(rdev); in sumo_rlc_init()
4186 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4187 &rdev->rlc.save_restore_gpu_addr); in sumo_rlc_init()
4189 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4190 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); in sumo_rlc_init()
4191 sumo_rlc_fini(rdev); in sumo_rlc_init()
4195 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr); in sumo_rlc_init()
4197 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r); in sumo_rlc_init()
4198 sumo_rlc_fini(rdev); in sumo_rlc_init()
4202 dst_ptr = rdev->rlc.sr_ptr; in sumo_rlc_init()
4203 if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4205 for (i = 0; i < rdev->rlc.reg_list_size; i++) in sumo_rlc_init()
4225 radeon_bo_kunmap(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4226 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4231 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4232 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); in sumo_rlc_init()
4233 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4234 rdev->rlc.clear_state_size = si_get_csb_size(rdev); in sumo_rlc_init()
4235 dws = rdev->rlc.clear_state_size + (256 / 4); in sumo_rlc_init()
4247 rdev->rlc.clear_state_size = dws; in sumo_rlc_init()
4250 if (rdev->rlc.clear_state_obj == NULL) { in sumo_rlc_init()
4251 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4253 NULL, &rdev->rlc.clear_state_obj); in sumo_rlc_init()
4255 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); in sumo_rlc_init()
4256 sumo_rlc_fini(rdev); in sumo_rlc_init()
4260 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_init()
4262 sumo_rlc_fini(rdev); in sumo_rlc_init()
4265 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4266 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4268 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4269 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); in sumo_rlc_init()
4270 sumo_rlc_fini(rdev); in sumo_rlc_init()
4274 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); in sumo_rlc_init()
4276 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r); in sumo_rlc_init()
4277 sumo_rlc_fini(rdev); in sumo_rlc_init()
4281 dst_ptr = rdev->rlc.cs_ptr; in sumo_rlc_init()
4282 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4283 cik_get_csb_buffer(rdev, dst_ptr); in sumo_rlc_init()
4284 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4285 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4288 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); in sumo_rlc_init()
4289 si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); in sumo_rlc_init()
4292 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4321 radeon_bo_kunmap(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4322 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4325 if (rdev->rlc.cp_table_size) { in sumo_rlc_init()
4326 if (rdev->rlc.cp_table_obj == NULL) { in sumo_rlc_init()
4327 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, in sumo_rlc_init()
4330 NULL, &rdev->rlc.cp_table_obj); in sumo_rlc_init()
4332 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r); in sumo_rlc_init()
4333 sumo_rlc_fini(rdev); in sumo_rlc_init()
4338 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_init()
4340 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_init()
4341 sumo_rlc_fini(rdev); in sumo_rlc_init()
4344 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4345 &rdev->rlc.cp_table_gpu_addr); in sumo_rlc_init()
4347 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4348 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r); in sumo_rlc_init()
4349 sumo_rlc_fini(rdev); in sumo_rlc_init()
4352 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr); in sumo_rlc_init()
4354 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r); in sumo_rlc_init()
4355 sumo_rlc_fini(rdev); in sumo_rlc_init()
4359 cik_init_cp_pg_table(rdev); in sumo_rlc_init()
4361 radeon_bo_kunmap(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4362 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4369 static void evergreen_rlc_start(struct radeon_device *rdev) in evergreen_rlc_start() argument
4373 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_start()
4380 int evergreen_rlc_resume(struct radeon_device *rdev) in evergreen_rlc_resume() argument
4385 if (!rdev->rlc_fw) in evergreen_rlc_resume()
4388 r600_rlc_stop(rdev); in evergreen_rlc_resume()
4392 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_resume()
4393 if (rdev->family == CHIP_ARUBA) { in evergreen_rlc_resume()
4395 3 | (3 << (16 * rdev->config.cayman.max_shader_engines)); in evergreen_rlc_resume()
4398 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in evergreen_rlc_resume()
4400 if (tmp == rdev->config.cayman.max_simds_per_se) { in evergreen_rlc_resume()
4411 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4412 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4423 fw_data = (const __be32 *)rdev->rlc_fw->data; in evergreen_rlc_resume()
4424 if (rdev->family >= CHIP_ARUBA) { in evergreen_rlc_resume()
4429 } else if (rdev->family >= CHIP_CAYMAN) { in evergreen_rlc_resume()
4442 evergreen_rlc_start(rdev); in evergreen_rlc_resume()
4449 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) in evergreen_get_vblank_counter() argument
4451 if (crtc >= rdev->num_crtc) in evergreen_get_vblank_counter()
4457 void evergreen_disable_interrupt_state(struct radeon_device *rdev) in evergreen_disable_interrupt_state() argument
4462 if (rdev->family >= CHIP_CAYMAN) { in evergreen_disable_interrupt_state()
4463 cayman_cp_int_cntl_setup(rdev, 0, in evergreen_disable_interrupt_state()
4465 cayman_cp_int_cntl_setup(rdev, 1, 0); in evergreen_disable_interrupt_state()
4466 cayman_cp_int_cntl_setup(rdev, 2, 0); in evergreen_disable_interrupt_state()
4475 for (i = 0; i < rdev->num_crtc; i++) in evergreen_disable_interrupt_state()
4477 for (i = 0; i < rdev->num_crtc; i++) in evergreen_disable_interrupt_state()
4481 if (!ASIC_IS_DCE5(rdev)) in evergreen_disable_interrupt_state()
4490 int evergreen_irq_set(struct radeon_device *rdev) in evergreen_irq_set() argument
4499 if (!rdev->irq.installed) { in evergreen_irq_set()
4504 if (!rdev->ih.enabled) { in evergreen_irq_set()
4505 r600_disable_interrupts(rdev); in evergreen_irq_set()
4507 evergreen_disable_interrupt_state(rdev); in evergreen_irq_set()
4511 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4520 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4522 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4526 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in evergreen_irq_set()
4530 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { in evergreen_irq_set()
4535 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4542 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in evergreen_irq_set()
4547 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4549 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { in evergreen_irq_set()
4555 if (rdev->irq.dpm_thermal) { in evergreen_irq_set()
4560 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4561 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4562 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); in evergreen_irq_set()
4563 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); in evergreen_irq_set()
4569 if (rdev->family >= CHIP_CAYMAN) in evergreen_irq_set()
4574 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_irq_set()
4576 rdev, INT_MASK + crtc_offsets[i], in evergreen_irq_set()
4578 rdev->irq.crtc_vblank_int[i] || in evergreen_irq_set()
4579 atomic_read(&rdev->irq.pflip[i]), "vblank", i); in evergreen_irq_set()
4582 for (i = 0; i < rdev->num_crtc; i++) in evergreen_irq_set()
4587 rdev, DC_HPDx_INT_CONTROL(i), in evergreen_irq_set()
4589 rdev->irq.hpd[i], "HPD", i); in evergreen_irq_set()
4592 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4599 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_set()
4601 rdev->irq.afmt[i], "HDMI", i); in evergreen_irq_set()
4611 static void evergreen_irq_ack(struct radeon_device *rdev) in evergreen_irq_ack() argument
4614 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; in evergreen_irq_ack()
4615 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_ack()
4616 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; in evergreen_irq_ack()
4621 if (i < rdev->num_crtc) in evergreen_irq_ack()
4626 for (i = 0; i < rdev->num_crtc; i += 2) { in evergreen_irq_ack()
4660 static void evergreen_irq_disable(struct radeon_device *rdev) in evergreen_irq_disable() argument
4662 r600_disable_interrupts(rdev); in evergreen_irq_disable()
4665 evergreen_irq_ack(rdev); in evergreen_irq_disable()
4666 evergreen_disable_interrupt_state(rdev); in evergreen_irq_disable()
4669 void evergreen_irq_suspend(struct radeon_device *rdev) in evergreen_irq_suspend() argument
4671 evergreen_irq_disable(rdev); in evergreen_irq_suspend()
4672 r600_rlc_stop(rdev); in evergreen_irq_suspend()
4675 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) in evergreen_get_ih_wptr() argument
4679 if (rdev->wb.enabled) in evergreen_get_ih_wptr()
4680 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in evergreen_get_ih_wptr()
4690 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in evergreen_get_ih_wptr()
4691 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4692 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in evergreen_get_ih_wptr()
4697 return (wptr & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4700 int evergreen_irq_process(struct radeon_device *rdev) in evergreen_irq_process() argument
4702 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_process()
4703 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; in evergreen_irq_process()
4717 if (!rdev->ih.enabled || rdev->shutdown) in evergreen_irq_process()
4720 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
4724 if (atomic_xchg(&rdev->ih.lock, 1)) in evergreen_irq_process()
4727 rptr = rdev->ih.rptr; in evergreen_irq_process()
4734 evergreen_irq_ack(rdev); in evergreen_irq_process()
4739 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in evergreen_irq_process()
4740 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in evergreen_irq_process()
4755 if (rdev->irq.crtc_vblank_int[crtc_idx]) { in evergreen_irq_process()
4756 drm_handle_vblank(rdev_to_drm(rdev), crtc_idx); in evergreen_irq_process()
4757 rdev->pm.vblank_sync = true; in evergreen_irq_process()
4758 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
4760 if (atomic_read(&rdev->irq.pflip[crtc_idx])) { in evergreen_irq_process()
4761 radeon_crtc_handle_vblank(rdev, in evergreen_irq_process()
4791 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); in evergreen_irq_process()
4840 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in evergreen_irq_process()
4850 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); in evergreen_irq_process()
4851 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in evergreen_irq_process()
4853 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in evergreen_irq_process()
4855 cayman_vm_decode_fault(rdev, status, addr); in evergreen_irq_process()
4861 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4865 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
4868 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4871 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in evergreen_irq_process()
4874 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in evergreen_irq_process()
4878 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4882 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_irq_process()
4886 rdev->pm.dpm.thermal.high_to_low = false; in evergreen_irq_process()
4891 rdev->pm.dpm.thermal.high_to_low = true; in evergreen_irq_process()
4898 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
4900 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in evergreen_irq_process()
4910 rptr &= rdev->ih.ptr_mask; in evergreen_irq_process()
4914 schedule_work(&rdev->dp_work); in evergreen_irq_process()
4916 schedule_delayed_work(&rdev->hotplug_work, 0); in evergreen_irq_process()
4918 schedule_work(&rdev->audio_work); in evergreen_irq_process()
4919 if (queue_thermal && rdev->pm.dpm_enabled) in evergreen_irq_process()
4920 schedule_work(&rdev->pm.dpm.thermal.work); in evergreen_irq_process()
4921 rdev->ih.rptr = rptr; in evergreen_irq_process()
4922 atomic_set(&rdev->ih.lock, 0); in evergreen_irq_process()
4925 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
4932 static void evergreen_uvd_init(struct radeon_device *rdev) in evergreen_uvd_init() argument
4936 if (!rdev->has_uvd) in evergreen_uvd_init()
4939 r = radeon_uvd_init(rdev); in evergreen_uvd_init()
4941 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in evergreen_uvd_init()
4948 rdev->has_uvd = false; in evergreen_uvd_init()
4951 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in evergreen_uvd_init()
4952 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in evergreen_uvd_init()
4955 static void evergreen_uvd_start(struct radeon_device *rdev) in evergreen_uvd_start() argument
4959 if (!rdev->has_uvd) in evergreen_uvd_start()
4962 r = uvd_v2_2_resume(rdev); in evergreen_uvd_start()
4964 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in evergreen_uvd_start()
4967 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in evergreen_uvd_start()
4969 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in evergreen_uvd_start()
4975 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in evergreen_uvd_start()
4978 static void evergreen_uvd_resume(struct radeon_device *rdev) in evergreen_uvd_resume() argument
4983 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in evergreen_uvd_resume()
4986 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in evergreen_uvd_resume()
4987 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in evergreen_uvd_resume()
4989 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in evergreen_uvd_resume()
4992 r = uvd_v1_0_init(rdev); in evergreen_uvd_resume()
4994 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in evergreen_uvd_resume()
4999 static int evergreen_startup(struct radeon_device *rdev) in evergreen_startup() argument
5005 evergreen_pcie_gen2_enable(rdev); in evergreen_startup()
5007 evergreen_program_aspm(rdev); in evergreen_startup()
5010 r = r600_vram_scratch_init(rdev); in evergreen_startup()
5014 evergreen_mc_program(rdev); in evergreen_startup()
5016 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) { in evergreen_startup()
5017 r = ni_mc_load_microcode(rdev); in evergreen_startup()
5024 if (rdev->flags & RADEON_IS_AGP) { in evergreen_startup()
5025 evergreen_agp_enable(rdev); in evergreen_startup()
5027 r = evergreen_pcie_gart_enable(rdev); in evergreen_startup()
5031 evergreen_gpu_init(rdev); in evergreen_startup()
5034 if (rdev->flags & RADEON_IS_IGP) { in evergreen_startup()
5035 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list; in evergreen_startup()
5036 rdev->rlc.reg_list_size = in evergreen_startup()
5038 rdev->rlc.cs_data = evergreen_cs_data; in evergreen_startup()
5039 r = sumo_rlc_init(rdev); in evergreen_startup()
5047 r = radeon_wb_init(rdev); in evergreen_startup()
5051 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_startup()
5053 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in evergreen_startup()
5057 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_startup()
5059 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in evergreen_startup()
5063 evergreen_uvd_start(rdev); in evergreen_startup()
5066 if (!rdev->irq.installed) { in evergreen_startup()
5067 r = radeon_irq_kms_init(rdev); in evergreen_startup()
5072 r = r600_irq_init(rdev); in evergreen_startup()
5075 radeon_irq_kms_fini(rdev); in evergreen_startup()
5078 evergreen_irq_set(rdev); in evergreen_startup()
5080 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_startup()
5081 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in evergreen_startup()
5086 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in evergreen_startup()
5087 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in evergreen_startup()
5092 r = evergreen_cp_load_microcode(rdev); in evergreen_startup()
5095 r = evergreen_cp_resume(rdev); in evergreen_startup()
5098 r = r600_dma_resume(rdev); in evergreen_startup()
5102 evergreen_uvd_resume(rdev); in evergreen_startup()
5104 r = radeon_ib_pool_init(rdev); in evergreen_startup()
5106 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in evergreen_startup()
5110 r = radeon_audio_init(rdev); in evergreen_startup()
5119 int evergreen_resume(struct radeon_device *rdev) in evergreen_resume() argument
5126 if (radeon_asic_reset(rdev)) in evergreen_resume()
5127 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_resume()
5133 atom_asic_init(rdev->mode_info.atom_context); in evergreen_resume()
5136 evergreen_init_golden_registers(rdev); in evergreen_resume()
5138 if (rdev->pm.pm_method == PM_METHOD_DPM) in evergreen_resume()
5139 radeon_pm_resume(rdev); in evergreen_resume()
5141 rdev->accel_working = true; in evergreen_resume()
5142 r = evergreen_startup(rdev); in evergreen_resume()
5145 rdev->accel_working = false; in evergreen_resume()
5153 int evergreen_suspend(struct radeon_device *rdev) in evergreen_suspend() argument
5155 radeon_pm_suspend(rdev); in evergreen_suspend()
5156 radeon_audio_fini(rdev); in evergreen_suspend()
5157 if (rdev->has_uvd) { in evergreen_suspend()
5158 radeon_uvd_suspend(rdev); in evergreen_suspend()
5159 uvd_v1_0_fini(rdev); in evergreen_suspend()
5161 r700_cp_stop(rdev); in evergreen_suspend()
5162 r600_dma_stop(rdev); in evergreen_suspend()
5163 evergreen_irq_suspend(rdev); in evergreen_suspend()
5164 radeon_wb_disable(rdev); in evergreen_suspend()
5165 evergreen_pcie_gart_disable(rdev); in evergreen_suspend()
5176 int evergreen_init(struct radeon_device *rdev) in evergreen_init() argument
5181 if (!radeon_get_bios(rdev)) { in evergreen_init()
5182 if (ASIC_IS_AVIVO(rdev)) in evergreen_init()
5186 if (!rdev->is_atom_bios) { in evergreen_init()
5187 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); in evergreen_init()
5190 r = radeon_atombios_init(rdev); in evergreen_init()
5196 if (radeon_asic_reset(rdev)) in evergreen_init()
5197 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_init()
5199 if (!radeon_card_posted(rdev)) { in evergreen_init()
5200 if (!rdev->bios) { in evergreen_init()
5201 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in evergreen_init()
5205 atom_asic_init(rdev->mode_info.atom_context); in evergreen_init()
5208 evergreen_init_golden_registers(rdev); in evergreen_init()
5210 r600_scratch_init(rdev); in evergreen_init()
5212 radeon_surface_init(rdev); in evergreen_init()
5214 radeon_get_clock_info(rdev_to_drm(rdev)); in evergreen_init()
5216 radeon_fence_driver_init(rdev); in evergreen_init()
5218 if (rdev->flags & RADEON_IS_AGP) { in evergreen_init()
5219 r = radeon_agp_init(rdev); in evergreen_init()
5221 radeon_agp_disable(rdev); in evergreen_init()
5224 r = evergreen_mc_init(rdev); in evergreen_init()
5228 r = radeon_bo_init(rdev); in evergreen_init()
5232 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5233 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in evergreen_init()
5234 r = ni_init_microcode(rdev); in evergreen_init()
5241 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in evergreen_init()
5242 r = r600_init_microcode(rdev); in evergreen_init()
5251 radeon_pm_init(rdev); in evergreen_init()
5253 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in evergreen_init()
5254 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in evergreen_init()
5256 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in evergreen_init()
5257 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); in evergreen_init()
5259 evergreen_uvd_init(rdev); in evergreen_init()
5261 rdev->ih.ring_obj = NULL; in evergreen_init()
5262 r600_ih_ring_init(rdev, 64 * 1024); in evergreen_init()
5264 r = r600_pcie_gart_init(rdev); in evergreen_init()
5268 rdev->accel_working = true; in evergreen_init()
5269 r = evergreen_startup(rdev); in evergreen_init()
5271 dev_err(rdev->dev, "disabling GPU acceleration\n"); in evergreen_init()
5272 r700_cp_fini(rdev); in evergreen_init()
5273 r600_dma_fini(rdev); in evergreen_init()
5274 r600_irq_fini(rdev); in evergreen_init()
5275 if (rdev->flags & RADEON_IS_IGP) in evergreen_init()
5276 sumo_rlc_fini(rdev); in evergreen_init()
5277 radeon_wb_fini(rdev); in evergreen_init()
5278 radeon_ib_pool_fini(rdev); in evergreen_init()
5279 radeon_irq_kms_fini(rdev); in evergreen_init()
5280 evergreen_pcie_gart_fini(rdev); in evergreen_init()
5281 rdev->accel_working = false; in evergreen_init()
5288 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5289 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in evergreen_init()
5298 void evergreen_fini(struct radeon_device *rdev) in evergreen_fini() argument
5300 radeon_pm_fini(rdev); in evergreen_fini()
5301 radeon_audio_fini(rdev); in evergreen_fini()
5302 r700_cp_fini(rdev); in evergreen_fini()
5303 r600_dma_fini(rdev); in evergreen_fini()
5304 r600_irq_fini(rdev); in evergreen_fini()
5305 if (rdev->flags & RADEON_IS_IGP) in evergreen_fini()
5306 sumo_rlc_fini(rdev); in evergreen_fini()
5307 radeon_wb_fini(rdev); in evergreen_fini()
5308 radeon_ib_pool_fini(rdev); in evergreen_fini()
5309 radeon_irq_kms_fini(rdev); in evergreen_fini()
5310 uvd_v1_0_fini(rdev); in evergreen_fini()
5311 radeon_uvd_fini(rdev); in evergreen_fini()
5312 evergreen_pcie_gart_fini(rdev); in evergreen_fini()
5313 r600_vram_scratch_fini(rdev); in evergreen_fini()
5314 radeon_gem_fini(rdev); in evergreen_fini()
5315 radeon_fence_driver_fini(rdev); in evergreen_fini()
5316 radeon_agp_fini(rdev); in evergreen_fini()
5317 radeon_bo_fini(rdev); in evergreen_fini()
5318 radeon_atombios_fini(rdev); in evergreen_fini()
5319 kfree(rdev->bios); in evergreen_fini()
5320 rdev->bios = NULL; in evergreen_fini()
5323 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) in evergreen_pcie_gen2_enable() argument
5330 if (rdev->flags & RADEON_IS_IGP) in evergreen_pcie_gen2_enable()
5333 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_pcie_gen2_enable()
5337 if (ASIC_IS_X2(rdev)) in evergreen_pcie_gen2_enable()
5340 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in evergreen_pcie_gen2_enable()
5341 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in evergreen_pcie_gen2_enable()
5386 void evergreen_program_aspm(struct radeon_device *rdev) in evergreen_program_aspm() argument
5401 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_program_aspm()
5404 switch (rdev->family) { in evergreen_program_aspm()
5421 if (rdev->flags & RADEON_IS_IGP) in evergreen_program_aspm()
5443 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5450 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5480 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
5512 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
5529 if (rdev->family < CHIP_BARTS) in evergreen_program_aspm()