Lines Matching +full:clkf +full:- +full:- +full:-
58 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
75 if (!pi->boot_in_gen2) { in cypress_enable_bif_dynamic_pcie_gen2()
101 if (pi->gfx_clock_gating) {
124 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
149 if (eg_pi->light_sleep) { in cypress_gfx_clock_gating_enable()
179 if (rdev->family == CHIP_CEDAR) in cypress_mg_clock_gating_enable()
181 else if (rdev->family == CHIP_REDWOOD) in cypress_mg_clock_gating_enable()
193 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
196 if (eg_pi->mcls) { in cypress_mg_clock_gating_enable()
214 if (pi->mgcgtssm) in cypress_mg_clock_gating_enable()
225 if (pi->sclk_ss) in cypress_enable_spread_spectrum()
228 if (pi->mclk_ss) in cypress_enable_spread_spectrum()
268 return -EINVAL; in cypress_notify_smc_display_change()
315 eg_pi->pcie_performance_request_registered = true; in cypress_pcie_performance_request()
318 eg_pi->pcie_performance_request_registered) { in cypress_pcie_performance_request()
319 eg_pi->pcie_performance_request_registered = false; in cypress_pcie_performance_request()
340 pi->pcie_gen2 = true; in cypress_advertise_gen2_capability()
342 pi->pcie_gen2 = false; in cypress_advertise_gen2_capability()
344 if (!pi->pcie_gen2) in cypress_advertise_gen2_capability()
353 if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_get_maximum_link_speed()
408 for (i = 0; i < table->count; i++) { in cypress_populate_voltage_value()
409 if (value <= table->entries[i].value) { in cypress_populate_voltage_value()
410 voltage->index = (u8)i; in cypress_populate_voltage_value()
411 voltage->value = cpu_to_be16(table->entries[i].value); in cypress_populate_voltage_value()
416 if (i == table->count) in cypress_populate_voltage_value()
417 return -EINVAL; in cypress_populate_voltage_value()
428 if (pi->mem_gddr5) { in cypress_get_strobe_mode_settings()
429 if (mclk <= pi->mclk_strobe_mode_threshold) in cypress_get_strobe_mode_settings()
440 u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf) in cypress_map_clkf_to_ibias() argument
442 u32 ref_clk = rdev->clock.mpll.reference_freq; in cypress_map_clkf_to_ibias()
443 u32 vco = clkf * ref_clk; in cypress_map_clkf_to_ibias()
480 pi->clk_regs.rv770.mpll_ad_func_cntl; in cypress_populate_mclk_value()
482 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in cypress_populate_mclk_value()
484 pi->clk_regs.rv770.mpll_dq_func_cntl; in cypress_populate_mclk_value()
486 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in cypress_populate_mclk_value()
488 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in cypress_populate_mclk_value()
490 pi->clk_regs.rv770.dll_cntl; in cypress_populate_mclk_value()
491 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; in cypress_populate_mclk_value()
492 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
529 if (pi->mem_gddr5) { in cypress_populate_mclk_value()
537 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
552 if (pi->mclk_ss) { in cypress_populate_mclk_value()
558 u32 reference_clock = rdev->clock.mpll.reference_freq; in cypress_populate_mclk_value()
563 return -EINVAL; in cypress_populate_mclk_value()
576 dll_speed = rv740_get_dll_speed(pi->mem_gddr5, in cypress_populate_mclk_value()
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
601 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in cypress_populate_mclk_value()
602 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in cypress_populate_mclk_value()
603 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in cypress_populate_mclk_value()
604 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in cypress_populate_mclk_value()
605 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in cypress_populate_mclk_value()
606 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in cypress_populate_mclk_value()
607 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in cypress_populate_mclk_value()
608 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in cypress_populate_mclk_value()
618 if (rdev->family >= CHIP_BARTS) { in cypress_get_mclk_frequency_ratio()
625 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
632 mc_para_index = (u8)((memory_clock - 60000) / 5000); in cypress_get_mclk_frequency_ratio()
641 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
648 mc_para_index = (u8)((memory_clock - 40000) / 5000); in cypress_get_mclk_frequency_ratio()
661 if (!pi->mvdd_control) { in cypress_populate_mvdd_value()
662 voltage->index = eg_pi->mvdd_high_index; in cypress_populate_mvdd_value()
663 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in cypress_populate_mvdd_value()
667 if (mclk <= pi->mvdd_split_frequency) { in cypress_populate_mvdd_value()
668 voltage->index = eg_pi->mvdd_low_index; in cypress_populate_mvdd_value()
669 voltage->value = cpu_to_be16(MVDD_LOW_VALUE); in cypress_populate_mvdd_value()
671 voltage->index = eg_pi->mvdd_high_index; in cypress_populate_mvdd_value()
672 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in cypress_populate_mvdd_value()
688 level->gen2PCIE = pi->pcie_gen2 ? in cypress_convert_power_level_to_smc()
689 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0; in cypress_convert_power_level_to_smc()
690 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0; in cypress_convert_power_level_to_smc()
691 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0; in cypress_convert_power_level_to_smc()
692 level->displayWatermark = watermark_level; in cypress_convert_power_level_to_smc()
694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); in cypress_convert_power_level_to_smc()
698 level->mcFlags = 0; in cypress_convert_power_level_to_smc()
699 if (pi->mclk_stutter_mode_threshold && in cypress_convert_power_level_to_smc()
700 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in cypress_convert_power_level_to_smc()
701 !eg_pi->uvd_enabled) { in cypress_convert_power_level_to_smc()
702 level->mcFlags |= SMC_MC_STUTTER_EN; in cypress_convert_power_level_to_smc()
703 if (eg_pi->sclk_deep_sleep) in cypress_convert_power_level_to_smc()
704 level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP; in cypress_convert_power_level_to_smc()
706 level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP; in cypress_convert_power_level_to_smc()
709 if (pi->mem_gddr5) { in cypress_convert_power_level_to_smc()
710 if (pl->mclk > pi->mclk_edc_enable_threshold) in cypress_convert_power_level_to_smc()
711 level->mcFlags |= SMC_MC_EDC_RD_FLAG; in cypress_convert_power_level_to_smc()
713 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in cypress_convert_power_level_to_smc()
714 level->mcFlags |= SMC_MC_EDC_WR_FLAG; in cypress_convert_power_level_to_smc()
716 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk); in cypress_convert_power_level_to_smc()
718 if (level->strobeMode & SMC_STROBE_ENABLE) { in cypress_convert_power_level_to_smc()
719 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >= in cypress_convert_power_level_to_smc()
725 dll_state_on = eg_pi->dll_default_on; in cypress_convert_power_level_to_smc()
728 pl->sclk, in cypress_convert_power_level_to_smc()
729 pl->mclk, in cypress_convert_power_level_to_smc()
730 &level->mclk, in cypress_convert_power_level_to_smc()
731 (level->strobeMode & SMC_STROBE_ENABLE) != 0, in cypress_convert_power_level_to_smc()
735 pl->sclk, in cypress_convert_power_level_to_smc()
736 pl->mclk, in cypress_convert_power_level_to_smc()
737 &level->mclk, in cypress_convert_power_level_to_smc()
745 &eg_pi->vddc_voltage_table, in cypress_convert_power_level_to_smc()
746 pl->vddc, in cypress_convert_power_level_to_smc()
747 &level->vddc); in cypress_convert_power_level_to_smc()
751 if (eg_pi->vddci_control) { in cypress_convert_power_level_to_smc()
753 &eg_pi->vddci_voltage_table, in cypress_convert_power_level_to_smc()
754 pl->vddci, in cypress_convert_power_level_to_smc()
755 &level->vddci); in cypress_convert_power_level_to_smc()
760 ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in cypress_convert_power_level_to_smc()
773 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC)) in cypress_convert_power_state_to_smc()
774 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in cypress_convert_power_state_to_smc()
777 &state->low, in cypress_convert_power_state_to_smc()
778 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
784 &state->medium, in cypress_convert_power_state_to_smc()
785 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
791 &state->high, in cypress_convert_power_state_to_smc()
792 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
797 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
798 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
799 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
801 if (eg_pi->dynamic_ac_timing) { in cypress_convert_power_state_to_smc()
802 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
803 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
804 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
806 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
807 smc_state->levels[1].ACIndex = 0; in cypress_convert_power_state_to_smc()
808 smc_state->levels[2].ACIndex = 0; in cypress_convert_power_state_to_smc()
824 data->value[i] = cpu_to_be32(entry->mc_data[j]); in cypress_convert_mc_registers()
837 for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { in cypress_convert_mc_reg_table_entry_to_smc()
838 if (pl->mclk <= in cypress_convert_mc_reg_table_entry_to_smc()
839 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in cypress_convert_mc_reg_table_entry_to_smc()
843 if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) in cypress_convert_mc_reg_table_entry_to_smc()
844 --i; in cypress_convert_mc_reg_table_entry_to_smc()
846 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], in cypress_convert_mc_reg_table_entry_to_smc()
848 eg_pi->mc_reg_table.last, in cypress_convert_mc_reg_table_entry_to_smc()
849 eg_pi->mc_reg_table.valid_flag); in cypress_convert_mc_reg_table_entry_to_smc()
859 &state->low, in cypress_convert_mc_reg_table_to_smc()
860 &mc_reg_table->data[2]); in cypress_convert_mc_reg_table_to_smc()
862 &state->medium, in cypress_convert_mc_reg_table_to_smc()
863 &mc_reg_table->data[3]); in cypress_convert_mc_reg_table_to_smc()
865 &state->high, in cypress_convert_mc_reg_table_to_smc()
866 &mc_reg_table->data[4]); in cypress_convert_mc_reg_table_to_smc()
873 u16 address = pi->state_table_start + in cypress_upload_sw_state()
884 pi->sram_end); in cypress_upload_sw_state()
897 address = eg_pi->mc_reg_table_start + in cypress_upload_mc_reg_table()
903 pi->sram_end); in cypress_upload_mc_reg_table()
910 u32 multiplier = pi->mem_gddr5 ? 1 : 2; in cypress_calculate_burst_time()
917 burst_time = result - 4; in cypress_calculate_burst_time()
936 new_state->low.sclk, in cypress_program_memory_timing_parameters()
937 new_state->low.mclk)); in cypress_program_memory_timing_parameters()
939 new_state->medium.sclk, in cypress_program_memory_timing_parameters()
940 new_state->medium.mclk)); in cypress_program_memory_timing_parameters()
942 new_state->high.sclk, in cypress_program_memory_timing_parameters()
943 new_state->high.mclk)); in cypress_program_memory_timing_parameters()
956 for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { in cypress_populate_mc_reg_addresses()
957 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { in cypress_populate_mc_reg_addresses()
958 mc_reg_table->address[i].s0 = in cypress_populate_mc_reg_addresses()
959 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); in cypress_populate_mc_reg_addresses()
960 mc_reg_table->address[i].s1 = in cypress_populate_mc_reg_addresses()
961 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); in cypress_populate_mc_reg_addresses()
966 mc_reg_table->last = (u8)i; in cypress_populate_mc_reg_addresses()
974 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
975 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
978 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
979 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
982 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
983 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()
986 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table()
987 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; in cypress_set_mc_reg_address_table()
990 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
991 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
994 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
995 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
998 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
999 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
1002 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
1003 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
1006 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in cypress_set_mc_reg_address_table()
1007 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; in cypress_set_mc_reg_address_table()
1010 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in cypress_set_mc_reg_address_table()
1011 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; in cypress_set_mc_reg_address_table()
1014 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in cypress_set_mc_reg_address_table()
1015 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; in cypress_set_mc_reg_address_table()
1018 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1019 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1022 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1023 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1026 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1027 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1030 eg_pi->mc_reg_table.last = (u8)i; in cypress_set_mc_reg_address_table()
1039 for (i = 0; i < eg_pi->mc_reg_table.last; i++) in cypress_retrieve_ac_timing_for_one_entry()
1040 entry->mc_data[i] = in cypress_retrieve_ac_timing_for_one_entry()
1041 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_retrieve_ac_timing_for_one_entry()
1051 for (i = 0; i < range_table->num_entries; i++) { in cypress_retrieve_ac_timing_for_all_ranges()
1052 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = in cypress_retrieve_ac_timing_for_all_ranges()
1053 range_table->mclk[i]; in cypress_retrieve_ac_timing_for_all_ranges()
1054 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]); in cypress_retrieve_ac_timing_for_all_ranges()
1056 &eg_pi->mc_reg_table.mc_reg_table_entry[i]); in cypress_retrieve_ac_timing_for_all_ranges()
1059 eg_pi->mc_reg_table.num_entries = range_table->num_entries; in cypress_retrieve_ac_timing_for_all_ranges()
1060 eg_pi->mc_reg_table.valid_flag = 0; in cypress_retrieve_ac_timing_for_all_ranges()
1062 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_retrieve_ac_timing_for_all_ranges()
1063 for (j = 1; j < range_table->num_entries; j++) { in cypress_retrieve_ac_timing_for_all_ranges()
1064 if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != in cypress_retrieve_ac_timing_for_all_ranges()
1065 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { in cypress_retrieve_ac_timing_for_all_ranges()
1066 eg_pi->mc_reg_table.valid_flag |= (1 << i); in cypress_retrieve_ac_timing_for_all_ranges()
1081 pi->mem_gddr5, in cypress_initialize_mc_reg_table()
1096 if ((rdev->family == CHIP_CYPRESS) || in cypress_wait_for_mc_sequencer()
1097 (rdev->family == CHIP_HEMLOCK)) in cypress_wait_for_mc_sequencer()
1099 else if (rdev->family == CHIP_CEDAR) in cypress_wait_for_mc_sequencer()
1103 if ((rdev->family == CHIP_CYPRESS) || in cypress_wait_for_mc_sequencer()
1104 (rdev->family == CHIP_HEMLOCK)) { in cypress_wait_for_mc_sequencer()
1111 for (j = 0; j < rdev->usec_timeout; j++) { in cypress_wait_for_mc_sequencer()
1130 radeon_atom_set_ac_timing(rdev, boot_state->low.mclk); in cypress_force_mc_use_s1()
1133 if ((rdev->family == CHIP_CYPRESS) || in cypress_force_mc_use_s1()
1134 (rdev->family == CHIP_HEMLOCK)) { in cypress_force_mc_use_s1()
1142 for (i = 0; i < rdev->num_crtc; i++) in cypress_force_mc_use_s1()
1149 boot_state->low.mclk); in cypress_force_mc_use_s1()
1155 for (i = 0; i < rdev->usec_timeout; i++) { in cypress_force_mc_use_s1()
1174 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_copy_ac_timing_from_s1_to_s0()
1175 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_copy_ac_timing_from_s1_to_s0()
1176 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); in cypress_copy_ac_timing_from_s1_to_s0()
1191 if ((rdev->family == CHIP_CYPRESS) || in cypress_force_mc_use_s0()
1192 (rdev->family == CHIP_HEMLOCK)) { in cypress_force_mc_use_s0()
1200 for (i = 0; i < rdev->num_crtc; i++) in cypress_force_mc_use_s0()
1207 boot_state->low.mclk); in cypress_force_mc_use_s0()
1213 for (i = 0; i < rdev->usec_timeout; i++) { in cypress_force_mc_use_s0()
1231 voltage->index = eg_pi->mvdd_high_index; in cypress_populate_initial_mvdd_value()
1232 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE); in cypress_populate_initial_mvdd_value()
1246 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = in cypress_populate_smc_initial_state()
1247 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl); in cypress_populate_smc_initial_state()
1248 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = in cypress_populate_smc_initial_state()
1249 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2); in cypress_populate_smc_initial_state()
1250 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = in cypress_populate_smc_initial_state()
1251 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl); in cypress_populate_smc_initial_state()
1252 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = in cypress_populate_smc_initial_state()
1253 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2); in cypress_populate_smc_initial_state()
1254 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = in cypress_populate_smc_initial_state()
1255 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl); in cypress_populate_smc_initial_state()
1256 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL = in cypress_populate_smc_initial_state()
1257 cpu_to_be32(pi->clk_regs.rv770.dll_cntl); in cypress_populate_smc_initial_state()
1259 table->initialState.levels[0].mclk.mclk770.vMPLL_SS = in cypress_populate_smc_initial_state()
1260 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1); in cypress_populate_smc_initial_state()
1261 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 = in cypress_populate_smc_initial_state()
1262 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2); in cypress_populate_smc_initial_state()
1264 table->initialState.levels[0].mclk.mclk770.mclk_value = in cypress_populate_smc_initial_state()
1265 cpu_to_be32(initial_state->low.mclk); in cypress_populate_smc_initial_state()
1267 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in cypress_populate_smc_initial_state()
1268 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl); in cypress_populate_smc_initial_state()
1269 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in cypress_populate_smc_initial_state()
1270 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2); in cypress_populate_smc_initial_state()
1271 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in cypress_populate_smc_initial_state()
1272 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3); in cypress_populate_smc_initial_state()
1273 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = in cypress_populate_smc_initial_state()
1274 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum); in cypress_populate_smc_initial_state()
1275 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = in cypress_populate_smc_initial_state()
1276 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2); in cypress_populate_smc_initial_state()
1278 table->initialState.levels[0].sclk.sclk_value = in cypress_populate_smc_initial_state()
1279 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1281 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; in cypress_populate_smc_initial_state()
1283 table->initialState.levels[0].ACIndex = 0; in cypress_populate_smc_initial_state()
1286 &eg_pi->vddc_voltage_table, in cypress_populate_smc_initial_state()
1287 initial_state->low.vddc, in cypress_populate_smc_initial_state()
1288 &table->initialState.levels[0].vddc); in cypress_populate_smc_initial_state()
1290 if (eg_pi->vddci_control) in cypress_populate_smc_initial_state()
1292 &eg_pi->vddci_voltage_table, in cypress_populate_smc_initial_state()
1293 initial_state->low.vddci, in cypress_populate_smc_initial_state()
1294 &table->initialState.levels[0].vddci); in cypress_populate_smc_initial_state()
1297 &table->initialState.levels[0].mvdd); in cypress_populate_smc_initial_state()
1300 table->initialState.levels[0].aT = cpu_to_be32(a_t); in cypress_populate_smc_initial_state()
1302 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); in cypress_populate_smc_initial_state()
1305 if (pi->boot_in_gen2) in cypress_populate_smc_initial_state()
1306 table->initialState.levels[0].gen2PCIE = 1; in cypress_populate_smc_initial_state()
1308 table->initialState.levels[0].gen2PCIE = 0; in cypress_populate_smc_initial_state()
1309 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_populate_smc_initial_state()
1310 table->initialState.levels[0].gen2XSP = 1; in cypress_populate_smc_initial_state()
1312 table->initialState.levels[0].gen2XSP = 0; in cypress_populate_smc_initial_state()
1314 if (pi->mem_gddr5) { in cypress_populate_smc_initial_state()
1315 table->initialState.levels[0].strobeMode = in cypress_populate_smc_initial_state()
1317 initial_state->low.mclk); in cypress_populate_smc_initial_state()
1319 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) in cypress_populate_smc_initial_state()
1320 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG; in cypress_populate_smc_initial_state()
1322 table->initialState.levels[0].mcFlags = 0; in cypress_populate_smc_initial_state()
1325 table->initialState.levels[1] = table->initialState.levels[0]; in cypress_populate_smc_initial_state()
1326 table->initialState.levels[2] = table->initialState.levels[0]; in cypress_populate_smc_initial_state()
1328 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; in cypress_populate_smc_initial_state()
1339 pi->clk_regs.rv770.mpll_ad_func_cntl; in cypress_populate_smc_acpi_state()
1341 pi->clk_regs.rv770.mpll_ad_func_cntl_2; in cypress_populate_smc_acpi_state()
1343 pi->clk_regs.rv770.mpll_dq_func_cntl; in cypress_populate_smc_acpi_state()
1345 pi->clk_regs.rv770.mpll_dq_func_cntl_2; in cypress_populate_smc_acpi_state()
1347 pi->clk_regs.rv770.cg_spll_func_cntl; in cypress_populate_smc_acpi_state()
1349 pi->clk_regs.rv770.cg_spll_func_cntl_2; in cypress_populate_smc_acpi_state()
1351 pi->clk_regs.rv770.cg_spll_func_cntl_3; in cypress_populate_smc_acpi_state()
1353 pi->clk_regs.rv770.mclk_pwrmgt_cntl; in cypress_populate_smc_acpi_state()
1355 pi->clk_regs.rv770.dll_cntl; in cypress_populate_smc_acpi_state()
1357 table->ACPIState = table->initialState; in cypress_populate_smc_acpi_state()
1359 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; in cypress_populate_smc_acpi_state()
1361 if (pi->acpi_vddc) { in cypress_populate_smc_acpi_state()
1363 &eg_pi->vddc_voltage_table, in cypress_populate_smc_acpi_state()
1364 pi->acpi_vddc, in cypress_populate_smc_acpi_state()
1365 &table->ACPIState.levels[0].vddc); in cypress_populate_smc_acpi_state()
1366 if (pi->pcie_gen2) { in cypress_populate_smc_acpi_state()
1367 if (pi->acpi_pcie_gen2) in cypress_populate_smc_acpi_state()
1368 table->ACPIState.levels[0].gen2PCIE = 1; in cypress_populate_smc_acpi_state()
1370 table->ACPIState.levels[0].gen2PCIE = 0; in cypress_populate_smc_acpi_state()
1372 table->ACPIState.levels[0].gen2PCIE = 0; in cypress_populate_smc_acpi_state()
1373 if (pi->acpi_pcie_gen2) in cypress_populate_smc_acpi_state()
1374 table->ACPIState.levels[0].gen2XSP = 1; in cypress_populate_smc_acpi_state()
1376 table->ACPIState.levels[0].gen2XSP = 0; in cypress_populate_smc_acpi_state()
1379 &eg_pi->vddc_voltage_table, in cypress_populate_smc_acpi_state()
1380 pi->min_vddc_in_table, in cypress_populate_smc_acpi_state()
1381 &table->ACPIState.levels[0].vddc); in cypress_populate_smc_acpi_state()
1382 table->ACPIState.levels[0].gen2PCIE = 0; in cypress_populate_smc_acpi_state()
1385 if (eg_pi->acpi_vddci) { in cypress_populate_smc_acpi_state()
1386 if (eg_pi->vddci_control) { in cypress_populate_smc_acpi_state()
1388 &eg_pi->vddci_voltage_table, in cypress_populate_smc_acpi_state()
1389 eg_pi->acpi_vddci, in cypress_populate_smc_acpi_state()
1390 &table->ACPIState.levels[0].vddci); in cypress_populate_smc_acpi_state()
1398 if (pi->mem_gddr5) in cypress_populate_smc_acpi_state()
1430 if (rdev->family <= CHIP_HEMLOCK) in cypress_populate_smc_acpi_state()
1436 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = in cypress_populate_smc_acpi_state()
1438 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = in cypress_populate_smc_acpi_state()
1440 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = in cypress_populate_smc_acpi_state()
1442 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = in cypress_populate_smc_acpi_state()
1444 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = in cypress_populate_smc_acpi_state()
1446 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in cypress_populate_smc_acpi_state()
1448 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; in cypress_populate_smc_acpi_state()
1450 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in cypress_populate_smc_acpi_state()
1452 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in cypress_populate_smc_acpi_state()
1454 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = in cypress_populate_smc_acpi_state()
1457 table->ACPIState.levels[0].sclk.sclk_value = 0; in cypress_populate_smc_acpi_state()
1459 cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); in cypress_populate_smc_acpi_state()
1461 if (eg_pi->dynamic_ac_timing) in cypress_populate_smc_acpi_state()
1462 table->ACPIState.levels[0].ACIndex = 1; in cypress_populate_smc_acpi_state()
1464 table->ACPIState.levels[1] = table->ACPIState.levels[0]; in cypress_populate_smc_acpi_state()
1465 table->ACPIState.levels[2] = table->ACPIState.levels[0]; in cypress_populate_smc_acpi_state()
1475 if (voltage_table->count <= MAX_NO_VREG_STEPS) in cypress_trim_voltage_table_to_fit_state_table()
1478 diff = voltage_table->count - MAX_NO_VREG_STEPS; in cypress_trim_voltage_table_to_fit_state_table()
1481 voltage_table->entries[i] = voltage_table->entries[i + diff]; in cypress_trim_voltage_table_to_fit_state_table()
1483 voltage_table->count = MAX_NO_VREG_STEPS; in cypress_trim_voltage_table_to_fit_state_table()
1492 &eg_pi->vddc_voltage_table); in cypress_construct_voltage_tables()
1496 if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS) in cypress_construct_voltage_tables()
1498 &eg_pi->vddc_voltage_table); in cypress_construct_voltage_tables()
1500 if (eg_pi->vddci_control) { in cypress_construct_voltage_tables()
1502 &eg_pi->vddci_voltage_table); in cypress_construct_voltage_tables()
1506 if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS) in cypress_construct_voltage_tables()
1508 &eg_pi->vddci_voltage_table); in cypress_construct_voltage_tables()
1520 for (i = 0; i < voltage_table->count; i++) { in cypress_populate_smc_voltage_table()
1521 table->highSMIO[i] = 0; in cypress_populate_smc_voltage_table()
1522 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); in cypress_populate_smc_voltage_table()
1533 if (eg_pi->vddc_voltage_table.count) { in cypress_populate_smc_voltage_tables()
1535 &eg_pi->vddc_voltage_table, in cypress_populate_smc_voltage_tables()
1538 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0; in cypress_populate_smc_voltage_tables()
1539 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] = in cypress_populate_smc_voltage_tables()
1540 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); in cypress_populate_smc_voltage_tables()
1542 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { in cypress_populate_smc_voltage_tables()
1543 if (pi->max_vddc_in_table <= in cypress_populate_smc_voltage_tables()
1544 eg_pi->vddc_voltage_table.entries[i].value) { in cypress_populate_smc_voltage_tables()
1545 table->maxVDDCIndexInPPTable = i; in cypress_populate_smc_voltage_tables()
1551 if (eg_pi->vddci_voltage_table.count) { in cypress_populate_smc_voltage_tables()
1553 &eg_pi->vddci_voltage_table, in cypress_populate_smc_voltage_tables()
1556 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0; in cypress_populate_smc_voltage_tables()
1557 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] = in cypress_populate_smc_voltage_tables()
1558 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); in cypress_populate_smc_voltage_tables()
1566 if ((memory_info->mem_type == MEM_TYPE_GDDR3) || in cypress_get_mclk_split_point()
1567 (memory_info->mem_type == MEM_TYPE_DDR3)) in cypress_get_mclk_split_point()
1582 eg_pi->mvdd_high_index = 0; in cypress_get_mvdd_configuration()
1583 eg_pi->mvdd_low_index = 1; in cypress_get_mvdd_configuration()
1584 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1589 eg_pi->mvdd_high_index = 1; in cypress_get_mvdd_configuration()
1591 eg_pi->mvdd_high_index = 0; in cypress_get_mvdd_configuration()
1593 eg_pi->mvdd_low_index = in cypress_get_mvdd_configuration()
1594 (eg_pi->mvdd_high_index == 0) ? 1 : 0; in cypress_get_mvdd_configuration()
1599 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1603 pi->mvdd_split_frequency = in cypress_get_mvdd_configuration()
1606 if (pi->mvdd_split_frequency == 0) { in cypress_get_mvdd_configuration()
1607 pi->mvdd_control = false; in cypress_get_mvdd_configuration()
1618 RV770_SMC_STATETABLE *table = &pi->smc_statetable; in cypress_init_smc_table()
1625 switch (rdev->pm.int_thermal_type) { in cypress_init_smc_table()
1628 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; in cypress_init_smc_table()
1631 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; in cypress_init_smc_table()
1634 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; in cypress_init_smc_table()
1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in cypress_init_smc_table()
1639 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in cypress_init_smc_table()
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in cypress_init_smc_table()
1642 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; in cypress_init_smc_table()
1644 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in cypress_init_smc_table()
1645 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in cypress_init_smc_table()
1647 if (pi->mem_gddr5) in cypress_init_smc_table()
1648 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in cypress_init_smc_table()
1658 table->driverState = table->initialState; in cypress_init_smc_table()
1661 pi->state_table_start, in cypress_init_smc_table()
1663 pi->sram_end); in cypress_init_smc_table()
1680 &boot_state->low, in cypress_populate_mc_reg_table()
1683 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], in cypress_populate_mc_reg_table()
1684 &mc_reg_table.data[1], eg_pi->mc_reg_table.last, in cypress_populate_mc_reg_table()
1685 eg_pi->mc_reg_table.valid_flag); in cypress_populate_mc_reg_table()
1689 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start, in cypress_populate_mc_reg_table()
1691 pi->sram_end); in cypress_populate_mc_reg_table()
1704 &tmp, pi->sram_end); in cypress_get_table_locations()
1708 pi->state_table_start = (u16)tmp; in cypress_get_table_locations()
1713 &tmp, pi->sram_end); in cypress_get_table_locations()
1717 pi->soft_regs_start = (u16)tmp; in cypress_get_table_locations()
1722 &tmp, pi->sram_end); in cypress_get_table_locations()
1726 eg_pi->mc_reg_table_start = (u16)tmp; in cypress_get_table_locations()
1751 if (rdev->pm.dpm.new_active_crtc_count > 0) in cypress_program_display_gap()
1756 if (rdev->pm.dpm.new_active_crtc_count > 1) in cypress_program_display_gap()
1766 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in cypress_program_display_gap()
1767 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in cypress_program_display_gap()
1769 for (i = 0; i < rdev->num_crtc; i++) { in cypress_program_display_gap()
1770 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in cypress_program_display_gap()
1773 if (i == rdev->num_crtc) in cypress_program_display_gap()
1783 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in cypress_program_display_gap()
1795 if (eg_pi->pcie_performance_request) in cypress_dpm_setup_asic()
1796 eg_pi->pcie_performance_request_registered = false; in cypress_dpm_setup_asic()
1798 if (eg_pi->pcie_performance_request) in cypress_dpm_setup_asic()
1810 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in cypress_dpm_enable()
1813 if (pi->gfx_clock_gating) in cypress_dpm_enable()
1817 return -EINVAL; in cypress_dpm_enable()
1819 if (pi->voltage_control) { in cypress_dpm_enable()
1828 if (pi->mvdd_control) { in cypress_dpm_enable()
1836 if (eg_pi->dynamic_ac_timing) { in cypress_dpm_enable()
1841 eg_pi->dynamic_ac_timing = false; in cypress_dpm_enable()
1845 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in cypress_dpm_enable()
1848 if (pi->dynamic_ss) in cypress_dpm_enable()
1851 if (pi->thermal_protection) in cypress_dpm_enable()
1863 if (pi->dynamic_pcie_gen2) in cypress_dpm_enable()
1882 if (eg_pi->dynamic_ac_timing) { in cypress_dpm_enable()
1901 if (eg_pi->memory_transition) in cypress_dpm_enable()
1906 if (pi->gfx_clock_gating) in cypress_dpm_enable()
1909 if (pi->mg_clock_gating) in cypress_dpm_enable()
1921 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in cypress_dpm_disable()
1928 if (pi->thermal_protection) in cypress_dpm_disable()
1931 if (pi->dynamic_pcie_gen2) in cypress_dpm_disable()
1934 if (rdev->irq.installed && in cypress_dpm_disable()
1935 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in cypress_dpm_disable()
1936 rdev->irq.dpm_thermal = false; in cypress_dpm_disable()
1940 if (pi->gfx_clock_gating) in cypress_dpm_disable()
1943 if (pi->mg_clock_gating) in cypress_dpm_disable()
1951 if (eg_pi->dynamic_ac_timing) in cypress_dpm_disable()
1960 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in cypress_dpm_set_power_state()
1961 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in cypress_dpm_set_power_state()
1969 if (eg_pi->pcie_performance_request) in cypress_dpm_set_power_state()
1983 if (eg_pi->dynamic_ac_timing) { in cypress_dpm_set_power_state()
2005 if (eg_pi->pcie_performance_request) in cypress_dpm_set_power_state()
2033 return -ENOMEM; in cypress_dpm_init()
2034 rdev->pm.dpm.priv = eg_pi; in cypress_dpm_init()
2035 pi = &eg_pi->rv7xx; in cypress_dpm_init()
2039 eg_pi->ulv.supported = false; in cypress_dpm_init()
2040 pi->acpi_vddc = 0; in cypress_dpm_init()
2041 eg_pi->acpi_vddci = 0; in cypress_dpm_init()
2042 pi->min_vddc_in_table = 0; in cypress_dpm_init()
2043 pi->max_vddc_in_table = 0; in cypress_dpm_init()
2053 if (rdev->pm.dpm.voltage_response_time == 0) in cypress_dpm_init()
2054 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in cypress_dpm_init()
2055 if (rdev->pm.dpm.backbias_response_time == 0) in cypress_dpm_init()
2056 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in cypress_dpm_init()
2061 pi->ref_div = dividers.ref_div + 1; in cypress_dpm_init()
2063 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in cypress_dpm_init()
2065 pi->mclk_strobe_mode_threshold = 40000; in cypress_dpm_init()
2066 pi->mclk_edc_enable_threshold = 40000; in cypress_dpm_init()
2067 eg_pi->mclk_edc_wr_enable_threshold = 40000; in cypress_dpm_init()
2069 pi->rlp = RV770_RLP_DFLT; in cypress_dpm_init()
2070 pi->rmp = RV770_RMP_DFLT; in cypress_dpm_init()
2071 pi->lhp = RV770_LHP_DFLT; in cypress_dpm_init()
2072 pi->lmp = RV770_LMP_DFLT; in cypress_dpm_init()
2074 pi->voltage_control = in cypress_dpm_init()
2077 pi->mvdd_control = in cypress_dpm_init()
2080 eg_pi->vddci_control = in cypress_dpm_init()
2085 pi->asi = RV770_ASI_DFLT; in cypress_dpm_init()
2086 pi->pasi = CYPRESS_HASI_DFLT; in cypress_dpm_init()
2087 pi->vrc = CYPRESS_VRC_DFLT; in cypress_dpm_init()
2089 pi->power_gating = false; in cypress_dpm_init()
2091 if ((rdev->family == CHIP_CYPRESS) || in cypress_dpm_init()
2092 (rdev->family == CHIP_HEMLOCK)) in cypress_dpm_init()
2093 pi->gfx_clock_gating = false; in cypress_dpm_init()
2095 pi->gfx_clock_gating = true; in cypress_dpm_init()
2097 pi->mg_clock_gating = true; in cypress_dpm_init()
2098 pi->mgcgtssm = true; in cypress_dpm_init()
2099 eg_pi->ls_clock_gating = false; in cypress_dpm_init()
2100 eg_pi->sclk_deep_sleep = false; in cypress_dpm_init()
2102 pi->dynamic_pcie_gen2 = true; in cypress_dpm_init()
2104 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in cypress_dpm_init()
2105 pi->thermal_protection = true; in cypress_dpm_init()
2107 pi->thermal_protection = false; in cypress_dpm_init()
2109 pi->display_gap = true; in cypress_dpm_init()
2111 if (rdev->flags & RADEON_IS_MOBILITY) in cypress_dpm_init()
2112 pi->dcodt = true; in cypress_dpm_init()
2114 pi->dcodt = false; in cypress_dpm_init()
2116 pi->ulps = true; in cypress_dpm_init()
2118 eg_pi->dynamic_ac_timing = true; in cypress_dpm_init()
2119 eg_pi->abm = true; in cypress_dpm_init()
2120 eg_pi->mcls = true; in cypress_dpm_init()
2121 eg_pi->light_sleep = true; in cypress_dpm_init()
2122 eg_pi->memory_transition = true; in cypress_dpm_init()
2124 eg_pi->pcie_performance_request = in cypress_dpm_init()
2127 eg_pi->pcie_performance_request = false; in cypress_dpm_init()
2130 if ((rdev->family == CHIP_CYPRESS) || in cypress_dpm_init()
2131 (rdev->family == CHIP_HEMLOCK) || in cypress_dpm_init()
2132 (rdev->family == CHIP_JUNIPER)) in cypress_dpm_init()
2133 eg_pi->dll_default_on = true; in cypress_dpm_init()
2135 eg_pi->dll_default_on = false; in cypress_dpm_init()
2137 eg_pi->sclk_deep_sleep = false; in cypress_dpm_init()
2138 pi->mclk_stutter_mode_threshold = 0; in cypress_dpm_init()
2140 pi->sram_end = SMC_RAM_END; in cypress_dpm_init()
2149 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in cypress_dpm_fini()
2150 kfree(rdev->pm.dpm.ps[i].ps_priv); in cypress_dpm_fini()
2152 kfree(rdev->pm.dpm.ps); in cypress_dpm_fini()
2153 kfree(rdev->pm.dpm.priv); in cypress_dpm_fini()
2160 /* we never hit the non-gddr5 limit so disable it */ in cypress_dpm_vblank_too_short()
2161 u32 switch_limit = pi->mem_gddr5 ? 450 : 0; in cypress_dpm_vblank_too_short()