drm/radeon/cikd.h

743 #define		CLKF(x)					((x) << 16)  macro
983         /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
990 #       define FMT_TRUNCATE_DEPTH(x)         ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
993 #       define FMT_SPATIAL_DITHER_DEPTH(x)   ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
998 #       define FMT_TEMPORAL_DITHER_DEPTH(x)  ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
1729                 /* 0 - register
1730 		 * 1 - memory (sync - via GRBM)
1731 		 * 2 - gl2
1732 		 * 3 - gds
1733 		 * 4 - reserved
1734 		 * 5 - memory (async - direct)
1739                 /* 0 - LRU
1740 		 * 1 - Stream
1743                 /* 0 - me
1744 		 * 1 - pfp
1745 		 * 2 - ce
1757                 /* 0 - always
1758 		 * 1 - <
1759 		 * 2 - <=
1760 		 * 3 - ==
1761 		 * 4 - !=
1762 		 * 5 - >=
1763 		 * 6 - >
1766                 /* 0 - reg
1767 		 * 1 - mem
1770                 /* 0 - wait_reg_mem
1771 		 * 1 - wr_wait_wr_reg
1774                 /* 0 - me
1775 		 * 1 - pfp
1781                 /* 0 - LRU
1782 		 * 1 - Stream
1783 		 * 2 - Bypass
1815                 /* 0 - any non-TS event
1816 		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1817 		 * 2 - SAMPLE_PIPELINESTAT
1818 		 * 3 - SAMPLE_STREAMOUTSTAT*
1819 		 * 4 - *S_PARTIAL_FLUSH
1820 		 * 5 - EOP events
1821 		 * 6 - EOS events
1831                 /* 0 - LRU
1832 		 * 1 - Stream
1833 		 * 2 - Bypass
1836                 /* 0 - discard
1837 		 * 1 - send low 32bit data
1838 		 * 2 - send 64bit data
1839 		 * 3 - send 64bit GPU counter value
1840 		 * 4 - send 64bit sys counter value
1843                 /* 0 - none
1844 		 * 1 - interrupt only (DATA_SEL = 0)
1845 		 * 2 - interrupt when data write is confirmed
1848                 /* 0 - MC
1849 		 * 1 - TC/L2
1867                 /* 0 - ME
1868 		 * 1 - PFP
1871                 /* 0 - LRU
1872 		 * 1 - Stream
1873 		 * 2 - Bypass
1877                 /* 0 - DST_ADDR using DAS
1878 		 * 1 - GDS
1879 		 * 3 - DST_ADDR using L2
1882                 /* 0 - LRU
1883 		 * 1 - Stream
1884 		 * 2 - Bypass
1888                 /* 0 - SRC_ADDR using SAS
1889 		 * 1 - GDS
1890 		 * 2 - DATA
1891 		 * 3 - SRC_ADDR using L2
1897                 /* 0 - none
1898 		 * 1 - 8 in 16
1899 		 * 2 - 8 in 32
1900 		 * 3 - 8 in 64
1903                 /* 0 - none
1904 		 * 1 - 8 in 16
1905 		 * 2 - 8 in 32
1906 		 * 3 - 8 in 64
1909                 /* 0 - memory
1910 		 * 1 - register
1913                 /* 0 - memory
1914 		 * 1 - register
1951 /* SDMA - first instance at 0xd000, second at 0xd800 */
2023                 /* 0 - increment
2024 		 * 1 - write 1
2027                 /* 0 - wait
2028 		 * 1 - signal
2034                 /* 0 - wait_reg_mem
2035 		 * 1 - wr_wait_wr_reg
2038                 /* 0 - always
2039 		 * 1 - <
2040 		 * 2 - <=
2041 		 * 3 - ==
2042 		 * 4 - !=
2043 		 * 5 - >=
2044 		 * 6 - >