7051 	cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7052 	cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7053 	cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7054 	cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7055 	cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7056 	cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7057 	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7058 	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7063 		cp_int_cntl |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7071 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7074 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7077 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7080 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7089 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7092 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7095 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7098 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7114 				cp_m1p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7117 				cp_m1p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7120 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7123 				cp_m1p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7132 				cp_m2p0 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7135 				cp_m2p1 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7138 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()
7141 				cp_m2p2 |= TIME_STAMP_INT_ENABLE;  in cik_irq_set()