Lines Matching refs:performance_level_count

800 		for (i = 0; i < ps->performance_level_count; i++) {  in ci_apply_state_adjust_rules()
811 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
3712 	if (state->performance_level_count < 1)  in ci_trim_dpm_states()
3715 	if (state->performance_level_count == 1)  in ci_trim_dpm_states()
3817 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3819 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3858 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3859 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4760 	for (i = 0; i < state->performance_level_count; i++) {  in ci_get_maximum_link_speed()
5438 	ps->performance_level_count = index + 1;  in ci_parse_pplib_clock_info()
5933 	for (i = 0; i < ps->performance_level_count; i++) {  in ci_dpm_print_power_state()
5963 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
5974 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()